Fault diagnosis and its prediction in wireless sensor networks using regressional learning to achieve fault tolerance

Due to the wide range of critical applications and resource constraints, sensor node gives unexpected responses, which leads to various kind of faults in sensor node and failure in wireless sensor networks. Many research studies focus only on fault diagnosis, and comparatively limited studies have been conducted on fault diagnosis along with fault tolerance in sensor networks. This paper reports a complete study on both 2 aspects and presents a fault tolerance approach using regressional learning with fault diagnosis in wireless sensor networks. The proposed method diagnose the different types of faulty nodes such as hard permanent, soft permanent, intermittent, and transient faults with better detection accuracy. The proposed method follows a fault tolerance phase where faulty sensor node values would be predicted by using the data sensed by the fault free neighbors. The experimental evaluation of the fault tolerance module shows promising results with R² of more than 0.99. For the periodic fault such as intermittent fault, the proposed method also predict the possible occurrence time and its duration of the faulty node, so that fault tolerance can be achieved at that particular time period for better performance of the network.     

基于电压暂降测量的配电网故障自动定位

文中提出了一种结合电力系统分析程序、数据库检索方法和模式识别技术自动识别的11kV配电网故障定位方法。该方法采用三相不平衡潮流和故障分析程序,对配电网各节点的故障进行分析生成电压暂降数据库,设计了数据库搜索和模式识别算法,以便配电网在发生实际故障时识别故障位置。利用电力系统EMTDC模拟器对该方法进行了评估和测试。实验结果表明,提出的线性模式识别算法能够识别所研究的11kV配电网的大部分故障区段。     

A Novel Dynamic Fault Restoration Mechanism Using a Multiple Ring Approach in WDM Mesh Networks

This work describes a distributed fault restoration algorithm, called the Dynamic Multiple Ring Algorithm (DMRA), for application in WDM mesh networks. This study explores the choice of restoration paths and the assignment of fault-tolerant bandwidth when a link, node, or channel failure occurs according to the change in traffic load, number of nodes, and transmission delay including propagation and switching delays. Accordingly, the primary aim of this work is to use networking segments near faults to share the restoration load throughout a mesh network. Each node searches for restoration paths in their near environment using the proposed DMRA. Nodes use distributed control to search for neighboring nodes and to establish the relationship between them to build numerous logical rings. Nodes can also locate faults in the logical rings. These rings establish the restoration paths. The traffic load over failed links or nodes can be diverted to other paths in the networking segments. The cost of the restoration paths is computed at each node based on both the current capacity and the transmission delay. The selected restoration paths are suitable transmission routes in the network neighborhood. Hence, restoration paths can be identified and wavelength assigned quickly according to network bandwidth and traffic load. Simulation results reveal that the proposed method works extremely quickly and has a high success rate. Consequently, it is very useful for applications in real WDM networks, where the status varies from minute to minute.Corresponding author is presently a guest scientist with the National Institute of Standards and Technology, USA. This research was partially supported by the Grant of National Science Council, ROC (NSC-92-2218-E-155-004 and NSC-93-2917-I-155-001).     

On Selecting Testable Paths in Scan Designs

We propose an efficient method to select a minimal set of testable paths in scan designs, such that every line in the circuit is covered by at least one of the longest testable paths that contain it (if there are any). The proposed path selection approach is based on a stepwise path expansion procedure that uses delay information and compact information about untestable paths to select longest paths while avoiding untestable paths. Techniques called delay analysis and delay-constrained path expansion are used to speedup the selection of paths to test. Compared to earlier approaches, the proposed approach is fast and it is guaranteed to find testable paths. Additionally the procedure also derives tests for the selected paths. Experimental results for ISCAS89 benchmark circuits using standard scan and broadside testing are presented to demonstrate the effectiveness of the proposed method.     

An advanced diagnostic method for delay faults in combinational faulty circuits

Due to physical defects or process variations, a logic circuit may fail to operate at the desired clock speed. So, verifying the timing behavior of digital circuits is always necessary, and needs to test for delay faults. When a delay fault has been detected, a specific diagnostic method is required to locate the site of the fault in the circuit. So, a reliable method for delay fault diagnosis is proposed in this paper. Firstly, we present the basic diagnostic method for delay faults, which is based on multivalued simulation and critical path tracing. Next, heuristics are given that decrease the number of critical paths and improve diagnosis results. In the second part of this paper, we provide an approximate method to refine the results obtained with the basic diagnostic process. We compute the detection threshold of the potential delay faults, and use statistical studies to classify the faults from the most likely to be the cause of failure to the less likely. Finally, results obtained with ISCAS'85 circuits are presented to show the effectiveness of the method.     

Ball grid array (BGA) solder joint intermittency real-time detection

This paper presents test results and specifications for SJ BIST (solder joint built-in-self-test), an innovative sensing method for detecting faults in solder-joint networks that belong to the I/O ports of field programmable gate arrays (FPGAs), especially in ball grid array packages. It is well known that fractured solder joints typically maintain sufficient electrical contact to operate correctly for long periods of time. Subsequently, the damaged joint begins to exhibit intermittent failures: the faces of a fracture separate during periods of stress, causing incorrect FPGA signals. SJ BIST detects faults at least as low as 100 Ω with zero false alarms: minimum detectable fault period is one-half the period of the FPGA clock – guaranteed detection is two clock periods. SJ BIST correctly detects and reports instances of high-resistance with no false alarms: test results are shown in this paper. Being able to detect solder-joint faults in FPGAs increases fault coverage and health management capabilities, and provides support for condition-based and reliability-centered maintenance.     

基于二分图模型的通信信息网络故障联合定位

国家电网信息通信网络依靠两套运维系统,分别实现对信息网络与通信网络的故障定位与分析,然而通信网络故障往往会引发信息网络故障,如何高效精确地进行通信信息网络故障联合定位是亟需解决的问题.针对信息通信网络的联合故障定位问题,提出了基于二分图模型的故障联合定位算法.首先依据通信网网络节点的关联性对网络分簇,并将每一簇作为一个子域.其次在每个子域内建立基于二分图的故障关联影响模型,最终利用目标排序法并行地对多个子域内网络故障进行分析,从而实现通信信息网络关联故障高效精确的联合定位.实验结果表明,该联合故障定位分析方法的故障诊断率达85％～95％.     

Cell delay fault testing for iterative logic arrays

C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault occurs if and only if an input transition can not be propagated to the cell's output through a path in the cell in a specified clock period. The set of single-path propagation, hazard-free robust tests that completely check all the paths in a cell is first derived, and then necessary conditions for sending this test set to each cell in the array and simultaneously propagating the fault effects to the primary outputs are given. Test set minimization can be solved in a similar way as for the fault cover problem. We use the pipelined array multiplier as an example, and show that it is C-testable with 214 two-pattern tests. With a small number of additional patterns, all the combinational faults can be detected pseudoexhaustive.     

Energy efficient fault-tolerant multipath routing scheme for wireless sensor networks

In wireless sensor network （MSN）, reliability is the main issue to design any routing technique. To design a comprehensive reliable wireless sensor network, it is essential to consider node failure and energy constrain as inevitable phenomena. In this paper we present energy efficient node fault diagnosis and recovery for wireless sensor networks referred as energy efficient fault tolerant multipath routing scheme for wireless sensor network. The scheme is based on multipath data routing. One shortest path is used for main data routing in our scheme and other two backup paths are used as alternative path for faulty network and to handle the overloaded traffic on main channel. Shortest pat data routing ensures energy efficient data routing. Extensive simulation results have revealed that the performance of the proposed scheme is energy efficient and can tolerates more than 60% of fault.     

Cost Effective Shared Path Protection for WDM Optical Mesh Networks with Partial Wavelength Conversion

In this paper, we study routing and wavelength assignment of connection requests in survivable WDM optical mesh networks employing shared path protection with partial wavelength conversion while 100% restorability is guaranteed against any single failures. We formulate the problem as a linear integer program under a static traffic model. The objective is to minimize the total cost of wavelength-links and wavelength converters used by working paths and protection paths of all connections. A weight factor is used which is defined as the cost ratio of a wavelength converter and a wavelength-link. Depending on the relative cost of bandwidth and wavelength conversion, the optimization objective allows a proper tradeoff between the two. The proposed algorithm, the shortest-widest-path-first (SWPF) algorithm, uses a modified Dijkstra's algorithm to find a working path and a protection path for each connection request in the wavelength graph transformed from the original network topology. When there are multiple candidate paths that have the same minimum total cost, the path along which the maximum number of converters used at each node is minimized is chosen by the SWPF algorithm. We have evaluated the effectiveness of the proposed algorithm via extensive simulation. The results indicate that the performance of the proposed algorithm is very close to that of the optimal solutions obtained by solving the ILP formulation and outperforms existing heuristic algorithms in terms of total number of converters used and the maximum number of converters required at each node in the network. The proposed algorithm also achieves slightly better performance in terms of total cost of wavelength-links and converters used by all connections. We also investigated shared path protection employing converter sharing. The results show that the technique can reduce not only the total number of converters used in the network but also the maximum number of converters required at each node, especially when a large number of converters are needed in the network. In this study, although the ILP formulation is based on static traffic, the proposed algorithm is also applicable to routing dynamic connection requests.     

A fault simulation method: Parallel pattern critical path tracing

We present a fast fault simulation algorithm for combinational circuits which combines parallel pattern evaluation and critical path tracing. When the number of faults is large, our algorithm exploits the full advantages of critical path tracing. As fault dropping progresses, the overhead for critical path tracing surpasses its advantages. On the other hand, the efficiency of Parallel Pattern Single Fault Propagation (PPSFP) increases rapidly since relatively few undetected faults remain, and they tend to be inactive. To avoid the overhead of critical path tracing and achieve the advantages of PPSFP, dynamic update of node classes is used to produce a smooth transition from critical path tracing to PPSFP. By using this approach, we get high performance for both small and large numbers of test patterns. Also, preprocessing related to structure analysis is avoided while achieving almost all of its advantages.This work was supported in part by National Science Foundation grant MIP-9003292.     

Resynthesis of combinational logic circuits for improved path delayfault testability using comparison units

We propose a resynthesis method that modifies a given circuit to reduce the number of paths in the circuit and thus improve its path delay fault testability. The resynthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. A subcircuit can be replaced by a comparison unit if it implements a function belonging to the class of comparison functions defined here. Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates. These properties make them effective building blocks for resynthesis to improve the path delay fault testability of a circuit. Experimental results demonstrate considerable reductions in the number of paths and increased path delay fault testability. These are achieved without increasing the number of gates, or the number of gates along the longest path in the circuit. The random pattern testability for stuck-at faults remains unchanged     

基于神经网络与证据理论的模拟电路故障诊断

论述了利用多类电量测试信息、应用神经网络与D-S证据理论实现模拟电路故障诊断的基本原理,提出了一种基于可测点电压与不同测试频率下的电路增益经决策层信息融合的故障诊断新方法.分别利用此两类测试信息,各用一个独立的改进BP网络对电路进行初步诊断,再运用所提融合诊断算法实现故障定位.模拟实验结果表明:所提方法对硬故障与元件参数偏移较小的软故障均适用,故障定位准确率高.     

Delay Fault Coverage Enhancement Using Variable Observation Times

Detection of system timing failures has become a very importantproblem whenever high speed system operation is required. It has beendemonstrated that delay fault coverage loss could be significant if improperpropagation paths are used. This occurs when the delay test pair of a targetpropagation path cannot be effectively generated by an ATPG tool, or whenstuck-at test patterns are used as transition (or gate) delay test patterns.In this work, an efficient method is proposed to reduce the amount of faultcoverage loss by using variable observation times. The basic idea is tooffset the shorter propagation paths (really used) by tightening theobservation times. Given a probability distribution of defect sizes and aset of slack differences, this method is able to locate several observationtimes that result in small fault coverage loss.     

Procedure for building test sequences for NAND-NOR networks with permanent stuck-at faults

A numerical procedure is proposed for marking the signal paths when building test sequences for the detection of single stuck-at-0 faults in NAND-NOR networks. For this purpose the network is separated into cascade sub-networks. The sensitization of the signal path is first operated in the most extended cascade network, with respect to the transmission conditions related to any type of gate. Inhibition conditions are introduced in order to mark the sensitivity of any input to faults; it is then easily seen to what rank of the test sequence one must refer to detect a given single fault. An example is given of a fan-out network.     

False-Path Removal Using Delay Fault Simulation

Some false paths are caused by redundant stuck-at faults. Removal of those stuck-at faults automatically eliminates such false paths from the circuit. However, there are other false paths that are not associated with any redundant stuck-at fault. All segments of such a false path are shared with other testable paths. We focus on the elimination of this type of false paths. We use a non-enumerative path delay fault simulator based on the path status graph (PSG) data-structure, which duplicates selected gates to separate the detected and undetected path delay faults. The expanded circuit may contain new redundant stuck-at faults, corresponding to those undetected paths that are false. This happens because the expanded circuit has some new interconnects with only false paths passing through them. Such links become the sites for redundant stuck-at faults. Removal of these redundant faults eliminates false paths. The reported results show that the quality of the result may depend on the coverage of testable paths by the vectors that are simulated. When non-enumerative path delay simulation and implication-based redundancy removal techniques are used, the present procedure of false-path elimination can be applied to very large circuits.     

Implicit deductive fault simulation for complex delay fault models

This paper introduces an implicit version of the well-known deductive fault simulation technique suitable to delay fault models with an exponential number of faults. The proposed method calculates the fault coverage by generating lists of entities for each line during a single topological circuit traversal. Each stored entity only contains a number and a subset of the test vectors. No delay faults are stored, and no special data structures are required. There are significant differences between the presented implicit method and fault coverage using deductive fault simulation. The method is shown to be effective for delay the path and segment delay fault models.     

Test‐Generation‐Based Fault Detection in Analog VLSI Circuits Using Neural Networks

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece‐wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.     

Oscillation Ring Delay Test for High Performance Microprocessors

This paper proposes a new test scheme, oscillation ring test, and its associated test circuit organization for delay fault testing for high performance microprocessors. For this test scheme, the outputs of the circuit under test are connected to its inputs to form oscillation rings and test vectors which sensitize circuit paths are sought to make the rings oscillate. High speed transition counters or oscillation detectors can then be used to detect whether the circuit is working normally or not. The sensitizable paths of oscillation rings cover all circuit lines, detecting all gate delay faults, a large part of hazard free robust path delay faults and all the stuck-at faults. It has the advantage of testing the circuit at the working speed of the circuit. Also, with some modification, the scheme can also be used to measure the maximum speed of the circuit. The scheme needs minimal simple added hardware, thus ideal for testing, embedded circuits and microprocessors.     

Improving path delay testability of sequential circuits

We analyze the causes of low path delay fault coverage in synchronous sequential circuits and propose a method to improve testability. The three main reasons for low path delay fault coverage are found to be: (A) combinationally false (nonactivatable) paths; (B) sequentially nonactivatable paths; and (C) unobservable fault effects. Accordingly, we classify undetected faults in Groups A, B, and C. Combinationally false paths ran be made testable by modifying the circuit or resynthesizing the combinational logic as discussed by other researchers. A majority of the untestable faults are, however found in Group B, where a signal transition cannot be functionally propagated through a combinational path. A test requires two successive states necessary to create a signal transition and propagate it through the target path embedded in the sequential circuit. We study a partial scan technique in which flip-flops are scanned to break cycles and shun that a substantial increase in the coverage of path delay faults is possible