A Cost-Shared Quantization Algorithm and Its Implementation for Multi-Standard Video Codecs

Due to the growing demand of digital convergence, there is a need to have a video encoder/decoder (codec) that is capable of supporting multiple video standards on a single platform. High Efficiency Video Coding (HEVC), successor to H.264/MPEG-4 AVC, is a new standard under development that aims to substantially improve coding efficiency compared to AVC High Profile. This paper presents an efficient architecture based on a resource sharing strategy that can perform the quantization operation of the emerging HEVC encoder and six other video encoders: H.264/AVC, AVS, VC-1, MPEG-2, MPEG-4, and Motion JPEG (MJPEG). Since HEVC is still in the drafting stage, the proposed architecture is designed in such a way that any final changes can be accommodated into the design. The proposed quantizer architecture is completely division-free, as the division operation is replaced by shift and addition operations for all the codecs. The design is implemented on an FPGA and later synthesized in CMOS 0.18 μm technology. While working at 190 MHz, the design can decode a 1080p HD video at up to 61 frames per second. The multi-codec architecture is also suitable for low-cost VLSI implementation.     

新一代视频编码标准HEVC变换方法的研究

高性能视频编码( HEVC)将成为国际最新的视频编解码标准.该标准主要针对目前应用日益广泛的高清甚至超高清视频而开发,其编码的性能目标是在保持原来H.264/AVC的视频质量的同时,将比特率再降低一半.与原有标准一样,HEVC对帧内或帧间的残差信号进行正交变换以集中能量至矩阵左上角,然而H.264/AVC标准中的传统DCT方法对于高清视频的处理已不能有较好效果.讨论研究目前针对HEVC正交变换提出的变换方法,包括基于模式的方向变换MDDT、自适应离散余弦/正弦变换(DCT/DST)、旋转变换(ROT)、IDCT修剪和变换跳过模式(TSM)等方法.实验结果显示了上述几种方法在比特率降低、编码时间缩短、软硬件实现复杂度降低和客观视频质量等方面的改进.最后,提出了对HEVC正交变换的进一步研究方向.     

Gravity direction-based ultra-fast intraprediction algorithm for H.264/AVC video coding

The H.264/AVC video coding standard uses in intraprediction, 9 directional modes for 4 × 4 and 8 × 8 luma blocks, and 4 directional modes for 16 × 16 luma macroblocks, and 8 × 8 chroma blocks. The use of the variable block size and multiple modes in intraprediction makes the intracoding of H.264/AVC very efficient compared with other compression standards; however, computational complexity is increased significantly. In this paper, we propose a fast mode selection algorithm for intracoding. This algorithm is based on the vector of the block’s gravity center whose direction is used to select the best candidate prediction mode for intracoding. On this basis, only a small number of intraprediction modes are chosen for rate distortion optimization (RDO) calculation. Different video sequences are used to test the performance of proposed method. The simulation results show that the proposed algorithm increases significantly the speed of intracoding with negligible loss of peak signal-to-noise ratio quality.     

High performance architecture for unified forward and inverse transform of HEVC

High efficiency video coding (HEVC) transform algorithm for residual coding uses 2-dimensional (2D) 4×4 transforms with higher precision than H.264's 4×4 transforms, resulting in increased hardware complexity. In this paper, we present a shared architecture that can compute the 4×4 forward discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) of HEVC using a new mapping scheme in the video processor array structure. The architecture is implemented with only adders and shifts to an area-efficient design. The proposed architecture is synthesized using ISE14.7 and implemented using the BEE4 platform with the Virtex-6 FF1759 LX550T field programmable gate array (FPGA). The result shows that the video processor array structure achieves a maximum operation frequency of 165.2 MHz. The architecture and its implementation are presented in this paper to demonstrate its programmable and high performance.     

Machine learning based fast H.264/AVC to HEVC transcoding exploiting block partition similarity

Video transcoding is to convert one compressed video stream to another. In this paper, a fast H.264/AVC to High Efficiency Video Coding (HEVC) transcoding method based on machine learning is proposed by considering the similarity between compressed streams, especially the block partition correlations, to reduce the computational complexity. This becomes possible by constructing three-level binary classifiers to predict quad-tree Coding Unit (CU) partition in HEVC. Then, we propose a feature selection algorithm to get representative features to improve predication accuracy of the classification. In addition, we propose an adaptive probability threshold determination scheme to achieve a good trade-off between low coding complexity and high compression efficiency during the CU depth prediction in HEVC. Extensive experimental results demonstrate the proposed transcoder achieves complexity reduction of 50.2% and 49.2% on average under lowdelay P main and random access configurations while the rate-distortion degradation is negligible. The proposed scheme is proved more effective as comparing with the state-of-the-art benchmarks.     

An architecture of entropy decoder,inverse quantiser and predictor for multi-standard video decoding

A VLSI architecture for entropy decoder, inverse quantiser and predictor is proposed in this article. This architecture is used for decoding video streams of three standards on a single chip, i.e. H.264/AVC, AVS (China National Audio Video coding Standard) and MPEG2. The proposed scheme is called MPMP (Macro-block-Parallel based Multilevel Pipeline), which is intended to improve the decoding performance to satisfy the real-time requirements while maintaining a reasonable area and power consumption. Several techniques, such as slice level pipeline, MB (Macro-Block) level pipeline, MB level parallel, etc., are adopted. Input and output buffers for the inverse quantiser and predictor are shared by the decoding engines for H.264, AVS and MPEG2, therefore effectively reducing the implementation overhead. Simulation shows that decoding process consumes 512, 435 and 438 clock cycles per MB in H.264, AVS and MPEG2, respectively. Owing to the proposed techniques, the video decoder can support H.264 HP (High Profile) 1920 × 1088@30fps (frame per second) streams, AVS JP (Jizhun Profile) 1920 × 1088@41fps streams and MPEG2 MP (Main Profile) 1920 × 1088@39fps streams when exploiting a 200 MHz working frequency.     

Efficient Inter Prediction Mode Decision Method for Fast Motion Estimation in High Efficiency Video Coding

High Efficiency Video Coding (HEVC) is the most recent video coding standard to achieve a higher coding performance than the previous H.264/AVC. In order to accomplish this improved coding performance, HEVC adopted several advanced coding tools; however, these cause heavy computational complexity. Similar to previous video coding standards, motion estimation (ME) of HEVC requires the most computational complexity; this is because ME is conducted for three inter prediction modes — namely, uniprediction in list 0, uniprediction in list 1, and biprediction. In this paper, we propose an efficient inter prediction mode (EIPM) decision method to reduce the complexity of ME. The proposed EIPM method computes the priority of all inter prediction modes and performs ME only on a selected inter prediction mode. Experimental results show that the proposed method reduces computational complexity arising from ME by up to 51.76% and achieves near similar coding performance compared to HEVC test model version 10.1.     

Low-Complexity Intra-Coding Scheme for HEVC

Compared with H.264/AVC, the latest video standard High Efficiency Video Coding (HEVC) known as H.265 improves the coding efficiency by adopting the quadtree splitting structure which is flexible in representing various textural and structural information in images. However, the computational complexity is dramatically increased, especially in the intra-mode decision process owing to supporting more partitions and modes. In this paper, we propose a low-complexity algorithm for HEVC intra-coding, which consists of a fast coding unit (CU) size decision (FCUSD) method and a fast prediction unit (PU) mode decision (FPUMD) method. In FCUSD, unnecessary CU sizes are skipped early according to the depth level of neighboring CUs and the rate distortion (RD) cost threshold derived from the former coded frame. In FPUMD, the PU mode and RD cost correlations between different depth levels are utilized to terminate unnecessary candidate modes. Experimental results demonstrate that the proposed algorithm can achieve about 50.99 % computational complexity reduction on average with 1.18 % BD-rate increase and 0.08 dB BD-psnr loss.     

HEVC并行解码器设计

新一代视频编码标准HEVC(High Efficiency Video Coding)主要面向高清及超高清视频编码,压缩效率相比之前的编码标准H.264有较大提高.但压缩效率的提高必然会带来计算的复杂化,为提高HEVC的解码效率,降低时延,提出了一种并行解码器架构.该并行解码器的设计是基于HEVC中熵片(Entropy slice)和波前并行处理(Wavefront Parallel Processing, WPP)技术的引入以及滤波器(Deblocking Filter)无相关性的特点.实验结果表明,该并行解码器能够充分利用硬件资源,提高解码效率.     

Low calculation cost of HEVC coding unit size based on spatial homogeneity detection

For the same video quality, HEVC gives 25% to 50% bitrate savings, compared to its predecessor the Advanced Video Coding H.264 and thus supports resolutions up to 8 K UHD. However, the reduction in bitrates provided by the HEVC leads to an increase in the computational cost of the encoding operation. This complexity can become a true handicap especially for real-time video streaming and also for VANET (Vehicular Ad-Hoc Network) applications such as traffic safety and Video surveillance. The improvement in the bitrates and also the increase in the calculation cost are due to the use of large and multi-sized coding, prediction and transform blocks. Indeed, the H264 coder is based on structure macroblocks with sizes 4 × 4, 8 × 8 and 16 × 16, while H.265 depends on Coding Tree Units (CTUs), CTUs select sizes 4 × 4, 8 × 8, 16 × 16, 32 × 32 and 64 × 64 blocks. This paper proposes a fast CU (Coding Unit) size decision method to reduce the HEVC calculation cost based on spatial homogeneity. Compared with the HM16.13 benchmark test model, the average coding time is reduced by around 40% for CIF / QCIF video sequences, 35% to 43% for class A, B and C test sequences. These important reductions in coding time are obtained with negligible loss of quality and an average increase in bitrates which does not exceed 0.89% for the three configuration modes (All intra, Random Access and Low Delay).     

A Very High Throughput Deblocking Filter for H.264/AVC

This paper presents a novel hardware architecture for the real-time high-throughput implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard. A parallel filtering order of six units is proposed according to the H.264/AVC standard. With a parallel filtering order (fully compliant with H.264/AVC) and a dedicated data arrangement in local memory banks, the proposed architecture can process filtering operations for one macroblock with less filtering cycles than previously proposed approaches. Whereas, filtering efficiency is improved due to a novel computation scheduling and a dedicated architecture composed of six filtering cores. It can be used either into the decoder or the encoder as a hardware accelerator for the processor or can be embedded into a full-hardware codec. This developed Intellectual Property block-based on the proposed architecture supports multiple and high definition processing flows in real time. While working at clock frequency of 150 MHz, synthesized under 65 nm low power and low voltage CMOS standard cell technology, it easily meets the throughput requirements for 4 k video at 30 fps of all the levels in H.264/AVC video coding standard and consumes 25.08 Kgates.     

Reducing the Complexity of a Multiview H.264/AVC and HEVC Hybrid Architecture

With the advent of 3D displays, an efficient encoder is required to compress the video information needed by them. Moreover, for gradual market acceptance of this new technology, it is advisable to offer backward compatibility with existing devices. Thus, a multiview H.264/Advance Video Coding (AVC) and High Efficiency Video Coding (HEVC) hybrid architecture was proposed in the standardization process of HEVC. However, it requires long encoding times due to the use of HEVC. With the aim of tackling this problem, this paper presents an algorithm that reduces the complexity of this hybrid architecture by reducing the encoding complexity of the HEVC views. By using Naïve-Bayes classifiers, the proposed technique exploits the information gathered in the encoding of the H.264/AVC view to make decisions on the splitting of coding units in HEVC side views. Given the novelty of the proposal, the only similar work found in the literature is an unoptimized version of the algorithm presented here. Experimental results show that the proposed algorithm can achieve a good tradeoff between coding efficiency and complexity.     

Introduction to the High-Efficiency Video Coding Standard

The high-efficiency video coding(HEVC) standard is the newest video coding standard currently under joint development by ITU-T Video Coding Experts Group(VCEG) and ISO/IEC Moving Picture Experts Group(MPEG).HEVC is the next-generation video coding standard after H.264/AVC.The goals of the HEVC standardization effort are to double the video coding efficiency of existing H.264/AVC while supporting all the recognized potential applications,such as,video telephony,storage,broadcast,streaming,especially for large picture size video(4k × 2k).The HEVC standard will be completed as an ISO/IEC and ITU-T standard in January 2013.In February 2012,the HEVC standardization process reached its committee draft(CD) stage.The ever-improving HEVC standard has demonstrated a significant gain in coding efficiency in rate-distortion efficiency relative to the existing H.264/AVC.This paper provides an overview of the technical features of HEVC close to HEVC CD stage,covering high-level structure,coding units,prediction units,transform units,spatial signal transformation and PCM representation,intra-picture prediction,inter-picture prediction,entropy coding and in-loop filtering.The HEVC coding efficiency performances comparing with H.264/AVC are also provided.     

Intra Prediction for the Hardware H.264/AVC High Profile Encoder

The hardware implementation of the intra prediction described in this paper allows the H.264/AVC encoder to achieve optimal compression efficiency in real-time conditions. The architecture has some features that distinguish it from other solutions described in literature. Firstly, the architecture supports all intra prediction modes defined in High Profile of the H.264/AVC standard for all chroma formats. Secondly, the architecture can generate predictions for several quantization parameters. Thirdly, the hardware cost is reduced as the same resources are used to compute prediction samples for all the modes. Fourthly, the high sample-generation rate enables the encoder to achieve high throughputs. Fifthly, 4?×?4 block reordering and interleaving with other modes minimize the impact of the long-delay reconstruction loop on the encoder throughput. The architecture is verified against the JM.12 reference model and within the real-time FPGA hardware encoder. The synthesis results show that the design can operate at 100 MHz and 200 MHz for FPGA Aria II and 0.13 μm TSMC technology, respectively. These frequencies allow the encoder to support 720p and 1080p video at 30 fps.     

A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications

In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on HD1080 video (1920 times 1088@30 Hz) when operating at 120 MHz with 320 mW power dissipation. Fabricated by using the TSMC one-poly six-metal 0.18 mum CMOS technology, the proposed design occupies 2.9times2.9 mm² silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory     

A real-time inverse quantised transform for multi-standard with dynamic resolution support

In this paper, a real-time configurable intelligent property (IP) core is presented for image/video decoding process in compatibility with the standard MPEG-4 Visual and the standard H.264/AVC. The inverse quantised discrete cosine and integer transform can be used to perform inverse quantised discrete cosine transform and inverse quantised inverse integer transforms which only required shift and add operations. Meanwhile, COordinate Rotation DIgital Computer iterations and compensation steps are adjustable in order to compensate for the video compression quality regarding various data throughput. The implementations are embedded in publicly available software XVID Codes 1.2.2 for the standard MPEG-4 Visual and the H.264/AVC reference software JM 16.1, where the experimental results show that the balance between the computational complexity and video compression quality is retained. At the end, FPGA synthesised results show that the proposed IP core can bring advantages to low hardware costs and also provide real-time performance for Full HD and 4K–2K video decoding.     

Video coding with H.264/AVC: tools, performance, and complexity

H.264/AVC, the result of the collaboration between the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group, is the latest standard for video coding. The goals of this standardization effort were enhanced compression efficiency, network friendly video representation for interactive (video telephony) and non-interactive applications (broadcast, streaming, storage, video on demand). H.264/AVC provides gains in compression efficiency of up to 50% over a wide range of bit rates and video resolutions compared to previous standards. Compared to previous standards, the decoder complexity is about four times that of MPEG-2 and two times that of MPEG-4 Visual Simple Profile. This paper provides an overview of the new tools, features and complexity of H.264/AVC.     

H.264中DCT/IDCT/Hadamard变换多时钟方式的FPGA实现

DCT/IDCT/Hadamard变换被广泛应用于多种视频编码标准中,而H.264/MPEG-4AVC作为新一代的视频压缩标准,它具有在相同图像质量下比其他视频压缩标准拥有更高的压缩率的特性[1],因此对于H.264/MPEG-4AVC中的DCT/IDCT/Hadamard变换的研究就有着十分重要的意义。对于H.264/MPEG-4AVC中变换算法进行分析,并且提出一种可用的高效的硬件实现电路结构,此电路结构能够并行计算4输入像素数据。     

Fast multi-frame motion estimation for H264/AVC system

Advanced video compression standard, H264/AVC, with multi-frame motion estimation, can offer better motion-compensation than the previous coding standards. However, the implementation of real-time multi-frame estimation for an H264/AVC system is difficult due to heavy computations. In this paper, a fast algorithm is proposed in an effort to reduce the searching computation for motion estimation with five reference frames. The fast multi-frame motion estimation consists of the adaptive full-search, three-step search, and diamond search methods using the content adaptive control process. Efficient control flow is proposed to select the searching algorithm dependent on video features. The adaptive algorithm can achieve better rate-distortion and lower computation for H264/AVC coding. The experiments indicate that the speed-up is 6–15 times compared with the full search method, while the image quality slightly degrades.     

基于深层特征学习的高效率视频编码中帧内快速预测算法

高效视频编码(HEVC)标准相对于H.264/AVC标准提升了压缩效率,但由于引入的编码单元四叉树划分结构也使得编码复杂度大幅度提升。对此,该文提出一种针对HEVC帧内编码模式下编码单元(CU)划分表征矢量预测的多层特征传递卷积神经网络(MLFT-CNN),大幅度降低了视频编码复杂度。首先,提出融合CU划分结构信息的降分辨率特征提取模块;其次,改进通道注意力机制以提升特征的纹理表达性能;再次,设计特征传递机制,用高深度编码单元划分特征指导低深度编码单元的划分;最后建立分段特征表示的目标损失函数,训练端到端的CU划分表征矢量预测网络。实验结果表明,在不影响视频编码质量的前提下,该文所提算法有效地降低了HEVC的编码复杂度,与标准方法相比,编码复杂度平均下降了70.96%。