Dual-time resolution time-based transceiver for low-power serial interfaces

This paper presents the design and analysis of a CMOS power amplifier (PA) with active 2nd harmonic injection at the input. In this circuit, the main amplifier operates in class-A to provide a high linearity performance, and the auxiliary one is a class-C high efficiency amplifier, which injects the 2nd harmonic into the main amplifier. Theoretical analysis and simulations show that the proposed technique improves the PA linearity, power added efficiency (PAE), and the output power. The auxiliary amplifier, also referred as injection amplifier, injects the 2nd harmonic to the main (core) amplifier in order to compensate the gain compression phenomena at the main amplifier output node. Moreover, waveform shaping is employed to decrease the overlap of voltage and current waveforms, resulting in PAE improvement. The fully integrated PA with 2nd harmonic injection was designed and simulated in 0.18 µm CMOS technology, with a center frequency of 2.6 GHz. Post-layout simulation of PA exhibits 31.25% PAE in maximum linearity point (1 dBC point), illustrating 12.3% improvement at this power level. The 1 dBC point of PA is improved by 3.2 dB, and the PA output power is 20.2 dBm using 3.3 V supply voltage.     

Power-Combining Transformer Techniques for Fully-Integrated CMOS Power Amplifiers

Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented. For the high power CMOS PA design, two types of transformers, series-combining and parallel-combining, are fully analyzed and compared in detail to show the parasitic resistance and the turn ratio as the limiting factor of power combining. Based on the analysis, two kinds of parallel-combining transformers, a two-primary with a 1:2 turn ratio and a three-primary with a 1:2 turn ratio, are incorporated into the design of fully-integrated CMOS PAs in a standard 0.18-mum CMOS process. The PA with a two-primary transformer delivers 31.2 dBm of output power with 41% of power-added efficiency (PAE), and the PA with a three-primary transformer achieves 32 dBm of output power with 30% of PAE at 1.8 GHz with a 3.3-V power supply.     

S波段高效F类/逆F类GaN HEMT功率放大器设计

为了解决F类和逆F类（F-1类）功率放大器设计过程中受晶体管寄生参数影响,导致功放效率低以及输出匹配电路结构复杂的问题,提出了一种新型的输出匹配电路结构.首先,在直流偏置线中加入谐波调谐功能,避免单独设计谐波控制电路;其次,为满足F类和F-1类功放在器件本征漏极端所需的阻抗状态,匹配寄生参数呈现的封装端谐波阻抗,采用一段L型传输线结构代替传统的L-C集总元件寄生补偿方法;最后,由两段串联的传输线实现最优基波阻抗与50 Ω负载间的匹配.为验证方法的有效性,采用CGH40010氮化镓高电子迁移率晶体管（Gallium nitride high electron mobility transistor,GaN HEMT）器件,设计并加工了两款工作在2.4 GHz的F类和F-1类功放.测试结果显示:F类功放的峰值功率附加效率（power added efficiency,PAE）为75.5%,饱和输出功率为40.8 dBm;F-1类功放的峰值PAE为77.6%,饱和输出功率为40.3 dBm.该方法降低了电路复杂度和设计难度,可以较容易地补偿晶体管寄生参数,功放在高频工作时的效率得到提升,为利用GaN HEMT器件设计高效功放提供了一种可行的方案.     

A novel full-wave rectifier/sinusoidal frequency doubler topology based on CFOAs

In this paper, a high-efficiency class-F power amplifier (PA) is designed using integration between a low voltage p-HEMT transistor and a miniaturized microstrip suppressing cell. It results in nth harmonic suppression and high power added efficiency (PAE) under low radio frequency (RF) input powers. The simulation is performed based on harmonic balance analysis. The proposed power amplifier is fabricated, and measurements results validated the simulations. The proposed power amplifier operates at 1.8 GHz with 100 MHz bandwidth and an average PAE of 71.1%, with very low drain voltage of 2 V. At fundamental frequency of 1.8 GHz, the maximum measured PAE is 73.5% at about 12 dBm RF input power. The maximum output power and gain are 23.4 and 17.5 dBm in RF input power ranges of 0–12 dBm, respectively. The fabricated class-F PA with such characteristics can be used for power amplifications in wireless transmitters such as 4G (4th generation)-LTE (long term evolution) communication systems.     

Design of InP DHBT power amplifiers at millimeter-wave frequencies using interstage matched cascode technique

In this paper, the design of InP DHBT based millimeter-wave(mm-wave) power amplifiers(PAs) using an interstage matched cascode technique is presented. The output power of a traditional cascode is limited by the early saturation of the common-base(CB) device. The interstage matched cascode can be employed to improve the power handling ability through optimizing the input impedance of the CB device. The minimized power mismatch between the CB and the common-emitter(CE) devices results in an improved saturated output power. To demonstrate the technique for power amplifier designs at mm-wave frequencies, a single-branch cascode based PA using single-finger devices and a two-way combined based PA using three-finger devices are fabricated. The single-branch design shows a measured power gain of 9.2 dB and a saturated output power of 12.3 dBm at 67.2 GHz and the two-way combined design shows a power gain of 9.5 dB with a saturated output power of 18.6 dBm at 72.6 GHz.     

基于GaN器件的连续型高效宽带功率放大器设计*

提出一种高效宽带功率放大器的设计方法,并基于GaN HEMT 器件CGH40010F 设计了验证电路。利用功放管输出寄生参数的等效网络,将基于连续型功放理论得到的负载阻抗转换到封装参考面上,并利用多谐波双向牵引技术对转换后的负载阻抗进行适当调整,使二次谐波负载阻抗位于高效率区以及基频负载阻抗能够获得高功率附加效率和高输出功率。谐波阻抗位于高效率区使得匹配网络的设计简化为基频匹配网络的设计,降低了对谐波阻抗匹配的难度和宽带匹配网络设计的复杂度。实验结果表明:在1GHz -3GHz 工作频带(相对带宽100%)内,功率附加效率在53%-64.6%之间,输出功率为39.5±2dBm,增益为11.5±2dB,二次谐波小于-15dBc,三次谐波小于-25dBc。     

Design of efficient power amplifier for low power transmitters

This paper presents a fully integrated, low transmit-power and high-efficiency 2.4 GHz class-E power amplifier (PA) in TSMC 0.18 μm CMOS process for low-power transmitters such as wireless sensor networks (WSN). In this paper, a new output load has been proposed. Also, analytical design equations have been included to design an efficient low power circuit. This PA, employs the pad capacitance and bond-wire inductance of the output node, for satisfying class-E zero-voltage switching (ZVS) condition and matching the antenna’s 50 Ω resistance. By using bond-wire inductance instead of inductor in the output filter, smaller chip size and higher efficiency has been achieved compared to other works for low transmit-power applications. Also, the effectiveness of bulk-drive technique on faster switching and increasing efficiency have been evaluated. It has been proved that this technique leads to increase the efficiency of switching PAs. This PA delivers a range of output power from 2.7 to 7.2 dBm with a supply voltage range from 500 to 850 mV while achieving overall power efficiency range of 57.3–60.7%.     

Switchless compact dual-band matching networks for class-E power amplifiers

Two compact switchless dual-band load networks for class-E power amplifier (PA) operating at 800 and 1900 MHz are proposed, featuring small area and low loss which will be suitable for non-concurrent dual-band PA module in handset. Theoretical analysis and design equations are provided along with a loss model, including loss in the transistor and in the load network. Loss model is extracted for each structure to find the design parameters for optimized and balanced efficiency in both bands. Both designs are fabricated on Rogers RO4003 substrate with lumped components. Full PA simulations of both bands are carried out with co-simulation using a Triquint TGF2023-2-10 GaN transistor model, lumped components and EM models of load network layouts for both structures. The PA with transformer-based load network achieves a power added efficiency of 68.6 % at low band and 62.6 % at high band at an output power of 37.8 and 36.7 dBm respectively. The overall area consumed by the load network is 13.5 × 9.6 mm². The LC-based PA has a similar PAE of 68.3 and 60 % at low band and high band, respectively. The output power is 38.1 dBm in the low band and 37 dBm in the high-band. The overall area consumed by the load network is 9 × 10 mm²     

A 1 V power amplifier for 81–86 GHz E-band

The design and layout of a two stage SiGe E-band power amplifier using a stacked transformer for output power combination is presented. In EM-simulations with ADS Momentum, at E-band frequencies, the power combiner consisting of two individual single turn transformers performs significantly better than a single 2:1 transformer with two turns on the secondary side. Imbalances in the stacked transformer structure are reduced with tuning capacitors for maximum gain and output power. At 84 GHz the simulated loss of the stacked transformer is as low as 1.35 dB, superseding the performance of an also presented alternative power combiner. The power combination allows for a low supply voltage of 1 V, which is beneficial since the supply can then be shared between the power amplifier and the transceiver, thereby eliminating the need of a separate voltage regulator. To improve the gain of the two-stage amplifier it employs a capacitive cross-coupling technique not yet seen in mm-wave SiGe PAs. Capacitive cross-coupling is an effective technique for gain enhancement but is also sensitive to process variations as shown by Monte Carlo simulations. To mitigate this two alternative designs are presented with the cross coupling capacitors implemented either with diode coupled transistors or with varactors. The PA is designed in a SiGe process with f _T  = 200 GHz and achieves a power gain of 12 dB, a saturated output power of 16 dBm and a 14 % peak PAE. Excluding decoupling capacitors it occupies a die area of 0.034 mm².     

A 50 to 70 GHz Power Amplifier Using 90 nm CMOS Technology

A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured P_sat of 13.8 dBm, P_{1 dB} of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under V_DD biased at 1.8 V. When V_DD is biased at 3 V, it exhibits P_sat of 18 dBm, P_{1 dB} of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 times 0.5 mm². To the author's knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band.     

Linearity optimizing on HBT power amplifier design

Highly linearized of HBT power amplifier (PA) was achieved for wireless digital mobile communication systems. This study investigates in detail the improvement of the linearity of HBT power amplifiers. The dependence of collector–base capacitance (C_bc) on bias is regarded initially as a trade-off between linearity and breakdown voltage. A simulation of device performed using SILVACO software reveals that at a capacitance ratio; C_bc (0/6 V) is 1.25 at a BV_ceo of 22 V. The device-level DC characteristic, load-pull power performance and power cell PAs are evaluated. A reasonably high PAE ~55% is attainable at 2.0 GHz and an adjacent channel leakage power ratio (ACPR) of over −48 dBc is achieved. The maximum achievable PAE is 54% with a maximum power density of 0.75 W/mm at 5.8 GHz. The novel HBT epitaxial structure, the layout of power cell design and the thick metal shunt process used to ensure the high linearity of the power cell are demonstrated.     

Design Optimization and DPD Linearization of GaN-Based Unsymmetrical Doherty Power Amplifiers for 3G Multicarrier Applications

In this paper, a design optimization approach for gallium-nitride (GaN)-based Doherty power amplifiers (PAs) is proposed to enhance linearizability and maximize the power-added efficiency (PAE) for multicarrier wideband code division multiple access (WCDMA) applications. This is based on the use of an input offset line at the peaking amplifier path to compensate, at a given backoff level, for the bias and power-dependant phase variation through the carrier and peaking paths. At a 6-dB output power backoff (OPBO), measurement results of the unsymmetrical unlinearized Doherty amplifier using a four-carrier WCDMA signal achieved results of close to 50% for the PAE and about -30 dBc for the adjacent channel leakage ratio. Linearization of the designed Doherty PA using a baseband digital predistortion technique led to quasi-perfect cancellation of spectrum regrowth. At an OPBO equal to the input signal's peak-to-average power ratio, -63- and -53-dBc adjacent channel power ratios were obtained when the Doherty amplifier was driven by single- and four-carrier WCDMA signals, respectively. To the best of the authors' knowledge, this represents the best reported results for PAE and linearity for GaN-based Doherty PAs linearized over 20 MHz of instantaneous bandwidth.     

A Highly Efficient and Linear Class-AB/F Power Amplifier for Multimode Operation

The class-AB/F power amplifier (PA), a multimode PA, which can operate at both class-AB and class-F modes, is analyzed and compared with the conventional class-F and class-AB PAs. The open-circuited third harmonic control circuit enhances the efficiency of the PA without deteriorating the linearity of class-AB mode of the PA. The voltage and current waveforms are simulated to evaluate the appropriate operation for the modes. To demonstrate the multimode PA, the PA is implemented using an InGaP/GaAs HBT process and it is tested with reverse-link IS-95A code division multiple access (CDMA) and PCS1900 global system for mobile communications signals in the personal communications service band. The class-AB operation for a CDMA signal delivers a power-added efficiency (PAE) of 38.9% and an adjacent channel power ratio of 49.5 and 56.5 dBc at the offset of 1.25 and 2.25 MHz, respectively, at the output power of 28 dBm. The maximum PAE of 64.7% under the class-F operation is measured at 32.5-dBm output power for a GSM signal. The class-AB/F PA is a good candidate for the multimode PA of next-generation wireless communication systems.     

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-$mu$ m 2.5-V standard I/O FETs in a 0.13- $mu$m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.      

An improved 860–960 MHz fully integrated CMOS power amplifier designation for UHF RFID transmitter

An improved design of 860–960 MHz fully integrated CMOS power amplifier (PA) for UHF RFID transmitter is presented in this paper. It utilizes three stage differential structure, including common-source structure applying RC feedback circuit to improve linearity, cascade structure adopting self-biased cascode technique and self-forward-body-bias (SFBB) technique to overcome shortcomings of low breakdown voltage and to reduce supply voltage respectively in order to obtain high output power, high efficiency and low supply voltage. By integrating these techniques organically, simulation results demonstrate that the circuit provides 21 dBm output power and 35% power-added efficiency (PAE) with 3 V supply. A comparison with other PAs operating in similar frequencies shows the proposed LNA has advantages of higher output power, higher PAE, higher linearity and lower supply voltage.     

基于嵌套负载牵引技术的超宽带高效功放设计

提出了一种基于嵌套负载牵引技术的多倍频程功率放大器的设计方法。与传统的负载牵引技术不同,该方法考虑了基波阻抗与二次谐波阻抗之间的相关性,能够提供更精确的设计区域。它不仅可以研究带内谐波对功放多倍频性能的影响,而且可以改善设计空间,使宽带匹配网络设计更加方便。为验证该方法的可行性,设计并实现了一款超宽带功率放大器。实验结果表明,在0.3~3.2 GHz(相对带宽165.7%)频段内,漏极效率为61.8%~73.6%,输出功率为40.2~42.6 dBm,实现的功放面积为7.4 cm×3.0 cm,与其它性能相近功放相比,面积明显减小。     

Highly linear 0.18-/spl mu/m CMOS power amplifier with deep n-Well structure

The linearity of a 0.18-/spl mu/m CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parameters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is revealed that the DNW of the nMOS lowers the harmonic distortion generated from the intrinsic gate-source capacitance (C/sub gs/), which is the dominant nonlinear source, and partially from drain junction capacitance (C/sub jd/). Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18-/spl mu/m standard CMOS process. The single-ended PA with the DNW improves IMD3 and IMD5 about 5 dB with identical power performances, i.e., 20 dBm of P/sub out/, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at P/sub 1dB/. The IMD3 and IMD5 are below -40 dBc and -47dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of P/sub out/, 18.9 dB of power gain and 35% of PAE at P/sub 1dB/. The IMD3 and IMD5 are below -45 dB and -57 dBc, respectively. These performances of the linear PAs are state-of-the-art results.     

Ultra‐small Form‐Factor Helix on Pad‐Type Stage‐Bypass WCDMA Tx Power Amplifier Using a Chip‐Stacking Technique and a Multilayer Substrate

A fully integrated small form‐factor HBT power amplifier (PA) was developed for UMTS Tx applications. For practical use, the PA was implemented with a well configured bottom dimension, and a CMOS control IC was added to enable/disable the HBT PA. By using helix‐on‐pad integrated passive device output matching, a chip‐stacking technique in the assembly of the CMOS IC, and embedding of the bulky inductive lines in a multilayer substrate, the module size was greatly reduced to 2 mm × 2.2 mm. A stage‐bypass technique was used to enhance the efficiency of the PA. The PA showed a low idle current of about 20 mA and a PAE of about15% at an output power of 16 dBm, while showing good linearity over the entire operating power range.     

Device and Design Optimization for AlGaN/GaN X-Band-Power-Amplifiers with High Efficiency

The design, realization and characterization of dual-stage X-band high-power and highly-efficient monolithic microwave integrated circuit (MMIC) power amplifiers (PAs) with AlGaN/GaN high electronic mobility transistors (HEMTs) is presented. These high power amplifiers (HPAs) are based on a precise investigation of circuit-relevant HEMT behavior using two different field-plate variants and its effects on PA performance as well as optimization of HPA driver stage size which also has a deep impact on the entire HPA. Two broadband (3 GHz) MMICs with different field-plate variants and two narrowband (1 GHz) PAs with different driver- to final-stage gate-width ratio are realized with a maximum output power of 19-23 W, a maximum power-added efficiency (PAE) of ≥40%, and an associated power gain of 17 dB at X-band. Furthermore, two 1 mm test transistors of the same technology with the mentioned field-plate variants and a 1 mm test MMIC support VSWR-ratio tests of 6:1 and 4:1, respectively.