Time domain modelled ADC BIST with ramp noise projection

This paper proposes a time domain modelled built-in self-test (BIST) with ramp noise projection and their effects on analogue to digital converter (ADC) in testing. A self-biased linear ramp generator has been proposed for high precision testing. Threshold inversion quantization (TIQ) comparator based fast switching flash ADC has considered under test. A time domain model of output response analysis technique has been proposed to calibrate the linearity errors of the converter. An ADC has been validated with different input frequencies to characterize the harmonic distortion and average delay of the system. The proposed testing technique requires less time to measures the uncertainties of the ADC since the full computation is performed within one ramp cycle. The testing results of the proposed BIST technique are aimed to characterize, validate and compare to the best results of the existing ADC BIST techniques for test accuracy.     

New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters

Two alternative BIST schemes are proposed for structural testing of pipelined Analog-to-Digital Converters (ADC). They are oriented to fault detection in the converter stages rather than to measure the whole ADC electrical performance parameters. The operational principle of both strategies relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a simple DC stimuli set which is easily obtained, without strong precision requirements, by a resistive network. The main differences between both strategies relate to the way the output response is evaluated. In the BIST#1 scheme, analog and digital outputs are compared with reference levels generated with a reference D/A converter and a counter. In the BIST#2 strategy, only digital outputs are available and they are compared with fault-free values previously stored in an on-chip register. The new techniques are intended to be used in pipelined converters of an arbitrary number of conversion stages and with a digital self-correction mechanism.     

红外焦平面列级ADC数字读出电路测试技术研究

数字化红外焦平面器件是焦平面发展的重要方向,其核心是读出电路集成高性能模数转换器(ADC)。分析了读出电路数字化输出后焦平面性能参数的评价方法,阐述了红外焦平面列级ADC的静态测试和动态测试方法,提出了基于斜坡电压输入的过采样原理测试ADC静态性能,提升无误码分辨率测试正确性。针对ADC静态测试和动态测试要求,结合Labview软件和数字采集卡搭建了软硬件测试平台,并通过一款数字焦平面芯片的测试,验证了测试方法和平台适用于行列级ADC数字化读出电路的测试评价。     

Simultaneous Static Testing of A/D and D/A Converters Using a Built‐in Structure

Static testing of analog‐to‐digital (A/D) and digital‐to‐analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built‐in self‐test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations.     

Code-width testing-based compact ADC BIST circuit

This paper proposes a new analog-to-digital converter (ADC) built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal. The proposed BIST scheme can be implemented by a simple digital circuit whose gate count is only approximately 550. The proposed BIST scheme is verified by simulation with 138 test circuits of 6-b pipeline ADC with arbitrary faults. Simulation results show that it effectively detects not only the catastrophic faults but also some parametric faults. The simulated fault coverage is approximately 99%.     

An ADC BIST with on-chip ramp generator

This work presents built-in self-test (BIST) techniques for the production testing of mixed signal circuits. The special test strategy for the typical mixed-signal component analog-to-digital converter (ADC) is discussed. The traditional test for such mixed-signal components can be completed through a DSP-based mixed-signal tester with an arbitrary waveform generator and a signal digitizer, but such a test is very costly and time consuming. Hence, a BIST strategy based on an on chip ramp generator (OCRG) is proposed in this work for testing ADC. This BIST method has an advantage testing ADC without DAC to overcome area overhead. This BIST method realizes the test controller, test pattern generation and output response analyser at the aspect of the on-chip circuitry. The demonstration of the proposed BIST is given through various simulation results in the last parts of this work.     

A Built-in-Self-Test Σ-Δ ADC Prototype

This paper presents a built-in-self-test (BIST) Σ-Δ ADC prototype. The BIST circuity uses the proposed modified controlled sine wave fitting (CSWF) procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. Compared with conventional Fast Fourier Transform (FFT) analysis, neither complex CPU/DSP nor bulky memory is required. The added BIST circuitry is purely digital and the hardware overhead is as low as 11.9 K gates. A prototype comprising the second-order design-for-digital-testability Σ-Δ modulator chip and an FPGA board which implements the digital functions is used to demonstrate the effectiveness of the BIST design. Measurement results show that the SNDR difference between conventional FFT analysis and the proposed BIST design of the standard ??6 dBFS, 1 KHz tone test is only 0.3 dB. Furthermore, the tested dynamic range values by both methods are the same. The proposed BIST implementation achieves the advantages of compact hardware, high test accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.     

一种混合信号SoC中模数转换器的内建自测试方案

提出了一种针对混合信号SoC中ADC的动态参数与静态参数测试的内建自测试方案.由于动态参数和静态参数在同一个测试电路中都能够得到测试,因此能够更加全面准确地反映待测器件的性能.通过对存储器和计算资源的合理配置和复用,将两种测试的激励产生和响应分析集成在一起,最大程度地减少了对电路面积的影响.整个设计在FPGA上实现,实验结果证明了其可行性.     

Leakage-Aware Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators

Transient performance is one of the most crucial design properties in digital low-dropout regulator (DLDO) design. In this paper, an improved droop measurement built-in self-test (BIST) circuit for DLDOs is presented, expanding on the previous work (Dirican et al. 2018) by the same authors. The proposed BIST system can detect and store the transient droop information using droop detector and generates a digital output with a reuse based 10-bit successive-approximation (SAR) analog-to-digital converter (ADC) with better accuracy. The improvements are achieved by employing a multi-step ramp circuit and a leakage cancellation circuit. The system is made more suitable for process scaling by replacing the analog buffer with a multi-step ramp circuit. Employing a leakage cancellation circuit solves potential leakage problems during ADC operation due to the reused decoupling capacitor of the DLDO and nearly 75% reduction in maximum measurement error is observed using this feature. Additionally, the droop detector is capable of storing transient droop information with less than 0.6% error for droop voltages ranging from 45 mV to 406 mV for a nominal DLDO output voltage of 1.6 V where the supply voltage is 1.8 V. The proposed BIST circuit is designed using a 0.18 μm CMOS process in Cadence Virtuoso and verified with corner simulations.     

Experimental Results of Testing a BIST Σ–Δ ADC on the HOY Wireless Test Platform

High pin count packaging and 3D IC technology make testing such advanced ICs more and more difficult and expensive. The HOY wireless test platform provides an alternative and cost-effective test solution to address the poor accessibility and high test cost issues. The key idea is implementing a low-cost and short-distance wireless transceiver on chip so that all test instructions and data can be transmitted without physical access. Due to the limited wireless bandwidth, all modules in the device under test (DUT) are preferred to have some built-in self-test (BIST) features. Prior works successfully demonstrated that DUTs with memory and digital circuits can be tested on the low-cost wireless test platform. However, there is no example to show if it is also possible to test the DUT embedded with analog circuits on the HOY test platform. This paper demonstrates the first system-level integration including hardware and software for testing a fully-integrated BIST ADC on the HOY wireless test platform. The DUT chip fabricated in 0.18-μm CMOS consists of a second-order Σ–Δ ADC under test (AUT) and the BIST circuitry. The AUT design employs the decorrelating design-for-digital-testability (D³T) scheme to make itself digitally testable. The BIST design is based on the modified controlled sine wave fitting (CSWF) method. The required BIST circuits are purely digital and as small as 9.9k gates. The gate count of the HOY test wrapper is less than 1k. Experimental results obtained by the HOY wireless test platform show that the AUT achieves a dynamic range of 85.1 dB and a peak SNDR of 78.6 dB. The wireless test results show good agreement with those acquired by conventional analog tests.     

An Accumulator-Based Compaction Scheme For Online BIST of RAMs

Transparent built-in self test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional transparent BIST schemes, achieving considerable reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compaction is performed using either single-input or multiple-input shift registers whose characteristic polynomials are modified during testing. In this paper the utilization of accumulator modules for output data compaction in symmetric transparent BIST for RAMs is proposed. It is shown that in this way the hardware overhead, the complexity of the controller, and the aliasing probability are considerably reduced.      

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity characterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the LSB of the target ADC. The proposed ramp generator is employed in a servo-loop configuration to implement a BIST version of the reduced-code linearity test technique for pipeline ADCs, which drastically reduces the volume of test data and, thereby, the test time, as compared to the standard test based on a histogram. The demonstration of the pipeline ADC BIST is carried out based on a mixture of transistor-level and behavioral-level simulations that employ actual production test data.     

An Output Response Analyzer Circuit for ADC Built-in Self-Test

In this paper, a structure of the output response analyzer (ORA) circuit for analog-to-digital converters (ADCs) built-in self-test (BIST) is presented. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to estimate the degradation of signal-to-noise ratio (SNR) value. The appropriate approximations of the testing parameters reduce difficulties in designing the complete ORA circuit. In addition, the feature of reusable hardware in the calculation of sine-wave reference histograms and the computing capability of ADCs’ parameters further improves the ORA design. This design is compact and easily to be adjusted by different setting. The developed ORA circuits are synthesized in a 0.18-μm technology to analyze the outputs of an 8-bit ADC to verify the designs.     

A new on-chip digital BIST for analog-to-digital converters

A fully digital built-in self-test (BIST) for analog-to-digital converters is presented in this paper. This test circuit is capable of measuring the DNL, INL, offset error and gain error, and mainly consists of several registers and some digital subtracters. The main advantage of this BIST is the ability to test DNL and INL for all codes in the digital domain, which in turn eliminates the necessity of calibration. On the other hand, some parts of the analog-to-digital converter with minor modifications are used in the BIST simultaneously. This also reduces the area overhead and the cost of the test. The proposed BIST structure presents a compromise between test accuracy, area overhead and test cost. The BIST circuitry has been designed using Mitel CMOS 1.5 μm technology. The simulation results of the test show that it can be applied to medium resolution analog-to-digital converters or high resolution pipelined analog-to-digital converters. The presented BIST shows satisfactory results for a nine-bit pipe-lined analog-to-digital converter.     

Deterministic Built-in Pattern Generation for Sequential Circuits

We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits. Our approach is based on precomputed test sequences, and is especially suited to sequential circuits that contain a large number of flip-flops but relatively few controllable primary inputs. Such circuits, often encountered as embedded cores and as filters for digital signal processing, are difficult to test and require long test sequences. We show that statistical encoding of precomputed test sequences can be combined with low-cost pattern decoding to provide deterministic BIST with practical levels of overhead. Optimal Huffman codes and near-optimal Comma codes are especially useful for test set encoding. This approach exploits recent advances in automatic test pattern generation for sequential circuits and, unlike other BIST schemes, does not require access to a gate-level model of the circuit under test. It can be easily automated and integrated with design automation tools. Experimental results for the ISCAS 89 benchmark circuits show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time and low to moderate hardware overhead.     

A digital pixel sensor array with programmable dynamic range

This paper presents a digital pixel sensor (DPS) array employing a time domain analogue-to-digital conversion (ADC) technique featuring adaptive dynamic range and programmable pixel response. The digital pixel comprises a photodiode, a voltage comparator, and an 8-bit static memory. The conversion characteristics of the ADC are determined by an array-based digital control circuit, which linearizes the pixel response, and sets the conversion range. The ADC response is adapted to different lighting conditions by setting a single clock frequency. Dynamic range compression was also experimentally demonstrated. This clearly shows the potential of the proposed technique in overcoming the limited dynamic range typically imposed by the number of bits in a DPS. A 64 /spl times/ 64 pixel array prototype was manufactured in a 0.35-/spl mu/m, five-metal, single poly, CMOS process. Measurement results indicate a 100 dB dynamic range, a 41-s mean dark time and an average current of 1.6 /spl mu/A per DPS.     

An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR

Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes.     

一种有效的ADC内建自测试方案

内建自测试是降低ADC电路测试成本的有效方法。通过最小二乘法和斜坡柱状图。我们得出了测试ADC电路的增益误差、失调误差、微分非线性和积分非线性的算法。根据这些测试算法。介绍了一种易于片上集成的内建自测试结构。实验结果表明，该内建自测试方案具有较高的测试精度。     

On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits

High-speed digital design is becoming increasingly analog. In particular, interconnect response at high frequencies can be nonmonotonic with "porch steps" and ringing. Crosstalk (both capacitive and inductive) can result in glitches on wires that can produce functional failures in receiving circuits. Most of these important effects are not addressed with traditional automatic test pattern generation (ATPG) and built-in self-test (BIST) techniques, which are limited to the binary abstraction. In this work, we explore the feasibility of integrating primitive sampling oscilloscopes on-chip to provide waveforms on selective critical nets for test and diagnosis. The oscilloscopes rely on subsampling techniques to achieve 10-ps timing accuracy. High-speed samplers are combined with delay-locked loops (DLLs) and a simple 8-bit analog-to-digital converter (ADC) to convert the waveforms into digital data that can be incorporated as part of the chip scan chain. We will describe the design and measurement of a chip we have fabricated to incorporate these oscilloscopes with a high-frequency interconnect structure in a TSMC 0.25-/spl mu/m process. The layout was extracted using Cadence's Assura RCX-PL extraction engine, enabling a comparison between simulated and measured results.     

红外焦平面读出电路集成数字输出

为了实现红外焦平面数字化输出,设计了一种集成片上模数转换的焦平面读出电路,包括一个512512的读出电路单元阵列和列共享的逐次逼近寄存器型模数转换器(SAR ADC)。单元读出电路采用了直接注入(DI)结构作为输入级,输出的信号通过多路传输送到模数转换器。设计的逐次逼近型的模数转换器中的比较器采用的是由前置放大器、锁存器、自偏置差分放大器和输出驱动器组成的高速比较器,数模转换器(DAC)采用的是三段式的电荷按比例缩放和电压按比例缩放相结合的结构。在Cadence和Synopsys设计平台下对模拟和数字部分电路分别进行设计、仿真与版图设计。电路工艺采用GLOBALFOUNDRIES公司0.35 m CMOS 3.3 V工艺加工流片。测试结果显示SAR ADC有效位数为8.2位,转换频率超过150 k Samples/s,功耗低于300 W,满足焦平面100帧频以及低功耗的需求。