The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed. Then two new circuits, i.e., CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced. In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun. The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed. Both the forward scaling of the active devices and the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples.     

A low-power highly linear cascoded multiple-gated transistor CMOS RF amplifier with 10 dB IP3 improvement (Revised)

A low-power highly linear CMOS RF amplifier circuit composed of a Multiple-Gated common-source FET TRansistor (MGTR) in cascode configuration is reported. In an MGTR amplifier, linearity is improved by using transconductance linearization which can be achieved by canceling the negative peak value of g/sub m/" of the main transistor with the positive one in the auxiliary transistor having a different size and gate drive combined in parallel. This enhancement, however, is limited by the distortion originated from the combined influence of g/sub m/' and harmonic feedback, which can greatly be reduced by the cascoding MGTR output. IP3 improvement as large as 10 dB has been obtained from an experimental RF amplifier designed at 900 MHz and fabricated using 0.35 /spl mu/m BiCMOS technology using only CMOS at a similar power consumption and gain as those obtainable from conventional cascode single gate transistor amplifiers.     

A low-power highly linear cascoded multiple-gated transistor CMOS RF amplifier with 10 dB IP3 improvement

A low-power highly linear CMOS RF amplifier circuit composed of a Multiple-Gated common-source FET TRansistor (MGTR) in cascode configuration is reported. In a MGTR amplifier, linearity is improved by using transconductance linearization which can be achieved by canceling the negative peak value of g/sub m/" of the main transistor with the positive one in the auxiliary transistor having a different size and gate drive combined in parallel. This enhancement, however, is limited by the distortion originated from the combined influence of g/sub m/' and harmonic feedback, which can greatly be reduced by the cascoding MGTR output. IP3 improvement as large as 10 dB has been obtained from an experimental RF amplifier designed at 900 MHz and fabricated using 0.35 /spl mu/m BiCMOS technology using only CMOS at a similar power consumption and gain as those obtainable from conventional cascode single gate transistor amplifiers.     

Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors

It has been known that using selective epitaxial growth (SEG) of silicon, to elevate source/drain regions, is beneficial to digital CMOS by reducing the junction leakage. In addition, this architecture also reduces the gate resistance by enabling a T-shape gate and allowing thicker silicides, which is beneficial for RF-CMOS regarding increased maximum oscillation frequency (f/sub max/) and lowering of the noise figure (NF). In this paper, we report the impact of the SEG-deep source/drain implant (DSDI) process sequence and Co silicide thickness on DC and RF performance of NMOS transistors. Up to a 28%-45% improvement in f/sub max/ is achievable due to a T-shaped gate and thicker Co, made possible by an elevated source/drain (/sup E/S/D) architecture. The maximum transconductance (g/sub m/) of the /sup E/S/D device reaches a value of 1100 mS/mm, which in turn gives a very high f/sub T/ of 150 GHz. The low gate sheet resistance obtained with this architecture is also very beneficial for suppressing noise figure in the low-noise amplifier (LNA) circuit demonstrated in this paper. Furthermore, it is shown by simulation that the noise performance of an RF LNA improves due to the SEG and the Co thickness in the T-shaped gate of the NMOS transistor.     

Simultaneous all-optical frequency downconversion technique utilizing an SOA-MZI for WDM radio over fiber (RoF) applications

Simultaneous all-optical frequency-downconversion technique utilizing a semiconductor optical amplifier Mach-Zehnder interferometer (SOA-MZI) is experimentally demonstrated, and its application to a wavelength-division-multiplexing (WDM) radio over fiber (RoF) uplink is proposed. The conversion efficiencies from 22.5 (f/sub RF/) to 2.5 GHz (f/sub IF/=f/sub RF/-2f/sub LO/) are in the range from 1.5 to 3 dB for the optical RF wavelength between 1548 and 1558 nm. Error-free simultaneous all-optical frequency downconversion of the two WDM RoF upstream channels that carry 155-Mb/s differential phase-shift keying data at 22.5 GHz to an optical intermediate frequency signal having the frequency of 2.5 GHz with the power penalty less than 0.1 dB at the bit error rate of 10/sup -8/ is achieved.     

A 40 GHz single-ended down-conversion mixer in 0.13 /spl mu/m SiGeC BiCMOS HBT

This work presents a single-ended active mixer realized with a 0.13 /spl mu/m BiCMOS SiGeC heterojunction bipolar transistor (HBT) technology. This mixer is designed to be integrated in a superheterodyne receiver for 40 GHz wireless communication systems. Local oscillator (LO) and RF signals are directly applied to the base of the HBT through two coupled lines. The mixer provides a down-conversion from 42 GHz to 2 GHz. The mixer exhibits a power conversion gain better than 2.4 dB and a measured double-sideband noise figure less than 8.3 dB for P/sub LO/=3 dBm (power of the local oscillator) under a global power consumption lower than 9.5 mW. This architecture exhibits good linearity performance with a measured IP/sub 1dB/ of about -7 dBm and an IIP3 of +4 dBm. The linear dynamic range for a 2 GHz system bandwidth is approximately 65 dB for P/sub LO/=+2 dBm and T/sub 0/=290 K. The third order spurious free dynamic range is calculated to be better than 52 dB.     

A 0.13 μm CMOS UWB RF Transmitter with an On‐Chip T/R Switch

This paper presents a fully integrated 0.13 μm CMOS MB‐OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low‐pass filter, a variable gain amplifier, a voltage‐to‐current converter, an I/Q up‐mixer, a differential‐to‐single‐ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 μm CMOS technology. The fabricated transmitter shows a ?3 dB bandwidth of 550 MHz at each sub‐band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.     

Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMs

A sensing scheme in which the bit line is precharged to half V/SUB DD/ is introduced for CMOS DRAMs. The proposed circuitry uses a PMOS memory array and incorporates the following features: (1) a complementary sense amplifier consisting of NMOS and PMOS cross-coupled pairs; (2) clocked pulldown of the latching node; (3) complementary clocking of the PMOS pullup; (4) full-sized dummy cell generation of reference potential for sensing; (5) shorting transistor to equalize precharge potential of bit lines; and (6) depletion NMOS decoupling transistors for multiplexing bit lines. The study shows that the half-V/SUB DD/ bit-line sensing scheme has several unique advantages, especially for high-performance high-density CMOS DRAMs, which compared to the full-V/SUB DD/ bit-line sensing scheme used for NMOS memory arrays or the grounded bit-line sensing scheme for PMOS arrays in CMOS DRAMs.     

Load modulation power amplifier with lumped-element combiner for IEEE 802.11b/g WLAN applications

A new monolithic microwave integrated circuit power amplifier for 802.11b/g wireless local area network (WLAN) has been implemented using the load modulation concept of a Doherty amplifier. The /spl lambda//4 transmission line for the load modulation circuit of the carrier amplifier is replaced by a lumped element based /spl pi/-network, which dual functions as an output matching network, simultaneously. This amplifier shows that error vector magnitude is about 4.6% and power added efficiency (PAE) about 31.8% at P/sub out/ of 19 dBm for a 802.11g 64QAM signal. PAE of the power amplifier is about 49.6%, and adjacent channel leakage ratio below 37.2dBc at 11 MHz offset at P/sub out/ of 23 dBm for the 802.11b complementary code keying signal     

6-k/spl Omega/ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range

A high-gain, 43-Gb/s InP HBT transimpedance-limiting amplifier (TIALA) with 100-/spl mu/A/sub pp/ sensitivity and 6 mA/sub pp/ input overload current is presented. The circuit also operates as a limiting amplifier with 40-dB differential gain, better than 15-dB input return loss, and a record-breaking sensitivity of 8 mV/sub pp/ at 43 Gb/s. It features a differential TIA stage with inductive noise suppression in the feedback network and consumes less than 450mW from a single 3.3-V supply. The TIALA has 6-k/spl Omega/ (76dB/spl Omega/) differential transimpedance gain and 35-GHz bandwidth and comprises the transimpedance and limiting gain functions, an auto-zero dc feedback circuit, signal level monitor, and slicing level adjust functions. Other important features include 45-dB isolation and 800-mV/sub pp/ differential output.     

Design of a CMOS opamp input stage immune to EMI

In this paper the behaviour of a complementary nMOS–pMOS differential pair in the presence of RF interference superimposed on the input terminals is analysed. An intrinsic nonlinearity cancellation mechanism in this structure is demonstrated, and proper design criteria are presented to exploit this mechanism in order to achieve a very high immunity to RF interference. A high-immunity complementary differential pair has been employed as an input stage of a folded cascode operational amplifier and its improved behaviour in the presence of RF interference has been verified by computer simulations.     

A 86 to 108 GHz Amplifier in 90 nm CMOS

This letter presents a CMOS amplifier with 22 GHz 3-dB bandwidth ranging from 86 to 108 GHz. The amplifier is implemented in 90 nm mixed signal/radio frequency (RF) CMOS process using three-stage cascode RF NMOS configuration. It achieves a peak gain of 17.4 dB at 91 GHz from the measured results. To our knowledge, this is the highest frequency CMOS amplifier reported to date.     

A 44-GHz-high IP3 InP HBT MMIC amplifier for low DC powermillimeter-wave receiver applications

This paper reports on what is believed to be the highest IP3/P_dc power linearity figure of merit achieved from a monolithic microwave integrated circuit (MMIC) amplifier at millimeter-wave frequencies. The 44 GHz amplifier is based on an InP heterojunction bipolar transistor (HBT) technology with f_T's and f_max's of 70 and 200 GHz, respectively. The 44-GHz amplifier design consists of four prematched 1×l0μm² four-finger (40-μm²) heterojunction bipolar transistor (HBT) cells combined in parallel using a compact λ/8 four-way microstrip combiner. Over a 44-50-GHz frequency band, the amplifier obtains a gain of 5.5-6 dB and a peak gain of 6.8-7.6 dB under optimum gain bias. At a low bias current of 48 mA and a total dc power of 120 mW, the amplifier obtains a peak IP3 of 34 dBm, which corresponds to an IP3/P_dc power ratio of 21:1, a factor of two better than previous state-of-the-art MMIC's reported in this frequency range. By employing a thin, lightly doped HBT collector epitaxy design tailored for lower voltage and higher IP3, a record IP3/P_dc, power ratio of 42.4:1 was also obtained and is believed to be the highest reported for an MMIC amplifier of any technology. The new high-linearity HBT's have strong implications for millimeter-wave receiver as well as low-voltage wireless applications     

A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner

A wideband CMOS low noise amplifier (LNA) with single-ended input and output employing noise and IM2 distortion cancellation for a digital terrestrial and cable TV tuner is presented. By adopting a noise canceling structure combining a common source amplifier and a common gate amplifier by current amplification, the LNA obtains a low noise figure and high IIP3. IIP2 as well as IIP3 of the LNA is important in broadband systems, especially digital terrestrial and cable TV applications. Accordingly, in order to overcome the poor IIP2 performance of conventional LNAs with single-ended input and output and avoid the use of external and bulky passive transformers along with high sensitivity, an IM2 distortion cancellation technique exploiting the complementary RF performance of NMOS and PMOS while retaining thermal noise canceling is adopted in the LNA. The proposed LNA is implemented in a 0.18 $muhbox{m}$ CMOS process and achieves a power gain of 14 dB, an average noise figure of 3 dB, an IIP3 of 3 dBm, an IIP2 of 44 dBm at maximum gain, and S11 of under ${- 9}~{rm dB}$ in a frequency range from 50 MHz to 880 MHz. The power consumption is 34.8 mW at 2.2 V and the chip area is 0.16 ${rm mm}^{2}$.      

A low cost and low power silicon npn bipolar process with NMOS transistors (ADRF) for RF and microwave applications

A silicon bipolar process for RF and microwave applications, which features 25-GHz double-polysilicon self-aligned npn bipolar transistors with 5.5-V BV/sub CEO/, optional 0.7-/spl mu/m (L/sub eff/) NMOS transistors with p/sup +/ polysilicon gates for switch applications, lateral pnp transistors, high and low valued resistors, p/sup +/ polysilicon-to-n/sup +/ plug capacitors, and inductors is described. The npn transistors utilize nitride-oxide composite spacers formed using sacrificial TEOS spacers, a process which is simpler than the previously reported composite spacer processes. Use of the composite spacer structure virtually eliminates problems relating to the extrinsic-intrinsic base link-up and reduces plasma induced damage associated with the conventional spacer process. Microwave and RF capabilities of the process up to several GHz are demonstrated by fabricating and characterizing RF amplifiers, low noise amplifiers, and RF switches.<>     

A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers

A wide-band radio-frequency (RF) front-end is designed with a balanced combined low-noise amplifier and a switching mixer (a low-noise converter) in an RF Si-bipolar process with an f/sub T/ of 25 GHz. The circuit achieves 20-dB conversion gain, higher than -4.5-dBm RF-to-IF IIP/sub 3/ (+15.5-dBm OIP/sub 3/) and less than 3.8-dB double-side-band noise figure in 900-MHz (e.g., GSM) and 1.9-GHz (e.g., WCDMA) frequency bands. The -1-dB compression point is -20 dBm at 13-mA DC current consumption from a single 5-V supply. The local-oscillator leakage to the input is less than -56 dBm in the 900-MHz band and less than -63 dBm in the 1.9-GHz band. The -3-dB bandwidth of the amplifier is larger than 3 GHz and a wide-band matching at the input with -10 to -41-dB S/sub 11/ is achieved in the frequency bands of interest by applying a dual-loop wide-band active feedback. The die area is 0.69 /spl times/ 0.9 mm/sup 2/. The circuit is suitable for area-efficient multiband multistandard low-IF receivers.     

Exact analysis of maximum available gain and unilateral gain including phase angle of S21

Exact formulae are presented for both maximum available gain (G/sub ma/) and unilateral gain (U), which include both the magnitude and phase angle of the S/sub 21/ parameter. The result for G/sub ma/ is not unique since there are many possible solutions to simultaneously match S/sub 11/ and S/sub 22/ when k>1. For the phase angle of U, the result tends to become 180/spl deg/ when using the topology of a variable coupler, a line stretcher, and a feedback amplifier. From the verifications, an amplifier using the unilateralizing technique will achieve 4-6 dB higher gain than that of the G/sub ma/ amplifier.     

A 20-GHz low-noise amplifier with active balun in a 0.25-/spl mu/m SiGe BICMOS technology

A 20-GHz low-noise amplifier (LNA) with an active balun fabricated in a 0.25-/spl mu/m SiGe BICMOS (f/sub t/=47 GHz) technology was presented by the authors in 2004. The LNA achieves close to 7 dB of gain and a noise figure of 4.9 dB with all ports simultaneously matched to 50 /spl Omega/ with better than -16 dB of return loss. The amplifier is highly linear with an IP/sub 1dB/ of 0 dBm and IIP/sub 3/ of 9 dBm, while consuming 14 mA of quiescent current from a 3.3-V rail, with temperature-compensated biasing. To the authors' knowledge, the LNA delivers the lowest reported noise figure and highest linearity for a silicon implementation of a combined active balun and LNA at 20 GHz, and is the first implementation of an active balun with an LC degenerated emitter-coupled pair. Here we expand on that work, with an analysis of the balun operation and noise optimization of the design.     

Bias-temperature instabilities of polysilicon gate HfO/sub 2/ MOSFETs

Bias-temperature instabilities (BTI) of HfO/sub 2/ metal oxide semiconductor field effect transistors (MOSFETs) have been systematically studied for the first time. NMOS positive BTI (PBTI) exhibited a more significant V/sub t/ instability than that of PMOS negative BTI (NBTI), and limited the lifetime of HfO/sub 2/ MOSFETs. Although high-temperature forming gas annealing (HT-FGA) improved the interface quality by passivating the interfacial states with hydrogen, BTI behaviors were not strongly affected by the technique. Charge pumping measurements were extensively used to investigate the nature of the BTI degradation, and it was found that V/sub t/ degradation of NMOS PBTI was primarily caused by charge trapping in bulk HfO/sub 2/ rather than interfacial degradation. Deuterium (D/sub 2/) annealing was found to be an excellent technique to improve BTI immunity as well as to enhance the mobility of HfO/sub 2/ MOSFETs.     

A CMOS 140-mW fourth-order continuous-time low-pass filter stabilized with a class AB common-mode feedback operating at 550 MHz

A 550-MHz linear-phase low-pass continuous-time filter is described. The operational transconductance amplifier (OTA) is based on complementary differential pairs in order to achieve high-frequency operation. A common-mode feedback (CMFB) based on a Class AB amplifier with improved stability at high frequencies is introduced. Results for the stand alone OTA show a unity gain frequency of 1 GHz while the excess phase is less than 5/spl deg/. The filter is based on G/sub m/-C biquads and achieves IM3 <-40 dB for a two-tone input signal of -10 dBm each. The power consumption of the fourth-order filter is 140 mW from supply voltages of /spl plusmn/1.65 V. The chip was fabricated in a standard 0.35-/spl mu/m CMOS technology.