Thin-film transistors in polycrystalline silicon by blanket andlocal source/drain hydrogen plasma-seeded crystallization

Thin film n-channel transistors have been fabricated in polycrystalline silicon films crystallized using hydrogen plasma seeding, by using several processing techniques with 600 to 625°C or 1000°C as the maximum process temperature. The TFTs from hydrogen plasma-treated films with a maximum process temperature of 600°C, have a linear field-effect mobility of ~35 cm²/Vs and an ON/OFF current ratio of ~10⁶, and TFTs with a maximum process temperature of 1000°C, have a linear field-effect mobility of ~100 cm²/Vs and an ON/OFF current ratio of ~10⁷. A hydrogen plasma has also then been applied selectively a in the source and drain regions to seed large crystal grains in the channel. Transistors made with this method with maximum temperature of 600°C showed a nearly twofold improvement in mobility (72 versus 37 cm² /Vs) over the unseeded devices at short channel lengths. The dominant factor in determining the field-effect mobility in all cases was the grain size of the polycrystalline silicon, and not the gate oxide growth/deposition conditions. Significant increases in mobility are observed when the grain size is in order of the channel length. However the gate oxide plays an important role in determining the subthreshold slope and the leakage current     

Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates     

Effects of trap-state density reduction by plasma hydrogenation inlow-temperature polysilicon TFT

The reduction of trap-state densities by plasma hydrogenation in n-channel polysilicon thin-film transistors (poly-TFTs) fabricated using a maximum temperature of 600°C has been studied. Hydrogenated devices have a mobility of ~40 cm²/V×5, a threshold voltage of ~2 V, an inverse subthreshold of ~ 0.55 V/decade, and a maximum on/off current ratio of 5×10⁸. The effective channel length decreases by ~0.85 μm after a short hydrogenation which may be attributed to the activation of donors at trap states near the source/drain junctions. Trap-state densities decrease from 1.6×10¹² to 3.5×10¹¹ cm^-2 after hydrogenation, concomitant with the reduction of threshold voltage. Using the gate lengths at which the trap-state densities deviate from the long-channel values as markets for the leading edge of passivation, the apparent hydrogen diffusivity is found to be 1.2×10^-11 cm²/s at 350°C in the TFT structure     

Characterization of highly doped n- and p-type 6H-SiCpiezoresistors

Highly doped (~2×10¹⁹ cm^-3) n- and p-type 6H-SiC strain sensing mesa resistors configured in Wheatstone bridge integrated beam transducers were investigated to characterize the piezoresistive and electrical properties. Longitudinal and transverse gauge factors, temperature dependence of resistance, gauge factor (GF), and bridge output voltage were evaluated. For the n-type net doping level of 2×10¹⁹ cm^-3 the bridge gauge factor was found to be 15 at room temperature and 8 at 250°C. For this doping level, a TCR of -0.24%/°C and -0.74%/°C at 100°C was obtained for the n- and p-type, respectively. At 250°C, the TCR was -0.14%/°C and -0.34%/°C, respectively. In both types, for the given doping level, impurity scattering is implied to be the dominant scattering mechanism. The results from this investigation further strengthen the viability of 6H-SiC as a piezoresistive pressure sensor for high-temperature applications     

Effect of ion energy on hydrogen diffusion in n- and p-GaAs

The ion energy during electron cyclotron resonance (ECR) plasma hydrogenation is found to have a strong effect on both the effective diffusivity and solubility of hydrogen in n⁺ and p⁺ GaAs. For fixed plasma exposure conditions (30 min, 250°C) the diffusion depths for -150 V acceleration voltage are ~50 and ~100% larger, respectively, in p⁺- and n⁺-GaAs compared to 0 V acceleration voltage. The smaller incorporation depths at lower ion energy coincide with much larger peak hydrogen concentrations and higher apparent thermal stability of passivated dopants     

Amorphous silicon buried-channel thin-film transistors

We demonstrate a buried-channel thin-film field effect transistor (TFT) based on deposited silicon nitride and hydrogenated amorphous silicon with the conducting channel recessed approximately 50 Å from the interface. We fabricate transistors and capacitors by DC reactive magnetron sputtering of a silicon target in a plasma of (Ar+H ₂+N₂) or (Ar+H₂) for the nitride and silicon layers, respectively. To create a step in the conduction band, and thus a buried-channel, we vary the hydrogen partial pressure which varies the hydrogen content and the bandgap of amorphous silicon. Capacitance-voltage and current-voltage measurements on these devices present strong evidence for the existence of the buried-channel. We achieve a record field effect mobility in saturation of 1.68 cm² /V-s with amorphous silicon deposited at 230°C, and an acceptable mobility of 0.44 cm²/V-s with amorphous silicon deposited at 125°C     

Characterization of n-type β-SiC as a piezoresistor

SiC is currently being investigated for device applications involving high temperatures. The properties of n-type β-SiC relevant to piezoresistive devices, namely the gauge factor (GF) and temperature coefficient of resistivity (TCR), are characterized for several doping levels. The maximum gauge factor observed was -31.8 for unintentionally doped (10¹⁶-10¹⁷/cm³) material. This gauge factor decreases with temperature to approximately half its room-temperature value at 450°C. Unintentionally doped SiC has a roughly constant TCR of 0.72%/°C over the range 25-800°C and exhibits full impurity ionization at room temperature. Degenerately doped gauges (N_d=10²⁰/cm³) exhibited a lower gauge factor (-12.7), with a more constant temperature behavior and a lower TCR (0.04%/°C). The mechanisms of the piezoresistive effect and TCR in n-SiC are discussed, as well as their application towards sensors     

Study on hydrogenation of polysilicon thin film transistors by ionimplantation

Hydrogenation of polysilicon (poly-Si) thin film transistors (TFT's) by ion implantation has been systematically studied. Poly-Si TFT performance was dramatically improved by hydrogen ion implantation followed by a forming gas anneal (FGA). The threshold voltage, channel mobility, subthreshold swing, leakage current, and ON/OFF current ratio have been studied as functions of ion implantation dose and FGA temperature. Under the optimized conditions (H⁺ dose of 5×10¹⁵ cm^-2 and FGA temperature at 375°C), NMOS poly-Si TFT's fabricated by a low temperature 600°C process have a mobility of ~27 cm ²/V·s, a threshold voltage of ~2 V, a subthreshold swing of ~0.9 V/decade, and an OFF-state leakage current of ~7 pA/μm at V_DS=10 V. The avalanche induced kink effect was found to be reduced after hydrogenation     

Deep-level dominated current-voltage characteristics of buriedimplanted oxide silicon-on-insulator

Current-voltage characteristics of Au contacts formed on buried implanted oxide silicon-on-insulator (SOI) structures are discussed, which indicate that the dominant transport mechanism is space-charge-limited current (SCLC) conduction in the presence of deep-level states. The deep-level parameters, determined using a simple analysis, appear to be sensitive to anneal conditions used and subsequent processing. Silicon implanted with 1.7×10¹⁸ cm^-2 oxygen ions at 150 keV following a 1200°C anneal for 3 h shows deep level 0.37 eV below the conduction band edge with a concentration of unoccupied traps of ~ 2×10¹⁵ cm^-3 . In contrast, arsenic ion implantation, in the 1200°C annealed material with a dose of 1.5×10¹² cm^-2 at 60 keV and activated by rapid thermal annealing (RTA), introduces a deep level 0.25 eV below the conduction band edge with an unoccupied trap concentration of ~6×10¹⁷ cm^-2     

High current p/p+-diamond Schottky diode

Epitaxial p-type Schottky diodes have been fabricated on p⁺ -substrate. While the activation energy of the epitaxial layer conductivity is 390 meV, that of the substrate is only 50 meV. At forward bias the substrate conductivity dominates above 150°C, leading for a 5×10^-5 cm² area contact to a series resistance of 14 Ω at 150°C reducing to 8 Ω at 500°C. To our knowledge, this is the lowest series resistance reported so far for a diamond Schottky diode enabling extremely high current densities of 10³ A/cm and a current rectification ratio at ±2 V of 10⁵ making these diodes already attractive as high temperature rectifiers     

Rapid isothermal annealing of high- and low-energy ion-implantedInP and In0.53Ga0.47As

Rapid isothermal annealing (RIA) was performed on 0.5-16-MeV Si ⁺, 1-MeV Be⁺, and 150-keV Ge⁺ implanted InP:Fe and 380-keV Fe⁺ implanted InGaAs. Annealings were performed in the temperature range 800-925°C using an InP proximity wafer in addition to the Si₃N₄ dielectric cap. Dopant activations close to 100% were obtained for 3×10¹⁴ cm^-2 Si⁺ and 2×10¹⁴ cm^-2 Be⁺ implants in InP:Fe. For the elevated temperature (200°C) 1×10¹⁴ cm^-2 Ge⁺ implant, a maximum of 50% activation was obtained. No redistribution of dopant was observed for Si and Ge implants due to annealing. However, redistribution of dopant was seen for Be and Fe implants due to annealing. Phosphorous coimplantation has helped to eliminate the Be in-diffusion problem in InP, but did not help to reduce Fe in-diffusion and redistribution in InGaAs. Using an RIA cycle with low temperature and short duration is the only solution to minimize Fe redistribution in InGaAs     

Nitrogen-implanted SiC diodes using high-temperature implantation

6H-SiC diodes fabricated using high-temperature nitrogen implantation up to 1000°C are reported. Diodes were formed by RIE etching a 0.8-μm-deep mesa across the N⁺/P junction using NF₃/O₂ with an aluminum transfer mask. The junction was passivated with a deposited SiO₂ layer 0.6 μm thick. Contacts were made to N⁺ and P regions with thin nickel and aluminum layers, respectively, followed by a short anneal between 900 and 1000°C. These diodes have reverse-bias leakage at 25°C as low as 5×10^-11 A/cm² at 10 V     

Polycrystalline silicon thin film transistors fabricated at reducedthermal budgets by utilizing fluorinated gate oxidation

Polycrystalline silicon thin film transistors have been fabricated at reduced gate oxidation thermal budgets by utilizing NF₃-enhanced dry oxidation. Good performance TFTs with effective electron mobility values as high as 38 cm²/V.sec, threshold voltage values near zero, ON/OFF current ratios of up to 5×10⁷ and subthreshold slopes of 0.3 V/dec have been fabricated at an oxidation temperature of 800°C. Stable devices at an electrical stressing field of 3 MV/cm were demonstrated. Thermal gate oxide TFTs have also been fabricated at a maximum temperature of 650°C. The effect of hydrogen plasma passivation was found to depend on process conditions and was correlated with the amount of fluorine in the area near the Si-SiO₂ interface. Passivation at low power was always beneficial. Passivation at high power was highly beneficial for a limited amount of interfacial fluorine, but less beneficial or even detrimental when a large fluorine amount in the near interface area was present     

Photoluminescence from Er-implanted polycrystalline 3C SiC

Erbium (Er) ions were implanted into polycrystalline 3C silicon carbide (SiC), and were characterized by photoluminescence (PL) measurements and Rutherford backscattering spectrometry (RBS) channeling analysis. The optimum annealing temperature and Er dose for SiC:Er were 1600°C and 3×10¹³ cm^-2, respectively. PL intensity decreased at 1700°C, and the bandedge luminescence changed in relation to the luminescence of Er³⁺. The decrease in the PL intensity of Er³⁺ may be due to the sublimation of Si atoms and the decrease in excitation volume of PL. The PL intensity of SiC:Er,O (SiC:Er coimplanted with oxygen) was twice as strong as that of SiC:Er, whereas no other PL peaks were observed. Thermal quenching of the luminescence of Er³⁺ was suppressed by using SiC with a wide band gap as a host material and the Er³⁺-PL was observed at room temperature (RT). Our present results suggest that the transfer of the recombination energy of electron-hole pairs generated in SiC to the Er-4f-shell via the Auger effect causes the luminescence of Er³⁺ in SiC:Er     

Effect of p-doping on the temperature dependence of differentialgain in FP and DFB 1.3-μm InGaAsP-InP multiple-quantum-well lasers

The temperature dependence of differential gain dG/dn for 1.3-μm InGaAsP-InP FP and DFB lasers with two profiles of p-doping was obtained from RIN measurements within the temperature range of 25°C-65°C. Experiments showed that the change of the active region doping level from 3·10¹⁷ cm^-3 to 3·10¹⁸ cm^-3 leads to a 50% increase of the differential gain for FP lasers at 25°C. Heavily doped devices also exhibit more rapid reduction of the differential gain with increasing temperature. The effect of active region doping on the energy separation between the electron Fermi level and electronic states coupled into the laser mode explains the observations. The temperature dependence of differential gain for DFB devices strongly depends on the detuning of the lasing wavelength from the gain peak     

Temperature-humidity-bias-behavior and acceleration model for InPplanar PIN photodiodes

The reliability of InP planar PIN photodiodes in humid ambients has been studied. The dependence of the degradation rate in temperature, humidity and bias was determined by aging devices at temperatures between 50 and 150°C, humidities between 50 and 85% RH, and biases between 2 and 25 V. Failure occurred as a result of a sudden increased dark current. This increase in dark current had little affect on the device responsivity. At all aging conditions the failure distributions were well represented by a lognormal distribution in time with a dispersion of less than 0.3. From these data, an acceleration factor (AF) was developed and is given by AF=exp(E/kT)exp[A(RH)²]exp[B(V)] where E=-0.42 eV, A=-4.6×10^-4, and B=-6.7×10^-2/V. Extensive failure mode analysis was done on more then 500 failed devices. Based on this, a failure mechanism was proposed. The model requires ingress of moisture to the InP surface. The moisture is reduced at the p-contact region of the device region, giving off hydrogen. Under negative bias In and P react with the hydrogen to form gaseous IH and PH ₃. This lead to the semiconductor erosion. The erosion continues until device failure occurs. The worst case concentrate of PH ₃ which if created would produce less than 0.1 ppb PH₃ per cm³ of air. Thus it is not a fire or health hazard. Finally, we present reliability prediction for nonhermetic PIN's encapsulated in an optically clear silicone based polymer. We estimate a 20 year hazard rate of less than 100 FIT's for devices operating at an ambient of 45°C/50% RH. For comparison, the hermetic counterparts of similar design have a 20 year hazard rate of less than 10 FIT's     

High field effect mobility deuterated amorphous silicon thin-filmtransistors based on the substitution of hydrogen with deuterium

The characteristics of amorphous silicon hydrogen and deuterium thin-film transistors (a-Si:H/a-Si:D TFT) were studied. The deuterated and hydrogenated amorphous silicon channels were prepared by first annealing the as-deposited a-Si:H layer at 550°C in N₂ environment to expel all the hydrogen atoms out of the films, then the D ₂ or H₂ plasma were applied to treat the amorphous silicon layers. The field effect mobility of the conventional hydrogen TFT is usually smaller than 1 cm²/V-s. It was found that substitution of hydrogen with deuterium improved the field effect mobility of the TFT. The maximum field effect mobility of a-Si:D TFT obtained from the saturation region was 1.77 cm²/V-s     

High frequency performance of SiC heterojunction bipolartransistors

A compact heterojunction bipolar transistor (HBT) model was employed to simulate the high frequency and high power performances of SiC-based bipolar transistors. Potential 6H-SiC/3C-SiC heterojunction bipolar transistors (6H/3C-HBT's) at case temperatures of 27°C (300 K) through 600°C (873 K) were investigated. The high frequency and high power performance was compared to AlGaAs/GaAs HBT's. As expected, the ohmic contact resistance limits the high frequency performance of the SiC HBT. At the present time, it is only possible to reliably produce 1×10^-4 Ω-cm² contact resistances on SiC, so an f_T of 4.4 GHz and an f_max of 3.2 GHz are the highest realistic values. However, assuming an incredibly low 1×10^-6 Ω-cm² contact resistance for the emitter, base, and collector terminals, an f_T of 31.1 GHz and an f_max of 12.7 GHz can be obtained for a 6H/3C-SiC HBT     

Rapid thermal annealing effects on Si p+-n junctionsfabricated by low-energy FIB Ga+ implantation

Effects of rapid thermal annealing (RTA) on sub-100 nm p⁺ -n Si junctions fabricated using 10 kV FIB Ga⁺ implantation at doses ranging from 10¹³ to 10¹⁵ cm ^-2 are reported. Annealing temperature and time were varied from 550 to 700°C and 30 to 120 s. It was observed that a maximum in the active carrier concentration is achieved at the critical annealing temperature of 600°C. Temperatures above and below the critical temperature were followed by a decrease in the active concentration, leading to a `reverse' annealing effect     

Electrical characterization of annealed Ti/TiN/Pt contacts onN-type 6H-SiC epilayer

We report results of the electrical characteristics of in vacuo deposited Ti/TiN/Pt contact metallization on n-type 6H-SiC epilayer as function of impurity concentration in the range of 3.3×10¹⁷ cm^-3 to 1.9×10¹⁹ cm^-3. The as-deposited contacts are rectifying, except for the highly doped sample. Only the lesser doped remains rectifying after samples are annealed at 1000°C between 0.5 and 1 min in argon. Bulk contact resistance ranging from factors of 10^-5 to 10^-4 Ω-cm² and Schottky barrier height in the range of 0.54-0.84 eV are obtained. Adhesion problems associated with metal deposition on pre-processed titanium is not observed, leading to excellent mechanical stability. Auger electron spectroscopy (AES) reveals the out diffusion of Ti-Si and agglomeration of Ti-C species at the epilayer surface. The contact resistance remains appreciably stable after treatment in air at 650°C for 65 h. The drop in SBH and the resulting stable contact resistance is proposed to be associated with the thermal activation of TiC diffusion barrier layer on the 6H-SiC epilayer during annealing