Measurement of ultralow gate tunneling currents using floating-gate integrator technique

We report for the first time that a gate tunneling current measurement sensitivity better than 3/spl times/10/sup -22/ A has been achieved by using a floating-gate integrator technique. The technique involves monitoring the charge change in the floating-gate integrated with an on-chip op-amp and an on-chip feedback capacitor. We used this technique to study the stress-induced leakage current (SILC) and its cycling dependence of 70 /spl Aring/ oxides in the direct tunneling region at oxide voltage as low as 1.9 V. The technique has been validated through correlation to direct measurement on MOSFET arrays and theoretical calculations. The measured SILC current is modeled with an Inelastic trap-assisted tunneling model.     

Polarity-dependent tunneling current and oxide breakdown indual-gate CMOSFETs

The gate tunneling leakage current in dual-gate CMOSFETs exhibits strong polarity dependence when measured in inversion, although it exhibits practically no polarity dependence when measured in accumulation. Specifically, p⁺-gate pMOSFET shows substantially lower tunneling current than n⁺-gate nMOSFET when measured in inversion. This polarity dependence arises from the difference in the supply of tunneling electrons. The polarity dependent tunneling current has a significant impact on oxide reliability measurements. For example, it gives rise to a higher T_bd value for p⁺/pMOSFET as compared to that for n⁺/nMOSFET when both are biased to inversion. Rationaless are given as to why T_bd is a better gauge than Q_bd for reliability assessment, and why nMOSFET is more prone to oxide breakdown than pMOSFET under normal operating conditions     

Modeling CMOS tunneling currents through ultrathin gate oxide dueto conduction- and valence-band electron and hole tunneling

A semi-empirical model is proposed to quantify the tunneling currents through ultrathin gate oxides (1-3.6 nm). As a multiplier to a simple analytical model, a correction function is introduced to achieve universal applicability to all different combinations of bias polarities (inversion and accumulation), gate materials (N⁺, P⁺ , Si, SiGe) and tunneling processes. Each coefficient of the correction function is given a physical meaning and determined by empirical fitting. This new model can accurately predict all the current components that can be observed: electron tunneling from the conduction band (ECB), electron tunneling from the valence band (EVB), and hole tunneling from the valence hand (HVB) in dual-gate poly-Si_1-xGe_x-gated (x=0 or 0.25) CMOS devices for various gate oxide thicknesses. In addition, this model ran also be employed to determine the physical oxide thickness from I-V data with high sensitivity. It is particularly sensitive in the very-thin-oxide regime, where C-V extraction happens to be difficult or impossible (because of the presence of the large tunneling current)     

Modelling of dual-gate MESFETs with second gate forward biased

Drain characteristics of dual-gate MESFETs with the second gate positively biased have been analysed on the basis of Pucel.s model. A diode in series with a resistor was proposed to model the positively biased gate. The simulated characteristics agree well with the experimental curves.     

10 Gbit/s AND gate using dual-gate GaAs MESFET

Using a commercial dual-gate GaAs MESFET transistor mounted in a microstrip circuit, an AND gate has been built. With the 100 ps (FWHM) wide test pulses available, a speed of 10 Gbit/s NRZ and a pulse suppression of at least 14 dB was obtained.     

High-performance dual-gate carbon nanotube FETs with 40-nm gate length

We report on a high-performance back-gated carbon nanotube field-effect transistor (CNFET) with a peak transconductance of 12.5 /spl mu/S and a delay time per unit length of /spl tau//L=19 ps//spl mu/m. In order to minimize the parasitic capacitances and optimize the performance of scaled CNFETs, we have utilized a dual-gate design and have fabricated a 40-nm-gate CNFET possessing excellent subthreshold and output characteristics without exhibiting short-channel effects.     

On the calculation of gate tunneling currents in ultra-thin metal–insulator–semiconductor capacitors

The calculation of gate tunneling currents in metal–insulator–semiconductor structures with ultra-thin gate stacks directly relies on quantum mechanical principles. In this paper, it is illustrated that well-known techniques based on elementary quantum physics and statistical mechanics can successfully be applied to solve some conceptual problems encountered on calculating the gate current and the charge distribution.     

Influence of gate intervals on the behaviour of submicron dual-gate FETs

A simple, self-consistent model, taking into account the non-stationary electron dynamic effects, is used to study the behaviour of submicron dual-gate FETs. It shows that the conventional model, based on the connection of two field-effect transistors in cascade, is no longer valid when the intergate distances become smaller than 0.6 ?m.     

Fully depleted 20-nm SOI CMOSFETs with W-clad gate/source/drainlayers

Fully-depleted 20-nm SOI complementary metal-oxide-semiconductor field effect transistors (CMOSFETs) were successfully fabricated without a raised source/drain (S/D) structure, instead using low-temperature selective tungsten CVD (SWCVD) technology that can reduce the S/D series resistance. The thickness of the residual SOI layer under the W-clad layer in the S/D region was 6 nm for an nMOSFET and 9 nm for a pMOSFET. For 0.15-μm-gate CMOSFETs, the subthreshold swings were 70 and 75 mV/dec for the nMOSFET and pMOSFET, respectively. The effectiveness of SWCVD technology when applied to ultrathin SOI devices was confirmed by small Si consumption and good continuity between the W and SOI layers. We expect that the S/D series resistance can be reduced to less than 1 kΩ-μm by optimizing the S/D implantation conditions     

Wannier-Stark oscillations in Zener tunneling currents

We have performed measurements of current-voltage characteristics at low temperatures in p-i-n diodes with a thin intrinsic region containing several (GaAs₅/(AlAs)₂ quantum wells. Under reverse bias, we found an oscillatory structure in the second derivative of the Zener tunneling current. The measurements agree well with theoretical calculations that are based on a transfer matrix approach and a realistic multi-band and multi-channel tight-binding scattering theory. The experiments show that Wannier-Stark oscillations in semiconductors occur in the d.c. current, in the regime of interband tunneling.     

A thorough study of quasi-breakdown phenomenon of thin gate oxidein dual-gate CMOSFET's

The conduction mechanism of the quasibreakdown (QB) mode for thin gate oxide has been studied in a dual-gate CMOSFET with a 3.7 nm thick gate oxide. Systematic carrier separation experiments were conducted to investigate the evolutions of gate, source/drain, and substrate currents before and after gate oxide quasibreakdown (QB). Our experimental results clearly show that QB is due to the formation of a local physically-damaged-region (LPDR) at Si-SiO₂ interface. At this region, the effective oxide thickness is reduced to the direct tunneling (DT) regime. The observed high gate leakage current is due to DT electron or hole currents through the region where the LPDR is generated. Twelve V_g, I_sub, I_sd/ versus time curves and forty eight I-V curves of carrier separation measurements have been demonstrated. All the curves can be explained in a unified way by the LPDR QB model and the proper interpretation of the carrier separation measurements. Particularly, under substrate injection stress condition, there is several orders of magnitude increase of I_sub(I_sd/) at the onset point of QB for n(p)-MOSFET, which mainly corresponds to valence electrons DT from the substrate to the gate, consequently, cold holes are left in the substrate and measured as substrate current. These cold holes have no contribution to the oxide breakdown and thus the lifetime of oxide after QB is very long. Under the gate injection stress condition, there is sudden drop and even change of sign of I_sub(I_sd/) at the onset point of QB for n(p)-MOSFET, which corresponds to the disappearance of impact ionization and the appearance of hole DT current from the substrate to the gate     

Direct tunneling gate leakage current in transistors with ultrathinsilicon nitride gate dielectric

We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si₃N₄) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms mere extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si ₃N₄ gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications     

A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs

This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.     

Excess tunneling currents in p-Si-n-3C-SiC heterostructures

An attempt is made to interpret the current-voltage characteristic of a p-Si-n-3C-SiC heterostructure in terms of the excess-tunneling mechanism. The space charge region width W and tunneling length λ are estimated. It is shown that W ? λ and, despite this, that the current transport through the heterostructure obeys the tunneling mechanism. The characteristic tunneling energy ?=57 meV, temperature coefficient of the saturation current, and the barrier thinness factor are found.     

Temperature effect on gate leakage currents in gate dielectric films of GaAs MOSFET

The gate dielectrics of Ga₂O₃(As₂O₃) of the GaAs MOSFET were prepared by a low-cost and low-temperature liquid-phase chemically enhanced oxidation method. The temperature and oxide thickness dependence of gate dielectric films on GaAs MOSFET have been investigated. The leakage current and dielectric breakdown field were both studied. Both gate leakage current density and breakdown electrical field were found to depend on the oxide thickness and operating temperature. The increasing trend in gate leakage current and the decreasing trend in breakdown electrical field were observed upon reducing oxide thickness from 30 to 12 nm and increasing operating temperature from −50°C to 200°C.     

Correlation between substrate and gate currents in MOSFET's

A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.     

Electron gate currents and threshold stability in the n-channel stacked gate MOS tetrode

A new structure is given for the n-channel stacked gate MOS tetrode which consists of a polycrystalline silicon buried control gate and thermally grown oxide for the offset gate insulator. As a result of the large band-bending in the offset gate depletion region of an operating tetrode, some drain current electrons surmount the Si-SiO2energy barrier and are injected into the oxide. Since the electron trapping is relatively small in the thermal-oxide offset gate insulator, it was possible to measure gate currents of up to2 times 10^{-4}A/cm². The gate current was measured as a function of the drain current, the drain voltage and the offset gate voltage. The resulting behavior confirms previous models of the tetrode device. Since electron trapping is much less in thermally grown oxide than in deposited pyrolytic oxide which was used formerly, the offset gate threshold voltage shifts less. As a result of this effect the new structure is used to advantage in fabricating the n-channel stacked gate tetrode in that the drain current is comparatively insensitive to changes in the offset gate voltage.     

A review of gate tunneling current in MOS devices

Gate current in metal–oxide–semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied in this paper. The physical mechanisms of tunneling in an MOS structure are reviewed, along with the particularities of tunneling in modern MOS transistors, including effects such as direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling and gate current partitioning. The modeling approach to gate current used in several compact MOS models is presented and compared. Also, some of the effects of this gate current in the performance of digital, analog and RF circuits is discussed, and it is shown how new effects and considerations will come into play when designing circuits that use MOSFETs with ultra-thin oxides.     

An analytical gate tunneling current model for MOSFETs

Gate tunneling current of MOSFETs is an important factor in modeling ultra small devices. In this paper, gate tunneling in present-generation MOSFETs is studied. In the proposed model, we calculate the electron wave function at the semiconductor-oxide interface and inversion charge by treating the inversion layer as a potential well, including some simplifying assumptions. Then we compute the gate tunneling current using the calculated wave function. The proposed model results have an excellent agreement with experimental results in the literature.     

Width dependence of substrate and gate currents in MOSFET's

Width dependence of hot-electron currents in MOSFET's fabricated with LOCOS, non-LOCOS, and a modified LOCOS processes are studied. The experimental results show that the substrate and gate currents are apparently enhanced in narrow width devices. The enhancement, however, is due to different voltage drops across the source-drain series resistance. The voltage drops are usually larger in wider devices. After correcting for the resistance effect, the substrate and gate currents scale with the device width. With this typical LOCOS process, the bird's beak and in-diffusion of field implant dopants do not cause excess hot-electron activities along the channel/field edges as has been suspected. Some other LOCOS process could, of course, produce a different result. Studies using wide test devices must consider the series resistance effect. With this precaution taken, models derived from wide-channel data will be applicable to narrow-channel devices, at least for some processes.