Multilayer model of indium arsenide epilayers

The charge carrier transport coefficients of an inhomogeneous thin semiconductor in a MOS structure were obtained using a multilayer model. The expression for the Hall coefficient of a three-layer system extended to arbitrary strength magnetic fields was used to separate the bulk transport parameters from the parameters describing transport at the two surfaces. Experimentally, a gate voltage was used to vary the surface under the oxide from depletion to accumulation, and the Hall coefficient was measured as a function of magnetic field. The characteristics of the back surface were obtained with the front surface held at the flat-band condition. The variation of the front surface parameters with gate voltage was obtained with the front surface in accumulation. The measurements were made on a MOS structure consisting of an InAs epilayer deposited by vapor phase epitaxy procedures on a semi-insulating GaAs substrate covered by a pyrolytic silicon dioxide insulating layer and an aluminum gate.     

An approach for quantum mechanical modeling and simulation for MOS devices, covering the whole operation region

A quantum mechanical (QM) approach for modeling and simulation of MOS devices, covering the whole operation region, was proposed. This formulation is applicable continuously from the subthreshold to the saturation regions, since it exactly treats the QM effects on the in-depth distribution of the gate induced carriers in the channel by solving one dimensional Poisson equation and Schrödinger equation self-consistently and it treats the lateral drift–diffusion transport using quasi-Fermi potential. A QM simulator was implemented using this QM approach. This QM simulator was verified by classical three-dimensional device simulator, CADDETH, in the whole range of operation of bulk MOSFET with low dopant density where QM effect is negligible. The QM simulation elucidated that the threshold voltage shift in thin SOI MOSFETs in saturation region as well as in linear region results from energy shift of the lowest conduction electron level and effective increase of gate oxide thickness.     

Threshold voltage calculation in ultrathin-film SOI MOSFETs using the effective potential

The success of the effective potential method of including quantum confinement effects in simulations of MOSFETs is based on the ability to calculate ahead of time the extent of the Gaussian wave packet used to describe the electron. In the calculation of the Gaussian, the inversion layer is assumed to form in a triangular potential well, from which a suitable standard deviation can be obtained. The situation in an ultrathin silicon-on-insulator (SOI) MOSFET is slightly different, in that the potential well has a triangular bottom, but there is a significant contribution to the confinement from the rectangular barriers formed by the gate oxide and the buried oxide. For this more complex potential well, it is of interest to determine the range of applicability of the effective potential model with a constant standard deviation. In this paper, we include this effective potential model in Monte Carlo calculations of the threshold voltage of ultrathin SOI MOSFETs. We find that the effective potential recovers the expected trend in threshold voltage shift with decreasing silicon thickness, down to a thickness of approximately 3 nm.     

Current tunnelling through MOS devices

In this study, we have calculated the tunnelling current through ultra thin gate oxides for MOS structure. In the aim to reduce the large gate leakage while scaling SiO₂ down oxide thickness, it has become necessary to use high-k gate dielectrics. We have used HfO₂/SiO₂ dual layer as gate oxide. According to the importance of these alternative gate dielectrics, it becomes essential to take into account the existence of electron trap at the HfO₂/SiO₂ interface. The gate current of n poly-Si/HfO₂/trap/SiO₂/p Si substrate capacitors is underestimated for low voltage if the effect of traps is not taken into account. The influence of trap parameters like width, depth and material masse on gate current has been examined.     

SWNT array resonant gate MOS transistor

We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.     

Coulomb-blockade in nanometric Si-film silicon-on-nothing (SON) MOSFETs

The advantages of using architectures with gate nonoverlapped with source/drain have already been demonstrated in order to measure controlled single electron effects in planar MOSFETs. In this paper, we performed nonoverlapped silicon-on-nothing (SON) transistors with Si-film from 15 down to 9 nm. This leads to the fabrication of a quantum box (QB) defined by two lateral potential barriers in a thin Si-film (due to the camel's back shape of the potential along the channel), and by two vertical potential barriers due to the gate oxide and to the buried dielectric of the SON architecture. This small volume device behaves like a quantum box, and we demonstrated that its own capacitance and consequently the Coulomb-blockade properties were mainly determined by the conduction film thickness. As the SON technology allows us to perform higly-performant fully depleted devices from bulk substrate, we will see in this paper that such devices can easily be adapted in order to fabricate three-dimensional QB, which becomes an alternative to fabricate SET with standard CMOS process.     

Monte Carlo Simulations of High-Performance Implant Free In0.3Ga 0.7As Nano-MOSFETs for Low-Power CMOS Applications

The potential performance of implant free heterostructure In_0.3Ga_0.7As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a high-kappa dielectric. The MC simulations show that the 30 nm gate length implant free MOSFET can deliver a drive current of 2174 muA/mum at 0.7 V supply voltage. The drive current increases to 2542 muA/mum in the 20 nm gate length device, saturating at 2535 muA/mum in the 15 nm gate length one. When quantum confinement corrections are included into MC simulations, they have a negligible effect on the drive current in the 30 and 20 nm gate length transistors but lower the 15 nm gate length device drive current at 0.7 V supply voltage by 10%. When compared to equivalent Si based MOSFETs, the implant free heterostructure MOSFETs can deliver a very high performance at low supply voltage, making them suitable for low-power high-performance CMOS applications     

应用于超薄栅氧化CMOS器件的两种电荷泵改进技术的比较

本文提出了High-low multi-frequency(HLMF)和Average bottom-top-pulse(ABTP)两种电荷泵改进技术,用于提高表征超薄栅氧化CMOS器件界面缺陷的精度.结果表明,在电荷泵技术测量过程中,这两种改进技术能非常有效地扣除漏电流.同时,也分析了电荷泵电流曲线的几个典型特性.由于ABTP技术是用静态模式测量漏电流,所以,在大的负Vbase端,电荷泵电流曲线的尾部出现大的波动.通过比较,我们发现HLMF具有更高的精度,可以作为用于提升表征超薄栅氧化CMOS器件界面缺陷精度的一种重要技术.     

Carrier lifetime analysis in thin gate oxide FD-SOI n-MOSFETs by gate-induced drain current transients

The drain current (I_D) transients by switching the biasing condition are examined in FD-SOI MOSFETs with negative biased back gate voltage (V_BG). Special attention is paid to the influence of the gate-induced charge/discharge of the floating body on the I_D transient. The I_D transient appears not only by switching the front gate voltage (V_FG) but also by switching V_BG. It is also shown that the analysis of a small V_FG step transient is useful to examine the lifetime under different bias conditions. All the results can be explained by the transitional change of I_D − V_FG characteristics at different body-charge conditions.     

Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures

The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter.     

Polymer electrolyte gating of carbon nanotube network transistors

Network behavior in single-walled carbon nanotubes (SWNTs) is examined by polymer electrolyte gating. High gate efficiencies, low voltage operation, and the absence of hysteresis in polymer electrolyte gating lead to a convenient and effective method of analyzing transport in SWNT networks. Furthermore, the ability to control carrier type with chemical groups of the host polymer allows us to examine both electron and hole conduction. Comparison to back gate measurements is made on channel length scaling. Frequency measurements are also made giving an upper limit of approximately 300 Hz switching speed for poly(ethylene oxide)/LiClO(4) gated SWNT thin film transistors.     

Tunneling currents through ultra thin HfO2/Al2O3/HfO2 triple layer gate dielectrics for advanced MIS devices

The dramatic scaling down of silicon integrated circuits has led to an intensive study of high dielectric constant materials as an alternative to the conventional insulators currently employed in microelectronics, i.e., silicon dioxide, silicon nitride, or oxynitride, which seem to have reached their physical limit in terms of reduction of thickness due to large leakage gate current. Introducing a physically thicker high-K material can reduce the leakage current to the acceptable limit. There are many potential candidates for high-K gate dielectrics with the K-valves ranging from 9 to 80. These are Al₂O₃, Y₂O₃, La₂O₃, Ta₂O₅, TiO₂, ZrO₂ and HfO₂. It is important to study the various leakage mechanisms in these films with the aim of improving their leakage current characteristics for use in advanced microelectronics devices. A procedure for calculating the tunneling current for stacked dielectrics is developed and subsequently applied to ultra thin films with equivalent oxide thickness (EOT) of 3.0 nm. Tunneling currents have been calculated as a function of gate voltage for different structures. Direct and Fowler-Nordheim tunneling currents through triple layer dielectrics are investigated for substrate injection. Using exact tunneling transmission calculations, current density–gate voltage (J _g?V _g) characteristics for ultra thin single layer gate dielectrics with different thicknesses have been shown to agree well with recently reported experiments. Extensions of this approach demonstrate that tunneling currents in HfO₂/Al₂O₃/HfO₂ structure with equivalent oxide thickness of 3.0 nm can be significantly lower than that through single layer oxides of the same thickness.     

Influence of gate thermal oxide layer on InGaP/InGaAs doping-channel field-effect transistors

In this article, the significant effect of a thin gate thermal oxide layer on InGaP/InGaAs doping-channel field-effect transistors (DCFETs) is first demonstrated. When compared to the conventional InGaP/InGaAs DCFET, the device with the gate thermal oxide layer exhibits a higher gate turn-on voltage and nearly voltage-independent transconductances as the gate-to-source is biased form −0.75 V to 0 V, while the maximum transconductance is lower. Experimentally, the transconductance within 90% of its maximum value for gate voltage swing is 1.63 V in the gate-oxide device, which is greater than that of 1.35 V in the device without the gate thermal oxide layer. Furthermore, it maintains a high drain current level at negative gate bias in the gate-oxide device, which can be attributed that the thermal oxide layer with a considerably large energy gap absorbs more of gate negative voltage and the influence of negative voltage on the gate depleted thickness is relatively slight.     

Label-free DNA detection with a nanogap embedded complementary metal oxide semiconductor

A nanogap embedded complementary metal oxide semiconductor (NeCMOS) is demonstrated as a proof-of-concept for label-free detection of DNA sequence. When a partially carved nanogap between a gate and a silicon channel is filled with charged biomolecules, the gate dielectric constant and charges are changed. When the gate oxide thickness reduces, the threshold voltage is significantly affected by a change of the charges, whereas it is scarcely influenced by a change of the dielectric constant. In the case of DNA, those two factors act on the threshold voltage oppositely in an n-channel NeCMOS but collaboratively in a p-channel NeCMOS because of the negative charges of DNA. Hence, a p-channel NeCMOS with a thin gate oxide is more attractive for DNA detection because it enhances the shift of threshold voltage; that is, it improves the sensitivity of DNA detection. In addition, the shift of threshold voltage according to the nanogap length is also investigated and the longer nanogap shows more shift of the threshold voltage.     

Analysis of Scaling Strategies for Sub-30 nm Double-Gate SOI N-MOSFETs

State-of-the-art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the ultrathin silicon body (UTB) double-gate (DG) MOSFET and considering the main figures of merit (FOM) for the high-performance N-MOS transistor. The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short-channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field. As a consequence, the impact of surface roughness at the Si-oxide interface and the gate tunneling leakage current are substantially reduced compared to the case of highly doped bulk MOSFETs. According to our results, thanks to the suppression of gate leakage current, scaling of the UTB-DG MOSFET down to the 32 nm technology node appears possible adopting -based gate dielectrics. In spite of the improved mobility at given inversion charge density, the simulated on-currents are substantially lower than those required by the 2005 ITRS for the 45 and 32 nm nodes . Nonetheless, thanks to relaxed scaling of the oxide thickness, hence to reduced gate capacitance, the requirements in terms of intrinsic delay and power-delay product can be satisfied. The issue of variability is analyzed by evaluating the dependence of the key FOM on the variation of critical dimensions such as the thickness of the gate oxide and of the silicon layer.     

Carbon nanotube electronics

Presents experimental results on single-wall carbon nanotube field-effect transistors (CNFETs) operating at gate and drain voltages below 1V. Taking into account the extremely small diameter of the semiconducting tubes used as active components, electrical characteristics are comparable with state-of-the-art metal oxide semiconductor field-effect transistors (MOSFETs). While output as well as subthreshold characteristics resemble those of conventional MOSFETs, we find that CNFET operation is actually controlled by Schottky barriers (SBs) in the source and drain region instead of by the nanotube itself. Due to the small size of the contact region between the electrode and the nanotube, these barriers can be extremely thin, enabling good performance of SB-CNFETs.     

Structure, sodium ion role, and practical issues for β-alumina as a high-k solution-processed gate layer for transparent and low-voltage electronics

Sodium β-alumina (SBA)-based gate dielectric films have been developed for all solution-processed, transparent and low voltage field-effect transistors (FETs). Its high dielectric constant has been ascribed to sodium (Na+) ions in the crystal structure; however, there are no published experimental results concerning the contribution of Na+ ions to the dielectric behavior, and the degree of crystallinity of the thin films. In addition, as an ionic conductor, β-alumina could give rise to some issues such as leakage current caused by Na diffusion, threshold voltage shift due to interface charge accumulation and longer response time due to slower polarization of the Na+ ions. This paper will address these issues using zinc tin oxide (ZTO) FETs, and propose possible measures to further improve SBA-based gate materials for electronic devices.     

Characterization of Near-Interface Oxide Trap Density in Nitrided Oxides for Nanoscale MOSFET Applications

This paper presents the depth profile of oxide trap density, extracted from the dual gate processed thermally grown oxide in NO ambient and remote plasma nitrided oxides by using multifrequency and multitemperature charge pumping technique in conjunction with the tunneling model of trapped charges. Nitrided oxide is widely used to improve the reliability of nanoscale MOSFETs because it can decrease the degradation of gate oxide due to the generation of traps therein. Based on the measurement, the optimum nitrogen concentration in such typical nitrided process is discussed in correlation with the gate oxide thickness for nanoscale CMOSFETs.     

3-D Monte Carlo Simulation of the Impact of Quantum Confinement Scattering on the Magnitude of Current Fluctuations in Double Gate MOSFETs

For the scaling of ultrathin body double gate (UTB DG) MOSFETs to channel lengths below 10 nm, a silicon body thickness of less than 5 nm is required. At these dimensions the influence of atomic scale roughness at the interface between the silicon body and the gate dielectric becomes significant, producing appreciable body thickness fluctuations. These fluctuations result in a scattering potential related to the quantum confinement variation within the channel which, similarly to the interface roughness scattering, influences the mobility, the drive current and the intrinsic parameter variations. In this paper we have developed an ensemble Monte Carlo simulation approach to study the impact of quantum confinement scattering on the transport in sub-10 nm UTB DG MOSFETs, and the corresponding intrinsic parameter variations. By comparing the Monte Carlo simulations with drift-diffusion simulations we quantify the important contribution of the quantum confinement related scattering to the current fluctuations in such devices     

Study of reactive sputtering titanium oxide for metal-oxide-semiconductor capacitors

Metal oxide semiconductor (MOS) capacitors with titanium oxide (TiO_x) dielectric layer, deposited with different oxygen partial pressure (30, 35 and 40%) and annealed at 550, 750 and 1000 °C, were fabricated and characterized.Capacitance-voltage and current-voltage measurements were utilized to obtain, the effective dielectric constant, effective oxide thickness, leakage current density and interface quality. The obtained TiO_x films present a dielectric constant varying from 40 to 170 and a leakage current density, for a gate voltage of − 1 V, as low as 1 nA/cm² for some of the structures, acceptable for MOS fabrication, indicating that this material is a viable high dielectric constant substitute for current ultra thin dielectric layers.