The SINFET: a new high conductance, high switching speed MOS-gated transistor

A new MOS power semiconductor device with a very low on-resistance and a switching speed comparable to conventional n-channel power MOSFETs is described. The fabrication process is similar to that of an n-channel lateral DMOS transistor but with the conventional high-low `ohmic? drain contact replaced by a Schottky contact. In operation, the Schottky contact injects minority carriers to conductivity-modulate the n- drift region, thereby reducing the on-resistance by a factor of about ten compared with those of conventional n-channel power MOSFETs of comparable size and voltage capability. Furthermore, since only a small number of minority carriers are injected, the device speed is comparable to conventional n-channel power MOSFETs.     

Hybrid Schottky injection MOS-gated power transistor

A modified Schottky injection field effect transistor (SINFET) which offers lower on-resistance and a switching speed comparable to conventional n-channel LDMOSTs is described. The fabrication process is similar to that of an LDMOS transistor but with the high-low (n+n-) `ohmic? contact at the drain replaced by a parallel combination of a Schottky barrier and a pn junction diode. This hybrid anode injects minority carriers into the n- drift region, which in turn provides conductivity modulation. A current handling capability 3.5 times larger than that of the LDMOST is achieved. With the minority carrier injection level limited by the Schottky barrier, the total amount of minority carriers injected by the hybrid anode is much lower than that injected by the pn junction diode alone. Thus, the device speed is comparable to the conventional n-channel LDMOST. By minimising the shunting resistance in the p-channel region, devices with a latch-up current density of 400 A/cm2 are obtained.     

High-power conductivity-modulated FET's (COMFET's) with a p-type channel

In previous work, a conductivity-modulated field-effect transistor (COMFET) having drastically reduced on-resistance was described; that device was based on n-channel MOS technology. In this letter, we report the development of a complementary device-the p-channel COMFET. These new p-channel COMFET's have demonstrated dc on-resistance values as low as 0.07 Ω at 20 A (for a 3 mm × 3 mm pellet), while providing forward blocking voltages of 200-400 V. To our knowledge, this on-resistance value (normalized to the same active area) is lower than that of any p-channel power MOSFET (even those with blocking voltages of only 100 V) and as much as 30 times less than that of a p-channel MOSFET with a comparable blocking-voltage capability. Using suitable minority-carrier-lifetime control techniques, drain-current-decay times have been reduced from ≈ 30 µs to below 1 µs.     

Optimized design of 4H-SiC floating junction power Schottky barrier diodes

SiC floating junction Schottky barrier diodes were simulated with software MEDICI 4.0 and their device structures were optimized based on forward and reverse electrical characteristics.Compared with the conventional power Schottky barrier diode,the device structure is featured by a highly doped drift region and embedded floating junction region,which can ensure high breakdown voltage while keeping lower specific on-state resistance,solved the contradiction between forward voltage drop and breakdown voltage.The simulation results show that with optimized structure parameter,the breakdown voltage Can reach 4 kV and the specific on-resistance is 8.3 mΩ·cm2.     

The COMFET—A new high conductance MOS-gated device

A new MOS gate-controlled power switch with a very low on-resistance is described. The fabrication process is similar to that of an n-channel power MOSFET but employs an n^--epitaxial layer grown on a p⁺substrate. In operation, the epitaxial region is conductivity modulated (by excess holes and electrons) thereby eliminating a major component of the on-resistance. For example, on-resistance values have been reduced by a factor of about 10 compared with those of conventional n-channel power MOSFET's of comparable size and voltage capability.     

Lateral MOS-gated power devices-a unified view

The authors present a unified view of lateral MOS-gated power devices based on the underlying device physics. This unified view facilities a qualitative understanding of the relative merit of different devices and their performance. Various MOS-controlled power and high-voltage devices can be viewed in a unified approach depending on the type of MOS gate control of the main current flowing through the device. The majority-carrier devices tend to favor speed over on-resistance. The mixed (bipolar-type) devices tend to favor lower on-resistance than speed. Hybrid devices are between these two extremes. Specifically, for high-frequency, high-voltage, and low-current applications the lateral DMOS (LDMOS) transistor is the device with the most desirable characteristics. At lower switching frequency and low-to-moderate current levels, the lateral IGBT (LIGBT) provides the same functionality with substantial areas savings. Lateral MOS-controlled thyristors (LMCTs) are suitable for low switching speed, high current applications     

Silicon Carbide Power MOSFET Model and Parameter Extraction Sequence

A compact circuit simulator model is used to describe the performance of a 2-kV, 5-A 4-H silicon carbide (SiC) power DiMOSFET and to perform a detailed comparison with the performance of a widely used 400-V, 5-A Si power MOSFET. The model's channel current expressions are unique in that they include the channel regions at the corners of the square or hexagonal cells that turn on at lower gate voltages and the enhanced linear region transconductance due to diffusion in the nonuniformly doped channel. It is shown that the model accurately describes the static and dynamic performance of both the Si and SiC devices and that the diffusion-enhanced channel conductance is essential to describe the SiC DiMOSFET on-state characteristics. The detailed device comparisons reveal that both the on-state performance and switching performance at 25degC are similar between the 400-V Si and 2-kV SiC MOSFETs, with the exception that the SiC device requires twice the gate drive voltage. The main difference between the devices is that the SiC has a five times higher voltage rating without an increase in the specific on-resistance. At higher temperatures (above 100degC), the Si device has a severe reduction in conduction capability, whereas the SiC on-resistance is only minimally affected     

A novel simplified process for fabricating a very high densityp-channel trench gate power MOSFET

A novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is realized. The proposed process showed improved on-resistance characteristics of the device with increasing cell density and the cost-effective production capability due to the lesser number of processing steps. By using this process technique, a remarkably increased high density (100 Mcell/inch²) trench gate power MOSFET with a cell pitch of 2.5 μm could be effectively realized. The fabricated device had a low specific on-resistance of 1.1 mΩ-cm² with a breakdown voltage of -36 V     

A new high breakdown voltage lateral Schottky collector bipolar transistor on SOI: design and analysis

Using two-dimensional process and device simulation, we present for the first time, a new high breakdown voltage two-zone base extended buried oxide (BOX) lateral Schottky Collector Bipolar Transistor (SCBT) on silicon-on-insulator with a breakdown voltage as high as 12 times that of the conventional lateral Schottky collector bipolar transistor. We have explained the new design features of the proposed Schottky collector structure and the reasons for its significantly improved breakdown performance. The proposed structure is expected to be suitable in the design of the new generation scaled high voltage Schottky collector bipolar transistors for low power high speed analog applications.     

Performance optimization of InGaAs power LDMOSFET

In this paper, a power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on InGaAs is proposed to achieve substantial improvement in breakdown voltage, on-resistance and Baliga׳s figure-of-merit with reduced cell pitch. The proposed LDMOSFET contains two vertical gates which are placed in two separate trenches built in the drift region. The source and drain contacts are taken from the top. The modified device has a planer structure implemented on InGaAs which is suitable for medium voltage power integrated circuits. The performance of proposed device is evaluated using two-dimensional numerical simulations and results are compared with that of the conventional LDMOSFET. The proposed structure considerably reduces the electric field inside the drift region due to reduced-surface field (RESURF) effect even at increased doping concentration leading to improved design trade-off. The proposed device provides 144% higher breakdown voltage, 25% lower specific on-resistance, 8 times improvement in figure-of-merit, and 25% reduction in cell pitch as compared to the conventional device.     

Power MOSFET's for medium-wave and short-wave transmitters

This paper describes design and performance of a high-frequency power MOST used for switching-mode power amplifiers in the medium-wave (500 kHz to 1.5 MHz) or short-wave (1.5 MHz to 30 MHz) transmitters whose output power is in the vicinity of 1 kW. To obtain the drain-source voltages greater than 200 V with on-resistance remaining approximately 1 Ω, the offset gate length and field plate length of the high-frequency power MOST are optimized as well as offset gate layer concentration. Employing the molybdenum gate fabricated by RF diode sputter, the MOST operates at high speed with turn-on and turn-off times of 22 and 25 ns, respectively. A high-temperature operation test was performed to assure the stability and reliability of the device. The test results indicate that phosphosilicate glass polarization affects the device reliability only when offset gate layer concentration is much lower than the optimized value.     

A dual-metal-trench Schottky pinch-rectifier in 4H-SiC

Characteristics of high-voltage dual-metal-trench (DMT) SiC Schottky pinch-rectifiers are reported for the first time. At a reverse bias of 300 V, the reverse leakage current of the SiC DMT device is 75 times less than that of a planar device while the forward bias characteristics remain comparable to those of a planar device. In this work, 4H-SiC pinch-rectifiers have been fabricated using a small/large barrier height (Ti/Ni) DMT device structure. The DMT structure is specially designed to permit simple fabrication in SiC. The Ti Schottky contact metal serves as a self-aligned trench etch mask and only four basic fabrication steps are required     

Influence of pinning trap in Ti/4H–SiC Schottky barrier diode

Ti/4H–SiC Schottky barrier diode without any intentional edge termination is fabricated. The obtained properties, low on-resistance of 3 mΩ cm² and low leakage current of 10⁻⁴ A/cm² at 1000 V, are evaluated by device simulation considering pinning at metal/semiconductor interface. The breakdown voltage is explained by minimization of electric field enhancement at the Schottky electrode edge due to pinning. The leakage current corresponds to Schottky barrier tunneling current depending on drift layer doping and Schottky barrier height.     

Design criteria of high-Voltage lateral RESURF JFETs on 4H-SiC

Integrated power electronics on SiC have great potential in future power electronics applications. In this paper, a novel vertical channel lateral junction field-effect transistor structure with reduced surface electric field effect is proposed for the first time on 4 H-SiC to address existing challenges in lateral power devices on SiC. Based on an experimentally proven channel design, the detailed design procedure of such a device has been investigated. Design criteria to optimize device forward blocking as well as conduction characteristics are studied. Parameter tolerance and design windows are discussed considering practical issues in device fabrication. Designs that will lead to an optimized tradeoff between device breakdown voltage and specific on-resistance are shown. With an 8-/spl mu/m-long drift region, a 1535-V breakdown voltage and 3.24 m/spl Omega//spl middot/cm/sup 2/ specific on-resistance can be achieved. This represents a figure-of-merit of 737 MW/cm/sup 2/, about 100 times higher than that of the best normally off lateral power devices reported in the literature. The proposed device can be an attractive candidate for power integrated circuit on SiC.     

A compact efficient Schottky collector transistor switch

A vertical Schottky collector transistor switch with merged vertical n-p-n load is described which is useful in both memory and logic applications. The device has been fabricated in an infant oxide isolated bipolar technology with Schottky collector area of 3.8 /spl mu/m/spl times/5.0 /spl mu/m (0.15 mil/spl times/0.2 mil). The intrinsic n-p-n load transistor directly below the Schottky collector requires no additional surface area. Contact location to extrinsic device regions is not restricted, providing wiring flexibility. Current gains of 3 and 4 have been obtained for prototype Schottky collector and n-p-n transistors, respectively. A power-delay product of 60 fJ/V has been observed on a 25-state (fan-out=1) closed-loop inverter chain using 5 /spl mu/m metal lines and spaces. A 5.0 ns delay at 15 /spl mu/A/stage (power-delay product=75 fJ/V) reveals potential for fast, low power VLSI application. The intrinsic speed limit of 2.76 ms is attained at 60 /spl mu/A/stage.     

具有埋层的大功率集成器件二维简化模型分析

对具有埋层结构的集成大功率器件提出了导通电阻自限制二维模型.在假定条件成立时,推导出器件二维模型导通电阻自限制公式,得出了具有埋层结构的集成大功率器件结构其比导通电阻是随着面积不断增大的结论.通过实验,证实了该结论预测趋势的正确性.该结论对类似集成化大功率器件结构设计具有一定的指导作用.     

Evaluation of the ruggedness of power DMOS transistor from electro-thermal simulation of UIS behaviour

High-voltage power MOSFETs have been widely used in switching mode power supply circuits as output drivers for industrial and automotive electronic control systems. However, as the device size is reduced, the energy handling capability is becoming a very important issue to be addressed together with the trade-off between the series on-resistance R_ON and breakdown voltage V_BR. Unclamped inductive switching (UIS) condition represents the circuit switching operation for evaluating the “ruggedness”, which characterizes the device capability to handle high avalanche currents during the applied stress. In this paper we present an experimental method which modifies the standard UIS test and allows extraction of the maximum device temperature after the applied standard stress pulse vanishes. Corresponding analysis and non-destructive prediction of the ruggedness of power DMOSFETs devices supported by advanced 2-D mixed mode electro-thermal device and circuit simulation under UIS conditions using calibrated physical models is provided also. The results of numerical simulation are in a very good correlation with experimental characteristics and contribute to their physical interpretation by identification of the mechanism of heat generation and heat source location and continuous temperature extraction.     

30 V UMOS中影响导通电阻平坦度的因素分析

功率MOSFET作为开关器件时,导通电阻的平坦度是衡量其性能的重要参数。研究影响导通电阻平坦度的因素,并对其进行优化,有助于改善器件的性能。低压UMOS中,沟道电阻是导通电阻的主要部分。文章以沟道电阻为分析对象,利用公式分析影响因素,通过Sentaurus TCAD仿真验证了导通电阻平坦度的变化趋势。通过改变P型基区离子注入剂量和栅氧层厚度进行仿真。仿真结果表明,通过减小栅氧层厚度和减少P型基区注入剂量,可获得较好的导通电阻平坦度。     

基于肖特基二极管的太赫兹功率探头研究

目前的太赫兹功率探头主要采用热敏电阻和热电偶作为功率检测器件,测量速度较慢。肖特基二极管具有较快 的检波速度,但是在太赫兹频段检波灵敏度降低,功率检测实现的难度很大,本文对基于肖特基二极管的太赫兹功率探 头设计技术进行研究,采用双平衡检波、渐变波导匹配、小信号斩波放大、温度补偿等技术,实现了肖特基二极管在太 赫兹频段的高灵敏度、高稳定性功率检测,试验结果表明：0.11THz~0.325THz 频段端口驻波比优于1.35,灵敏度优于 -40dBm。     

Conduction power loss in MOSFET synchronous rectifier withparallel-connected Schottky barrier diode

The conduction power loss in an MOSFET synchronous rectifier with a parallel-connected Schottky barrier diode (SBD) was investigated. It was found that the parasitic inductance between the MOSFET and SBD has a large effect on the conduction power loss. This parasitic inductance creates a current that is shared by the two devices for a certain period and increases the conduction power loss. If conventional devices are used for under 1 MHz switching, the advantage of the low on-resistance MOSFET will almost be lost. To reduce the conduction loss for 10 MHz switching, the parasitic inductance must be a subnanohenley