共查询到20条相似文献,搜索用时 31 毫秒
1.
A 1-V, 8-bit pipelined ADC is realized using multi-phase switched-opamp (SO) technique. A novel loading-free architecture is proposed to reduce the capacitive loading and to improve the speed in low-voltage SO circuits. Employing the proposed loading-free pipelined ADC architecture together with double-sampling technique and a fast-wake-up dual-input-dual-output switchable opamp, the ADC achieves 100-MS/s conversion rate, which to our knowledge is the fastest ADC ever reported at 1-V supply using SO technique, with performance comparable to that of many high-voltage switched-capacitor (SC) ADCs. Implemented in a 0.18-mum CMOS process, the ADC obtains a peak SNR of 45.2 dB, SNDR of 41.5 dB, and SFDR of 52.6 dB. Measured DNL and INL are 0.5 LSB and 1.1 LSB, respectively. The chip dissipates only 30 mW from a 1-V supply 相似文献
2.
A 9-bit 1.0-V pipelined analog-to-digital converter has been designed using the switched-opamp technique. The developed low-voltage circuit blocks are a multiplying analog-to-digital converter (MADC), an improved common-mode feedback circuit for a switched opamp, and a fully differential comparator. The input signal for the converter is brought in using a novel passive interface circuit. The prototype chip, implemented in a 0.5-μm CMOS technology, has differential nonlinearity and integral nonlinearity of 0.6 and 0.9 LSB, respectively, and achieves 50.0-dB SNDR at 5-MHz clock rate. As the supply voltage is raised to 1.5 V, the clock frequency can be increased to 14 MHz. The power consumption from a 1.0-V supply is 1.6 mW 相似文献
3.
Jipeng Li Un-Ku Moon 《Solid-State Circuits, IEEE Journal of》2004,39(9):1468-1476
A time-shifted correlated double sampling (CDS) technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. An efficient common-mode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18-/spl mu/m CMOS process, the prototype 10-bit pipelined ADC occupies 2.5 mm/sup 2/ of active die area. With 1-MHz input signal, it achieves 65-dB SFDR and 54-dB SNDR at 100MS/s. For 99-MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8-V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline. 相似文献
4.
Ramirez-Angulo J. Sawant M.-S. Thoutam S. Lopez-Martin A.J. Carvajal R.G. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2006,53(4):289-293
A new low-voltage CMOS Class AB/AB fully differential opamp with rail-to-rail input/output swing and supply voltage lower than two V/sub GS/ drops is presented. The scheme is based on combining floating-gate transistors and Class AB input and output stages. The op amp is characterized by low static power consumption and enhanced slew-rate. Moreover the proposed opamp does not suffer from typical reliability problems related to initial charge trapped in the floating-gate devices. Simulation and experimental results in 0.5-/spl mu/m CMOS technology verify the scheme operating with /spl plusmn/0.9-V supplies and close to rail-to-rail input and output swing. 相似文献
5.
Gil-Cho Ahn Dong-Young Chang Brown M.E. Ozaki N. Youra H. Yamamura K. Hamashita K. Takasuka K. Temes G.C. Un-Ku Moon 《Solid-State Circuits, IEEE Journal of》2005,40(12):2398-2407
A 0.6-V 2-2 cascaded audio delta-sigma ADC is described. It uses a resistor-based sampling technique which achieves high linearity and low-voltage operation without subjecting the devices to large terminal voltages. A low-distortion feed-forward topology combined with nonlinear local feedback results in enhanced linearity by reducing the sensitivity to opamp distortion, and allows increased input amplitude, resulting in higher SNDR. The modulator achieves 82-dB dynamic range and 81-dB peak SNDR in the A-weighted audio signal bandwidth with an OSR of 64. The total power consumption of the modulator is 1 mW from a 0.6-V supply. The prototype occupies 2.9 mm/sup 2/ using a 0.35-/spl mu/m CMOS technology. 相似文献
6.
Fiorenza J. K. Sepke T. Holloway P. Sodini C. G. Lee H.-S. 《Solid-State Circuits, IEEE Journal of》2006,41(12):2658-2668
A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves replacing the operational amplifier in a standard switched-capacitor circuit with a comparator and a current source. During charge transfer, the comparator detects the virtual ground condition in place of the opamp which normally forces the virtual ground condition. A prototype 1.5-bit/stage 10-bit 7.9-MS/s pipeline ADC was designed using the comparator-based switched-capacitor technique. The prototype ADC was implemented in 0.18-mum CMOS. It achieves an ENOB of 8.6 bits for a 3.8-MHz input signal and dissipates 2.5 mW 相似文献
7.
A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters 总被引:1,自引:0,他引:1
Hwi-Cheol Kim Deog-Kyoon Jeong Kim W. 《IEEE transactions on circuits and systems. I, Regular papers》2006,53(4):795-801
This paper presents a partially switched-opamp technique for a high-speed, low-power pipelined analog-to-digital converter (ADC). Unlike a conventional switched-opamp technique, only the second stage of a two-stage opamp is switched with the enhanced power efficiency and the drawbacks of an opamp sharing technique and a conventional switched-opamp technique are addressed. The prototype of 8-bit 200-MS/s pipelined ADC is implemented in a 0.18-/spl mu/m CMOS process technology. This converter achieves 55.8-dB spurious free dynamic range, 47.3-dB signal-to-noise-plus-distortion ratio, 7.68 effective number of bits for a 90-MHz input at full sampling rate, and consumes 30-mW from a 1.8-V supply. The active area of the ADC is 0.15 mm/sup 2/. 相似文献
8.
A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR 总被引:6,自引:0,他引:6
A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW. 相似文献
9.
Morizio J.C. Hoke I.M. Kocak T. Geddie C. Hughes C. Perry J. Madhavapeddi S. Hood M.H. Lynch G. Kondoh H. Kumamoto T. Okuda T. Noda H. Ishiwaki M. Miki T. Nakaya M. 《Solid-State Circuits, IEEE Journal of》2000,35(7):968-976
This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 μm CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections 相似文献
10.
A modified switched-opamp technique is proposed to enable switched-capacitor (SC) circuits to operate at 1 V with the opamp fully functional in all phases. A 1-V fully differential two-switchable-output-pair operational amplifier has been designed for the proposed technique, which is then employed in a 1-V fully differential SC pseudo-2-path filter. Implemented in a standard single-poly triple-metal 0.5-μm CMOS process, the filter achieves a sixth-order bandpass response centered at 75 kHz with a quality factor of 45. Capacitors formed with polysilicon and highly doped n-well (cap-well option) regions are used to achieve both good linearity and small chip area. At 1-V supply, the filter obtains an output swing of 1.2 Vpp and a dynamic range of 51 db while dissipating 310 μW and occupying a chip area of 0.8 mm2 相似文献
11.
Kanda K. Nose K. Kawaguchi H. Sakurai T. 《Solid-State Circuits, IEEE Journal of》2001,36(10):1559-1564
In sub-1-V CMOS designs, especially around 0.5-V CMOS designs, on-state drain current of MOSFETs shows positive temperature dependence, being different from the negative temperature dependence in the conventional voltage designs. Combined with low threshold voltage less than 0.2 V, the possibility of temperature instability increases. This paper describes possible temperature instabilities in the low-voltage regime by using circuit simulation environments incorporating temperature change in time and experiments using MOSFETs and the 32-bit adder circuit in quarter-micrometer CMOS technology with a low threshold voltage of 0.25 V 相似文献
12.
《IEEE transactions on circuits and systems. I, Regular papers》2008,55(8):2188-2201
13.
This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters (ADC).The proposed calibration eliminates the errors of residual difference voltage induced by capacitor mismatch of pseudorandom(PN) sequence injection capacitors at the ADC initialization,while applies digital background calibration to continuously compensate the interstage gain errors in ADC normal operation.The presented technique not only reduces the complexity of analog circuit by eliminating the implementation of PN sequence with accurate amplitude in analog domain,but also improves the performance of digital background calibration by minimizing the sensitivity of calibration accuracy to sub-ADC errors.The use of opamps with low DC gains in normal operation makes the proposed design more compatible with future nanometer CMOS technology.The prototype of a 12-bit 40-MS/s pipelined ADC with the two-mode digital calibration is implemented in 0.18-μm CMOS process.Adopting a simple telescopic opamp with a DC gain of 58-dB in the first stage,the measured SFDR and SNDR within the first Nyquist zone reach 80-dB and 66-dB,respectively.With the calibration,the maximum integral nonlinearity (INL) of the ADC reduces from 4.75-LSB to 0.65-LSB,while the ADC core consumes 82-mW at 3.3-V power supply. 相似文献
14.
Demosthenous A. Panovic M. 《IEEE transactions on circuits and systems. I, Regular papers》2005,52(9):1721-1731
Analog computations such as four-quadrant multiplication, linear voltage-to-current conversion and sum-square or difference-square are fundamental for many analog signal processing systems. All these functions can be realized based on the principle of the linearized differential pair using floating-voltage sources. This paper describes an improved practical realization of this principle, which is particularly suited to analog VLSI computational systems. The proposed class-AB analog cells are very compact, exhibit low total harmonic distortion and low nonlinearity, have a wide bandwidth, and are compatible with low-power and low-voltage operation. A mathematical discussion on stability and harmonic distortion of the proposed realization is presented. Both simulated results and measurements from fabricated cell samples in a 0.8-/spl mu/m CMOS process are given. The described circuits operate from a single 2-V power supply. 相似文献
15.
Tsung-Sum Lee Chi-Chang Lu 《IEEE transactions on circuits and systems. I, Regular papers》2005,52(9):1752-1757
This paper describes the design strategy and implementation of a low-voltage pseudodifferential double-sampled timing-skew-insensitive sample-and-hold (S/H) circuit with low hold pedestal based on the Miller-effect scheme. The S/H circuit employs bootstrapped switches in order to facilitate low voltage operation. The design considerations for each building block are described in detail. The S/H circuit has been designed using a 0.35-/spl mu/m 2P4M CMOS technology and experimental results are presented. The 1.5-V S/H circuit operates up to a sampling frequency of 50 MHz with less than -54.6 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8 V/sub pp/. In these conditions, a differential hold pedestal of less than 0.8 mV, 1.6 ns acquisition time at 0.8-V step input, and 0.8 V/sub pp/ full-scale differential input range are achieved. 相似文献
16.
Hiraki M. Uano K. Minami M. Sato K. Matsuzaki N. Watanabe A. Nishida T. Sasaki K. Seki K. 《Solid-State Circuits, IEEE Journal of》1992,27(11):1568-1574
A BiCMOS logic circuit applicable to sub-2-V digital circuits has been developed. A transiently saturated full-swing BiCMOS (TS-FS-BiCMOS) logic circuit operates twice as fast as CMOS at 1.5-V supply. A newly developed transient-saturation technique, with which bipolar transistors saturate only during switching periods, is the key to sub-2-V operation because a high-speed full-swing operation is achieved to remove the voltage loss due to the base-emitter turn-on voltage. Both small load dependence and small fan-in dependence of gate delay time are attained with this technique. A two-input gate fabricated with 0.3-μm BiCMOS technology verifies the performance advantage of TS-FS-BiCMOS over other BiCMOS circuits and CMOS at sub 2-V supply 相似文献
17.
Borgatti M. Felici M. Ferrari A. Guerrieri R. 《Solid-State Circuits, IEEE Journal of》1998,33(7):1082-1089
In this paper, a low-power, low-voltage speech processing system is presented. The system is intended to he used in remote speech recognition applications where feature extraction is performed on terminal and high-complexity recognition tasks and moved to a remote server accessed through a radio link. The proposed system is based on a CMOS feature extraction chip for speech recognition that computes 15 cepstrum parameters, each 8 ms, and dissipates 30 μW at 0.9-V supply. Single-cell battery operation is achieved. Processing relies on a novel feature extraction algorithm using 1-bit A/D conversion of the input speech signal. The chip has been implemented as a gate array in a standard 0.5-μm, three-metal CMOS technology. The average energy required to process a single word of the TI46 speech corpus is 10 μJ. It achieves recognition rates over 98% in isolated-word speech recognition tasks 相似文献
18.
《IEEE transactions on circuits and systems. I, Regular papers》2009,56(5):966-974
19.
Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes have an adverse effect on area and power consumption and, more seriously, do not scale easily to low-voltage processes. We describe a digital technique which removes the accuracy constraints from the comparators. With no analog matching requirements, the comparators can be small, fast, and power efficient. A 6-bit prototype converter built in a standard 0.25-μm digital CMOS process occupies 1.2 mm2 and dissipates 150 mW from a 2.2-V supply at 400 MS/s 相似文献
20.
Dong-Young Chang Un-Ku Moon 《Solid-State Circuits, IEEE Journal of》2003,38(8):1401-1404
A low-voltage opamp-reset switching technique (ORST) that does not use clock boosting, bootstrapping, switched-opamp (SO), or threshold voltage scaling is presented. This technique greatly reduces device reliability issues. Unlike the SO technique, the opamps stay active for all clock phases and, therefore, the ORST is suitable for high-speed applications. This new switching technique is applied to the design of a 10-bit 25-MS/s pipelined analog-to-digital converter (ADC). The prototype ADC was fabricated in a 0.35-/spl mu/m CMOS process and demonstrates 55-dB signal-to-noise ratio, 55-dB spurious-free dynamic range, and 48-dB signal-to-noise-plus-distortion ratio performance with a 1.4-V power supply. The total power consumption is 21 mW. The ADC's minimum operating power supply is 1.3 V (|V/sub TH,P/| = 0.9 V) and the maximum operating frequency is 32 MS/s. The ORST is fully compatible with future low-voltage submicron CMOS processes. 相似文献