Electrical models of TFT‐LCD panels for circuit simulations

Abstract— As thin‐film‐transistor liquid‐crystal‐display (TFT‐LCD) panels become larger and provide higher resolution, the propagation delay of the row and column lines, the voltage modulation of Vcom, and the response time of the liquid crystal affect the display images now more than in the past. It is more important to understand the electrical characteristics of TFT‐LCD panels these days. There are several commercial products that simulate the electrical and optical performance of TFT‐LCDs. Most of the simulators are made for panel designers. However, this research is for circuit, system, and panel designers. It is made in a SPICE and Cadence environment as a commercial circuit‐design tool. For circuit and system designers, it will help to design the circuit around a new driving method. Also, it can be easily modified for every situation. It also gives panel designers design concepts. This paper describes the electrical model of a 15‐in. XGA (1024 × 768) TFT‐LCD panel. The parasitic resistance and capacitance of the panel are obtained by 3‐D simulation of a subpixel. The accuracy of these data is verified by the measured values of an actual panel. The developed panel simulation platform, the equivalent circuit of a 1 5‐in. XGA panel, is simulated by HSPICE. The results of simulation are compared with those of experiment, according to changing the width of the OE signal. The proposed simulation platform for modeling TFT‐LCD panels can be especially applied to large‐sized LCD TVs. It can help panel and circuit designers to verify their ideas without making actual panels and circuits.     

Recent developments in large‐area photomasks for display applications

One of the most critical areas in the manufacturing process for FPD panels or shadow masks for CRTs is lithography. Most existing lithography technologies require high‐quality large‐area photomasks. The requirements on these photomasks include positioning accuracy (registration) and repeatability (overlay), systematic image quality errors (“mura” or display quality), and resolution (minimum feature size). The general trend toward higher resolution and improved performance, e.g., for TFT desktop monitors, has put a strong focus on the specifications for large‐area‐display photomasks. This article intends to give an overview of the dominant issues for large‐area‐display photomasks, and illustrates differences compared with other applications. The article will also present state‐of‐the‐art methods and trends. In particular, the aspects of positioning accuracy over large areas and systematic image‐quality errors will be described. New qualitative and objective methods have been developed as means to capture systematic image‐quality errors. Results indicating that errors below 25 nm can be found early in the manufacturing process is presented, thus allowing inspection for visual effects before the actual display is completed. Positioning accuracy below 400 nm (3 sigma) over 720 × 560 mm have been achieved. These results will in the future be extended up toward 1 × 1 m for generation 4 in TFT‐LCD production.     

Toward sub‐micron oxide thin‐film transistors for digital holography

High‐performance 2‐μm‐channel oxide thin‐film transistors (TFT) on glass substrate for a 7‐μm‐pixel‐pitch spatial light modulator panel for digital holography applications were fabricated using a two‐step source/drain etching process. It showed a μ_FE of 45.5 cm²/Vs, SS of 0.10 V/dec, and Von of near zero voltage. Furthermore, we succeeded in the demonstration of sub‐micron TFTs, which is an indispensable route to next‐generation spatial light modulation devices with near 1‐μm pixel pitch. The issue of short‐channel transistors for display applications is also introduced. Finally, the digital holographic demonstration results based on the fabricated backplane are presented.     

Development of 100‐in. TFT‐LCDs for HDTV and public‐information‐display applications

Abstract— LCDs have achieved a full‐high‐definition resolution of 1920 × 1080 (16:9), 600‐nit brightness, 3000:1 dynamic contrast ratio, 92% color gamut, 178° viewing angle, and 5‐msec response time at all gray levels and are targeted for HDTV and public‐information‐display applications. Some unique technologies, such as Cu bus line, advanced wide view polarizer, and wide‐color‐gamut lamp, were applied. A new stitching‐free technology was developed to overcome the size limitation of the photomask in both the TFT and color‐filter processes. The size of the panel (100 in.), based on the wide format (16:9), is determined by the maximum efficiency of the world's first seventh‐generation line (glass size, 1950 × 2250 mm) in LG.Philips LCD's (LPL) Paju display cluster. The issues facing 100‐in. TFT‐LCDs will be discussed.     

High‐uniformity 2T1C AMOLED panels by a built‐in trimming method

Abstract— A new built‐in trimming scheme boosting the OLED driving current through analog programming of the driver p‐channel TFT is proposed. By using a selective programming operation, the current variation on the LTPS panel can be reduced to less than 1%. Another blanket‐boosting method is investigated for concurrent programming of the entire panel. This blanket‐boosting scheme has been successfully demonstrated on a 2.4‐in. AMOLED panel where the non‐uniformity improved from 8.1 to 4.9% under a worst‐case condition.     

Critical point defect detection for small‐pixel thin‐film transistor array applied to medical display

Thin‐film transistor (TFT) array testing technique has been used, which provides defect detection capability to control the yield of the TFT process. In the past, several defect inspection technologies have been developed and applied for the TFT array testing. When the TFT array pixel size is getting smaller and the resolution is higher, they also encounter the performance limitation on detecting the critical defect in this small‐pixel TFT array and facing a limited testing requirement. For medical display applications, the display pixels on an array panel are getting smaller and smaller; therefore, defect detection is getting more important and critical for managing yield with quality. In this study, a novel approach for defect detection was proposed. Here, the proposed voltage imaging technique is used for the TFT array test, and it provides better small‐pixel TFT array defect detection capability. The experimental results show that by using the voltage imaging technique, detecting critical point defect of TFT array can be effectively improved. And the detected small‐pixel size of TFT array panels can be smaller than 55 µm of an advanced medical display.     

Transflective TFT‐LCDs with high optical performance

Abstract— In order to reduce panel cost, reduce power consumption, and minimize thickness, a single panel with dual functions for high‐transmissive main displays and high reflective sub‐displays is becoming the trend. Two novel RGB‐W transflective 1.9‐in. a‐Si TFT LCDs have been developed to meet the requirements. By using the traditional seven‐mask dual‐cell‐gap structure, novel transflective tRGB‐t/rW TFT LCD and tRGB‐rW TFT‐LCD panels were fabricated with high transmittance and high reflectance, respectively. The optical clarity is excellent in both dark and bright conditions. Their superior optical performance is attributed to the high‐efficiency “transflective white” subpixel or “reflective white” subpixel.     

Improved image quality of a high‐transflective tRGB‐t/rW TFT‐LCD

Abstract— This work combines a very simple resolution rescaling method, a well‐known RGB‐to‐YUV converting technique and a detection strategy into an optimized switchable mechanism in order to eliminate the problems of obvious zigzag profiles caused by the special layouts of transflective tRGB‐t/rW TFT‐LCDs and the poor reflective gray‐level contrast ratio effected by the minimum white data in the transmissive RGB‐W + subpixel rendering algorithms. Finally, a transflective tRGB‐t/rW TFT‐LCD is revealed not only to have no visible zigzag profiles and high visibility of reflective gray‐level contrast ratio, but also to have extreme reflectance and transmittance. The excellent optical performance of the proposed system makes it particularly suitable for single‐panel applications that need both high‐transmissive main displays and high‐reflective subdisplays.     

New approaches to process simplification for large‐area high‐resolution TFT‐LCDs

Abstract— Novel process architectures are proposed for fabricating large‐area high‐resolution TFT‐LCDs with a minimal number of process steps. A low contact resistance between Al bus lines and the transparent conductive oxide layer, necessary for large‐area panels, is obtained by inducing a self‐formed inter‐metallic compound layer at the interface without using any additional buffer or capping layers. For enhanced brightness and resolution, a new TFT array structure integrated on a color‐filter substrate, referred to as an Array on Color Filter (AOC) structure, has been developed. Good‐quality TFTs were successfully constructed on the newly developed color filter for AOC within a sufficiently wide process margin. By adopting these novel technologies, a 15.0‐in. XGA prototype panel was fabricated and shows good display performance. Thus, these novel technologies have improved cost efficiency and productivity for TFT‐LCD manufacturing, and can be applied to the development of TFT‐LCDs of extended display area and enhanced resolution, benefiting from the low resistance bus lines, the high aperture ratio, and reduction in total process steps.     

Flexible AMOLEDs with low‐temperature‐processed TFT backplane technologies

Developments of backplane technologies, which are one of the challenging topics, toward the realization of flexible active matrix organic light‐emitting diodes (AMOLEDs) are discussed in this paper. Plastic substrates including polyimide are considered as a good candidate for substrates of flexible AMOLEDs. The fabrication process flows based on plastic substrates are explained. Limited by the temperature that plastic substrates can sustain, TFT technologies with maximum processing temperature below 400 °C must be developed. Considering the stringent requirements of AMOLEDs, both oxide thin‐film transistors (TFTs) and ultra‐low‐temperature poly‐silicon TFTs (U‐LTPS TFTs) are investigated. First, oxide TFTs with representative indium gallium zinc oxide channel layer are fabricated on polyimide substrates. The threshold voltage shifts under bias stress and under bending test are small. Thus, a 4.0‐in. flexible AMOLED is demonstrated with indium gallium zinc oxide TFTs, showing good panel performance and flexibility. Further, the oxide TFTs based on indium tin zinc oxide channel layer with high mobility and good stability are discussed. The mobility can be higher than 20 cm²/Vs, and threshold voltage shifts under both voltage stress and current stress are almost negligible, proving the potential of oxide TFT technology. On the other hand, the U‐LTPS TFTs are also developed. It is confirmed that dehydrogenation and dopant activation can be effectively performed at a temperature within 400 °C. The performance of U‐LTPS TFTs on polyimide is compatible to those of TFTs on glass. Also, the performance of devices on polyimide can be kept intact after devices de‐bonded from glass carrier. Finally, a 4.3‐in. flexible AMOLED is also demonstrated with U‐LTPS TFTs.     

Super‐large‐sized TFT‐LCD (55 in.) for HDTV application

Abstract— We have developed the world's largest TFT‐LCD, which has a 55‐in.‐diagonal size. This LCD features a 1920 × 1080 (16:9) resolution for full‐HDTV images, 500‐nit luminance, 72% color gamut, and 12‐msec response time at all gray levels. The size of the panel (55 in.) was determined by the maximum efficiency of our fifth‐generation line (glass size: 1100 × 1250 mm). To overcome the limitation of size in photolithography equipment, a new stitcking‐free technology was applied in both the TFT and color‐filter side. And the super‐IPS mode was used as a wide‐viewing‐angle technology because it is suitable in the fabrication of large panels. In this paper, we present issues on both the fabrication and characteristics of the 55‐in. TFT‐LCD.     

New era for TFT‐LCD size and viewing‐angle performance

Abstract— Samsung has announced the development of a full‐high‐definition (1920 × 1080) 82‐in. TFT‐LCD panel using Super‐PVA (S‐PVA) technology, the world's largest TFT‐LCD. In addition to the size breakthrough, this product achieves 600 nits of brightness, a contrast ratio of over 1200:1, an angle of view of 180°, a color gamut of 92%, and an 8‐msec response time. Several key enabling technologies were developed to achieve these specifications, including two‐transistor direct‐driven independently controlled S‐PVA subpixels, non‐even‐area‐ratio subpixels for optimal off‐axis gamma, gate overlap driving for larger driving margin, new CCFL technology for higher color gamut, and advanced fabrication techniques including the use of Samsung's new Gen 7 line. Many of these technologies will be applied to other products within Samsung's LCD‐TV product line. Samsung's broader development efforts toward the overall LCD‐TV market, including production status of the Gen 7 facility, will be updated.     

Development of 55” 4K UHD OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs

We investigated oxide TFT backplane technology to employ the internal gate driver IC (GIP circuit) on 55” 4K OLED TV panel. For the GIP circuit, we developed the high reliability oxide TFTs, especially only ?0.4 V Vth degradation under 100‐h long‐term PBTS stress and the short channel length TFTs (L = 4.5um) for narrow bezel. Consequently, we demonstrated the 55‐in 4K OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs.     

Incorporation of input function into displays using LTPS TFT technology

Abstract— A new display in which an input function is incorporated has been developed by using LTPS TFT technology. A new circuit configuration that includes a lateral p‐i‐n diode with an in‐pixel amplifier, an LTPS A/D converter on the periphery of the glass substrate and an external image‐processing LSI is presented. The experimental results of two major applications of the image‐capture function and touch‐panel function are discussed.     

IGZO‐TFT technology for large‐screen 8K display

We succeeded in G8 factory for mass production of Indium–Gallium–Zink–Oxide thin‐film transistor (IGZO‐TFT) for the first time in the world. The initial TFT process was an etching stop‐type TFT, but now, we are mass producing channel etching‐type TFTs. And, its application range is smartphones, tablets, PCs, monitors, TV, and so on. In particular, because of recent demands for high‐resolution and narrow frame, our IGZO display has been advanced in technology development with gate driver in panel. In this paper, we report development combining low resistance technology and the latest IGZO‐TFT (IGZO5) for large‐screen 8K display.     

A low‐cost low‐temperature thin‐film‐transistor backplane based on oxide semiconductor

Abstract— An indium‐gallium‐zinc‐oxide (IGZO) thin‐film transistor (TFT) based on an anodized aluminum‐oxide gate dielectric and photoresist passivation has been fabricated. The TFT showed a field‐effect mobility of as high as 18 cm²/V‐sec and a threshold voltage of only 0.5 V. A 50 × 50 AMOLED display based on this type of TFT was designed and fabricated. The average luminance of the panel was 150 cd/m², and the maximum pixel luminance was 900 cd/m².     

Investigation of the hysteresis phenomenon of an a‐Si:H TFT at an elevated temperature for AMOLED displays

Abstract— The temperature dependence of the hysteresis of an a‐Si:H TFT has been investigated. An a‐Si:H TFT pixel driving scheme has been proposed and investigated. This scheme can eliminate changes in the organic light‐emitting diode (OLED) current caused by hysteresis of an a‐Si:H TFT. The VTH of the a‐Si:H TFT was changed according to the gate‐voltage sweep direction because of the hysteresis of the a‐Si:H TFT. The variation of VTH for a a‐Si:H TFT decreased from 0.41 to 0.17 V at an elevated temperature of 60°C because the sub‐threshold slope (s‐slope) of the a‐Si:H TFT, in the reverse voltage sweep direction, increased more than in the forward voltage sweep direction due to a greater increase in the initial electron trapped charges than the hole charges. Although the OLED current variation caused by hysteresis decreased (～14%) as the temperature increased, the error in the OLED current needed to be improved in order to drive the pixel circuit of AMOLED displays. The proposed pixel circuit can apply the reset voltage (?10 V) before the data voltage for the present frame that was written to fix the sweep direction of the data voltage. The variation in the OLED current caused by hysteresis of the a‐Si:H TFT was eliminated by the fixed voltage sweep direction in the proposed pixel circuit regardless of operating temperature.     

Liquid‐crystal displays using printed plastic TFT backplanes

Abstract— In this paper, we present results from a new liquid crystal over plastic printed thin‐film‐transistor (TFT) display. The display demonstrator shows that the processing incompatibilities between the plastic TFT backplane and the liquid‐crystal materials can be addressed to make a stable twisted‐nematic structure. New fabrication processes such as the photo‐alignment of liquid crystals have made it possible to create a new generation of displays, which pave the way towards fully integrated plastic liquid‐crystal‐display technologies.     

Vertically integrated,double stack oxide TFT layers for high‐resolution AMOLED backplane

We developed a novel vertically integrated, double stack oxide thin‐film transistor (TFT) backplane for high‐resolution organic light‐emitting diode (OLED) displays. The first TFT layer is bulk‐accumulation mode, and the second TFT layer is a single gate with back‐channel etched structure. The extracted mobilities and threshold voltages are higher than 10 cm²/Vs and 0 ~ 1 V, respectively. Both TFTs are found to be extremely stable under the bias and temperature stress. The gate driver with width of 530 μm and a pitch of 18.6 μm was developed, exhibiting well shifted signal up to the last stage of 900 stages without output degradation, which could be used for 1360 ppi TFT backplane.     

Multioutputs single‐stage gate driver on array with wide temperature operable thin‐film‐transistor liquid‐crystal display for high resolution application

A hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) gate driver with multioutputs (eight outputs per stage) for high reliability, 10.7‐inch automotive display has been proposed. The driver circuit is composed of one SR controller, eight driving TFTs (one stage to eight outputs) with bridging TFTs. The SR controller, which starts up the driving TFTs, could also prevent the noise of gate line for nonworking period. The bridging TFT, using width decreasing which connects between the SR controller and the driving TFT, could produce the floating state which is beneficial to couple the gate voltage, improves the driving ability of output, and reaches consistent rising time in high temperature and low temperature environment. Moreover, 8‐phase clocks with 75% overlapping and dual‐side driving scheme are also used in the circuit design to ensure enough charging time and reduce the loading of each gate line. According to lifetime test results, the proposed gate driver of 720 stages pass the extreme temperature range test (90°C and ?40°C) for simulation, and operates stably over 800 hours at 90°C for measurement. Besides, this design is successfully demonstrated in a 10.7‐inch full HD (1080 × RGB×1920) TFT‐liquid‐crystal display (LCD) panel.