Characteristics of diffused P-N junctions in epitaxial layers

A one-dimensional analysis has been made to determine properties of diffused p-n junctions in epitaxial layers with nonuniform impurity concentration. Impurity diffusion from the surface and from the substrate is assumed to have complementary error function distribution. The transcendental equations obtained by analytical integration of Poisson's equation were evaluated numerically with the IBM 7090/94. Junction depth, impurity gradient and impurity level at the junction are given for a variety of diffusion parameters and impurity concentrations. In addition, graphs are presented, showing the relationship between reverse voltage and depletion layer thickness, capacitance per unit area, and peak electric field for the case of silicon. A comparison between the actual impurity profile and the usual linear approximation using the impurity gradient at the junction gives the range of depletion layer thickness or reverse voltage in which such an approximation is justified. Further, examples are presented of the electric field distribution in the depletion layer for several impurity concentration profiles. Calculated and experimentally determined values of some readily accessible junction characteristics show reasonably good agreement.     

Control of electric field at the surface of P-N junctions

Both degradation resulting from ion migration and surface breakdown ofp-njunctions depend strongly on electric field. These problems can be minimized or avoided by designingp-njunction devices so that the electric field at the surface is substantially lower than that within the body of the device. The shape, surface doping, and dielectric constant at the junction-surface interface have an appreciable influence on the electric field of the adjoining space charge layer. Using relaxation methods, solutions of Poisson's equation in two dimensions have been found which permit predictions of the surface fields as a function of surface geometry and dielectric coatings. Measurements of the surface field by probing the junctions are in good agreement with calculated values. This approach has led to the design of very high voltagep-njunction devices which exhibit body breakdown only. With the breakdown confined to the body of the device, the reverse power dissipation capability is not only predictable but significantly greater (typically 30 a at 1200 v for a 100 µsec pulse applied to a large area device) than that achievable with surface limited devices.     

Avalanche breakdown characteristics of a diffused P-N junction

A one-dimensional analysis is presented on the avalanche breakdown characteristics of a diffused p-n junction diode. By numerically integrating the carrier ionization rate in a junction space-charge layer, avalanche breakdown voltage is calculated for diffused diodes of silicon and germanium; this voltage is graphically illustrated throughout a range of parameters applicable to most practical situations. In addition, for calculating the maximum cutoff frequency of varactor diodes, junction capacity is similarly illustrated assuming the device is biased to avalanche breakdown. From these illustrations, and from an accompanying nomograph which relates the physical constants of a junction to its impurity atom gradient, the above parameters can be readily established without additional calculations. Further, examples are also presented to demonstrate the reduction of breakdown voltage resulting from a rapid increase of conductivity within the space-charge layer of a diffused p-n junction; this situation approximates many epitaxial and double diffused structures.     

Electron beam switched P-N junctions

A high-speed, high-power switching device is analyzed and experimental results presented. The device consists of a back-biased p-n junction switched by an electron beam. A single position tube for use as a magnetic core driver has been tested. The device operated at a beam voltage of 19 kv and can give a 150-v, 1.5-a output pulse with a rise time of less than 4 nsec and a maximum device power dissipation of 14 w. Designs for a multiposition device and also a high-power amplifier, similar in operation to the single position device are discussed.     

Space-charge layer width in diffused junctions

This paper outlines a calculation of space-charge layer width in a planar junction made by diffusing an n or p impurity (assumed to follow a Gaussian or a complementary error function distribution) into a uniformly doped crystal of opposite conductivity type. The collector junction of most drift transistors conforms closely to this model. An exponential approximation to the impurity distribution permits curves to be drawn of the space-charge layer penetration in each direction from the junction as a function of applied reverse voltage, and of the electric field distribution. The quantities involved are normalized in terms of the initial doping level N1, the impurity diffusion lengthL = 2 sqrt{Dt}, and the junction depth xj. The curves should be useful in calculating depletion-layer capacitance, transistor punch-through voltage and junction breakdown voltage.     

Depletion region thicknesses in diffused junctions

Closed-form expressions are derived for total thickness of the depletion region and thickness of the depletion region on the n side of the junction. The expressions are applicable to n-p junction devices with either complementary error function or Gaussian impurity distributions. Depletion region thicknesses obtained by evaluation of the closed-form expressions are in excellent agreement with exact numerical calculations.     

Avalanche breakdown in silicon diffused junctions

In silicon erfc or gaussian diffused junctions, as well as in linearly graded and step junctions, avalanche breakdown voltage is given approximately by V_B = (5.8 × 10⁴) X_T^0.84 where X_T is total depletion-layer thickness in cm and V_B is breakdown voltage in volts. This expression holds to ±9 per cent for plane junctions in the range 15 V to 1 kV, as indicated in Fig. 6, and should be useful to the practical device designer. The quantity X_T for a diffused junction of the erfc type can be obtained from Fig. 3, which extends the range of previously published curves and is somewhat easier to read as well. This chart and Fig. 4, which gives peak field , can be used to estimate quantitatively the departure of such a diffused junction from pure step or pure graded behavior. The generalized V_B-X_T relationship is based in part on the results of Sze and Gibbons. When their expressions for V_B in step and linearly graded junctions are recast in terms of X_T (instead of doping N_B and gradient a, respectively) these reduce to power-law expressions differing only in numerical coefficient ( 10 per cent difference). The expression's upper range, 300–1000 V, is based upon the recent diffused-junction data of van Overstraeten and de Man, and the lower range, 15–300 V, is also consistent with the experimental data of Miller on step junctions and Carlson on diffused junctions. Carlson's observations were made in about 1959 on large numbers of commercial diodes and have not previously been generally available. These sets of experimental data are compared with the calculated results of the workers mentioned above, plus the diffused-junction results of Kennedy and O'Brien.     

Breakdown voltage of diffused epitaxial junctions

The quantitative aspects of the breakdown-voltage calculations in reach-through-limited p⁺−n−n⁺ junctions are revisited, using numerical simulation. It is shown that the conventional abrupt-junction approximation may underestimate the breakdown voltage of diffused epitaxial junctions by as much as 60%, depending on junction depth. Oppositely, but less erroneously, a combined abrupt/linearly-graded approximation overestimates the breakdown voltage by at most 15%. A set of numerically calculated plots are provided for the design of low-voltage power devices.     

Avalanche breakdown of diffused silicon p-n junctions

Using impact ionization rates of Moll et al. [23] and Lee et al. [24], the avalanche breakdown voltages of diffused silicon p-n junctions were calculated by assuming an error function diffused impurity distribution. The theoretical results were verified experimentally with samples having breakdown voltages ranging from 100 volts to 9000 volts. Good agreement was found between the experimental breakdown voltages and those calculated with the data of Moll et al. This was seen even at high breakdown voltages where the ionizing fields were far lower than those for which ionization rates have been quoted.     

Monolithic photoreceiver integrating GaInAs PIN/JFET with diffused junctions

A new integrated PIN/JFET using an original three-layer GalnAs structure has been developed in order to optimise both devices separately. Thanks to the good performances and high reliability of individual components, the sensitivity of such monolithic photoreceivers is ? 33.7 dBm for a 10?9 bit error rate at 140 Mbit/s.     

Photoeffect in junction field effect transistors with drift velocity saturation

Photocurrents in junction field effect transistors under homogeneous illumination are analyzed theoretically taking into account drift velocity saturation by (i) the Trofimenkoff approximation, and (ii) an abrupt transition from a linear velocity-field relation to saturation. With the drain biased into saturation, the source current decreases more steeply with illumination than the drain current increases, the assymetry being a function of saturation drift velocity. At high illumination intensities drain current saturates with illumination intensity.     

Avalanche breakdown voltage of diffused junctions in silicon

A semi-theoretical relationship has been developed between the avalanche breakdown voltage and the product of the junction depth and background impurity concentration for plane, cylindrical and spherical diffused junctions. This has been confirmed experimentally for plane and cylindrical junctions, over the voltage range $\text{10 < V}{}_{\mathrm{B}}\text{< 9000}\text{V}$.     

Analytical approximations for diffused junctions under high-level conditions

A theoretical sutdy is made of the applicability of a previously-proposed diffused-junction model to diffused junctions with varying degrees of steepness in the impurity profile. This is done by comparing the predictions of the model with the exact numerical solutions obtained for a series of silicon p⁺n diffused junctions, ranging from very gradual junctions to the infinitely steep or ideal step junctions, and with the lightly-doped side of the junction in each case under high-level injection conditions. The results indicate that the range of validity of the model extends from those gradual junctions which are typically found in high-power thyristor structures to relatively steep diffused junctions similar to those that can occur in the emitter regions of UHF transistors.     

A theory of voltage breakdown of cylindrical P-N junctions, with applications

In certain p-n junctions, such as those made by the alloy method, edges on the junction surface will, by field concentration, lead to lower inverse breakdown voltages than would otherwise be obtained. These edges are approximated by pieces of circular cylinders, and a formula for the voltage breakdown of a circular cylindrical junction obtained. The results agree qualitatively with those found for certain alloy-type diodes.     

Transition region properties of reverse-biased diffused p-n junctions

Poisson's equation is solved for two common types of diffused p-n junctions in a manner similar to that of previous authors. By a suitable transformation, the field in the junction and capacitance-voltage relation for all junctions are shown to be presentable as a single family of curves with no approximation other than the assumption of negligible drift field. The abrupt and graded regions are discussed in detail. The zero-bias potential and capacitance are also discussed.     

Voltages and electric fields of diffused semiconductor junctions

Equations are developed and graphs are presented, showing a functional relationship between electric field and space-charge widening and also between reverse bias voltage and space-charge widening, for diffused diodes. Planar geometry, with the diffusion made from a constant surface concentration (C0) into material of constant impurity density, is assumed. The voltage vs space-charge width relation is presented graphically for the case of silicon. Graphs for other materials are not included, since they would differ from the silicon graphs only by a constant in the voltage axis. These graphs illustrate that for small reverse voltages the junction may be considered as being essentially linear, while for large reverse voltages it may be considered as an abrupt junction. A graph is provided which may be used to gain a qualitative indication of the electric field distribution within the space-charge region. This graph also gives an indication of the transition of junction behavior from nearly linear to nearly abrupt as the reverse voltage is increased.