Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applications

In the system-on-a-chip (SOC) era, chip layouts of integrated circuit (IC) products become more and more compact for cost reduction. To save layout area for SOC chips, on-chip electrostatic discharge (ESD) protection devices or input/output (I/O) transistors placed under bond pads is a good choice. To ensure that this choice is practicable, a test chip with large size NMOS devices placed under bond pads had been fabricated in a 0.35-/spl mu/m 1P4M 3.3-V CMOS process for verification. The bond pads of this test chip had been drawn with different layout patterns on the interlayer metals for two purposes. One is to investigate the efficiency against bonding stress applied on the active devices under the bond pads. The other purpose is to reduce the parasitic capacitance of bond pads for high-speed or high-frequency circuit applications. DC characteristics of these devices placed under bond pads had been measured under three conditions: before wire bonding, after wire bonding, and after thermal reliability stresses. After assembly with wire bond package and thermal reliability stresses, the measured results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied to save layout area of IC products by realizing on-chip ESD protection devices or I/O transistors under the bond pads, especially for the high-pin-count SOC.     

ESD protection under grounded-up bond pads in 0.13 μmeight-level copper metal, fluorinated silicate glass low-k intermetaldielectric CMOS process technology

Electrostatic discharge (ESD) protection device under the grounded-up bond pad is investigated in 0.13 μm full eight-level copper metal CMOS process technology with fluorinated silicate glass (FSG) low-k intermetal dielectric (IMD), The bonding force and power produces no cracking and no noticeable change in the second breakdown trigger point (V_t2) I_t2). High current I-V measured from the different level metal layer stack structures shows that 1) I_t2 depends very weakly on metal layers used, as expected due to certain junction power dissipation criterion and 2) V _t2 increases with the number of metal layers, The origin of the latter is increased dynamic impedance for increased metal layer number, as clarified by a simple RC model. The model also yields the intrinsic second breakdown trigger current and voltage for the underlying ESD protection device, Successfully configuring ESD protection circuits under the bond pads, therefore, not only is wholly free from the traditional area consumption, but also can substantially relax design constraints, enabling much more flexible and robust ESD schemes for various applications,     

Structural advantage for the EOT scaling and improved electron channel mobility by incorporating dysprosium oxide (Dy/sub 2/O/sub 3/) into HfO/sub 2/ n-MOSFETs

A structural approach of fabricating laminated Dy/sub 2/O/sub 3/-incorporated HfO/sub 2/ multimetal oxide dielectric has been developed for high-performance CMOS applications. Top Dy/sub 2/O/sub 3/ laminated HfO/sub 2/ bilayer structure shows the thinnest equivalent oxide thickness (EOT) with a reduced leakage current compared to HfO/sub 2/. This structure shows a great advantage for the EOT scaling CMOS technology. Excellent electrical performances of the Dy/sub 2/O/sub 3//HfO/sub 2/ multimetal stack oxide n-MOSFET such as lower V/sub T/, higher drive current, and an improved channel electron mobility are reported. Dy/sub 2/O/sub 3//HfO/sub 2/ sample also shows a better immunity for V/sub t/ instability and less severe charge trapping characteristics. Two different rationed Dy/sub 2/O/sub 3//HfO/sub 2/ and HfO/sub 2/ n-MOSFET were measured by charge-pumping technique to obtain the interface state density (D/sub it/), which indicates a reasonable and similar interface quality. Electron channel mobility is analyzed by decomposing into three regimes according to the effective field. Reduced phonon scattering is found to be the plausible mechanism for higher channel mobility.     

Scaling fully depleted SOI CMOS

Quasi-two-dimensional (2-D) device analyses, 2-D numerical device simulations, and circuit simulations of nanoscale conventional, single-gate fully depleted (FD) silicon-on-insulator (SOI) CMOS are done to examine the scalability and performance potential of the technology. The quasi-2-D analyses, which can apply to double-gate devices as well, also provide a simple expression to estimate the effective channel length (L/sub eff/) of FD/SOI MOSFETs. The insightful results show that threshold-voltage control via channel doping and polysilicon gates is not a viable option for extremely scaled FD/SOI CMOS, and hence that undoped channels and metal gate(s) with tuned work function(s) must be employed. Quantitative as well as qualitative insights gained on the short-channel effects reveal the need for ultrathin films (t/sub Si/ < 10 nm) for L/sub eff/ < 50 nm. However, the implied manufacturing burden, compounded by effects of carrier-energy quantization for ultrathin t/sub Si/, forces a pragmatic limit on t/sub Si/ of about 5 nm, which in turn limits the scalability to L/sub eff/ = 25-30 nm. Unloaded CMOS-inverter ring-oscillator simulations, done with our process/physics-based compact model (UFDG) in SPICE3, show very good performance for L/sub eff/ = 35 nm, and suggest viable technology designs for low-power as well as high-performance applications. These simulations also reveal that moderate variations in t/sub Si/ can be tolerated, and that the energy quantization significantly influences the scaled-technology performance and hence must be properly accounted for in optimal FD/SOI MOSFET design.     

0.18μm RF CMOS双向可控硅ESD防护器件的研究(英文)

基于传统双向可控硅(DDSCR)提出了两种静电放电(ESD)保护器件,可应对正、负ESD应力从而在2个方向上对电路进行保护。传统的DDSCR通过N-well与P-well之间的雪崩击穿来触发,而提出的新器件则通过嵌入的NMOS/PMOS来改变触发机制、降低触发电压。两种改进结构均在0.18μmRFCMOS下进行流片,并使用传输线脉冲测试系统进行测试。实验数据表明,这两种新器件具有低触发电压、低漏电流(～nA),抗ESD能力均超过人体模型2kV,同时具有较高的维持电压(均超过3.3V),可保证其可靠地用于1.8V、3.3V I/O端口而避免出现闩锁问题。     

应用于片上ESD防护中新式直通型MOS触发SCR器件的研究

在基于0.13μm CMOS工艺制程下,为研究片上集成电路ESD保护,对新式直通型MOS触发SCR器件和传统非直通型MOS触发SCR进行了流片验证,并对该结构各类特性进行了具体研究分析。实验采用TLP(传输线脉冲)对两类器件进行测试验证,发现新式直通型MOS触发SCR结构要比传统非直通型MOS触发SCR具有更低的触发电压、更小的导通电阻、更好的开启效率以及更高的失效电流。     

ESD implantations for on-chip ESD protection with layout consideration in 0.18-/spl mu/m salicided CMOS technology

One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra "ESD implantation" mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18-/spl mu/m salicided CMOS process is investigated by experimental testchips. The second breakdown current (I/sub t2/) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. A significant improvement in ESD robustness is observed when an nMOS device is fabricated with both boron and arsenic ESD implantations. The ESD robustness of the N-type diode under the reverse-biased stress condition can also be improved by the boron ESD implantation. The layout consideration in multifinger MOSFETs and diodes for better ESD robustness is also investigated.     

Reliability considerations for ESD protection under wire bonding pads

We have developed a configuration for diode-based electrostatic discharge structures that can be reliably placed under the metal stack of an integrated circuit wire bonding pad, thereby reducing the die area consumed for ESD. Prototype structures from both three- and four-level CMOS processes were assembled using gold ball and aluminum wedge bonding, respectively. Visual inspections after bonding found nothing that would compromise the integrity of the structure. Electrical tests found no failures from the ESD structure placement under the pad for over 8000 pads in the three-level metal and over 7000 pads for the four-level metal process. Structures under the pads pass full product-level qualification procedures.     

Fermi-level pinning at the polysilicon/metal oxide interface-Part I

We report here that Fermi pinning at the polysilicon/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. Oxygen vacancies at polysilicon/HfO/sub 2/ interfaces also lead to Fermi pinning. We show that this fundamental characteristic affects the observed polysilicon depletion. In Part I, the theoretical background is reviewed and the impact of the different gate stack regions are separated out by investigating the relative threshold voltage shifts of devices with Hf-based dielectrics. The effects of the interfacial bonding are examined in Part II.     

A simulation study to evaluate the feasibility of midgap workfunction metal gates in 25 nm bulk CMOS

The performance of 25 nm metallurgical channel length bulk MOSFETs with midgap workfunction metal gates has been compared with conventional polysilicon gates and bandedge workfunction metal gates. Device design using pocket halo implants was implemented to achieve the required off-state leakage specification. Highly accurate, full device simulations have been performed with a linear chain of inverters taking quantum effects into consideration. Drain induced barrier lowering (DIBL) was used as an indicator of short channel effects, and the stage delay of a linear chain of inverters and the on state drive current (I/sub on/) have been identified as metrics for performance. Compared to bandedge metal gates, midgap gates suffer from lower drive currents for both NMOS and PMOS devices. On the other hand, midgap devices were comparable in their performance to N/sup +/ polysilicon gated devices and exceeded that of P/sup +/ polysilicon devices. This high performance was attributed to a lack of poly depletion in midgap metal devices and a higher degree of DIBL which resulted in a lower V/sub t/ under high drain bias providing high drive current. Conclusions have been drawn on the feasibility of using midgap metal gates to simplify process integration in future generation CMOS devices.     

Characterization of CMOS Devices for VLSI

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND gates. Olpthnum performance (minimum figure of merit FM= f/sub pd/P/sub d/) is obtained for a CMOS/SOS two-input NAND gate (FO = 2, C/sub L/ = 22 fF) with an electrical channel length L = 0.75 /spl mu/m, channel width W= 5.0 /spl mu/m, and oxide thickness X/sub O/ = 450 /spl Aring/with V/sub DD/ = 3.0 V, to yield t/sub pd/ = 400 ps and P/sub d/ = 250 /spl mu/W (t/sub pd/P/sub d/ = 100 fJ) at room temperature. Bulk technology performs within a factor of 2 of SOS for t/sub pd/ and P/sub d/. CMOS technologies offer subnanosecond propagation delays, similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for t/sub pd/ describes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchal modeling approach to characterize mini-cells for VLSI.     

A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme

Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-V/sub th/ MOSFETs has a high operating speed, while a low-leakage power switch with a high-V/sub th/ MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-V/sub th/ and low-V/sub th/ MOSFETs (that is, multi-V/sub th/ CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V. In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word /spl times/ 8-bit SRAM chip, fabricated with the 0.35-/spl mu/m multi-V/sub th/ CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 /spl mu/W and that for 25-MHz operation is 1 mW, excluding that of the I/O buffers.     

Investigation on Robustness of CMOS Devices Against Cable Discharge Event (CDE) Under Different Layout Parameters in a Deep-Submicrometer CMOS Technology

Cable discharge events (CDEs) have been found to be the major root cause of inducing hardware damage on Ethernet ICs of communication interfaces in real applications. Still, there is no device-level evaluation method to investigate the robustness of complementary metal–oxide–semiconductor (CMOS) devices against a CDE for a layout optimization in silicon chips. The transmission-line pulsing (TLP) system was the most important method used to observe the electrical characteristics of semiconductor devices under human-body model (HBM) electrostatic discharge (ESD) stress. To understand the physical characteristics and CDE robustness of on-chip protection devices, the long-pulse transmission-line pulsing (LP-TLP) system is proposed in this paper and used to simulate the influence of CDE on Ethernet-integrated circuits. The secondary breakdown characteristics of the CDE protection devices under different layout styles and parameters can be measured and analyzed by the proposed LP-TLP with pulsewidths of 500 or 1000 ns. Furthermore, measured results using the LP-TLP system are compared with results measured by the traditional 100-ns TLP system. The experimental results with silicon devices in 0.18-$mu$ m CMOS process have shown that the CDE robustness of $n$ -channel metal–oxide–semiconductor (NMOS) and $p$ -channel metal–oxide–semiconductor (PMOS) devices in deep-submicrometer CMOS technology is much lower than their HBM ESD robustness. By using the proposed LP-TLP system, one set of design rules for I/O devices to sustain high CDE robustness in a given CMOS process can be evaluated and built up for chip layout.      

ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS IC's

This paper reports an ESD internal gate-oxide damage occurred on the digital-analog interface of a mixed-mode CMOS IC. A new ESD protection method is proposed to rescue this internal gate-oxide damage by adding ESD-protection devices on the long metal line between digital-analog interfaces. Experimental verification has confirmed that the IC product can be rescued to pass 2-KV ESD stress from the digital/analog VDD to digital/analog VSS pads without causing any internal damage again.     

Three-dimensional CMOS SOI integrated circuit usinghigh-temperature metal-induced lateral crystallization

A three-dimensional (3-D) CMOS integrated circuit was fabricated based on the conventional CMOS SOI technology. The first layer of transistors was formed on the SOI. The second layer of transistors was built on large-grain polysilicon-on-insulator (LPSOI). The recrystallized film was formed by the recrystallization of amorphous silicon using metal-induced lateral crystallization (MILC). The devices from the lower and upper layers were characterized and the result indicated that the SOI and LPSOI devices have similar electrical characteristics. The 3-D circuit design and layout considerations are introduced. The 3-D CMOS inverters were demonstrated with p-channel devices stacking over the n-channel ones. The ring-oscillator showed that the 3-D circuit has 30% reduction in the layout area and it operated at power supply as low as 0.5 V. The lower propagation delay and load capacitance suggest that 3-D circuit has higher performance than the conventional two-dimensional (2-D) circuit     

ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology

This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. Experimental results have verified that the human-body-model (HBM) ESD level of this new proposed I/O cells can be greater than 5 kV in a 130-nm fully salicided CMOS process. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of the I/O cell.     

Experimental method to thermally deembed pads from R/sub TH/ measurements

Both compound semiconductor and silicon-based bipolar junction transistors or heterojunction bipolar transistors (HBTs) require the efficient removal of heat in order to achieve a maximum level of performance and reliability. In order to satisfy both of these criteria, the electrothermal behavior of each device must be captured in a compact model. The model parameter that determines the junction temperature is R/sub TH/, the thermal resistance. Experimental methods to determine R/sub TH/ often require a relatively small device with a large R/sub TH/ to be attached to a set of relatively large metal pads with a low R/sub TH/. The pads act as a thermal shunt to the substrate and artificially lower the measured R/sub TH/. In order to obtain a suitable R/sub TH/ value for a device located in an IC, the pads must be deembedded from the measured data, much like pad deembedding for an S-parameter measurement. Test structures with various width metal traces between the emitter pad and device's emitter have been fabricated in a 200-GHz InP double HBT process. A method of using the measured R/sub TH/ of these structures and a simple resistive network model to deembed the pads is presented. It is shown that deembedded values can be as much as 30% higher than the measured R/sub TH/.     

ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers

Considering gate-oxide reliability, a new electrostatic discharge (ESD) protection scheme with an on-chip ESD bus (ESD_BUS) and a high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage N- and P-type MOS devices that can be safely operated under the 2.5-V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (positive-to-V_SS, negative-to-V_SS, positive-to-V_DD, and negative-to-V_DD) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13-mum CMOS process have confirmed that the proposed new ESD protection scheme has high human-body model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low- voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces.     

Characterization and modeling of AlGaN/GaN MOS capacitor with leakage for large signal transistor modeling

Dual mode AlGaN/GaN metal oxide semiconductor (MOS) heterostructure field-effect transistor (HFET) devices were fabricated and characterized. In HFET mode of operation the devices showed an f/sub t//spl middot/L/sub g/ product of 12GHz/spl middot//spl mu/m at Vgs=-2 V. The AlGaN devices showed formation of an accumulation layer under the gate in forward bias and a f/sub t//spl middot/L/sub g/ product of 6GHz/spl middot//spl mu/m was measured at Vgs=5 V. A novel piecewise small signal model for the gate capacitance of MOS HFET devices is presented and procedures to extract the capacitance in presence of gate leakage are outlined. The model accurately fits measured data from 45MHz to 10GHz over the entire bias range of operation of the device.     

Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.