Vertical current components in integrated injection logic

Analytic expressions representing a double diffused transistor impurity profile are used to calculate the current components in IIL structures. The expression for the hole current is given for IIL structures with the epitaxial layer grown on a wide n⁺substrate and for buried layer structures. It was found that an equivalent recombination velocity at the n-n⁺interface,S_{nn+}, is of order 10²higher in buried layer structures than in structures with the epitaxial layer grown on a wide n⁺substrate for comparable doping levels. Results obtained using the analytic expressions are compared with those obtained using a computer program which includes heavy doping effects and doping level mobility dependence. Both calculated and computed results are also compared with measured currents for a given IIL structure with the epitaxial layer grown on a wide n⁺substrate. The calculated and the computed results are in good agreement with the experimental results.     

Nonsaturated integrated injection logic

Conventional integrated-injection-logic structures suffer from strong saturation of the n?p?n transistors. This increases the storage time, and hence puts a limitation on the propagation delay of the structures. A current-control technique is given to reduce this effect without changing the basic i.i.l. structure.     

Folded-collector integrated injection logic

Folded-collector I/SUP 2/L offers an effective method of controlling the saturation of the n-p-n transistor simply by controlling the ratio of two areas: the area of the output collector(s) and the area of a `dummy' collector. This extra collector is folded back and connected to the input base. The structure improves the minimum delay of the basic I/SUP 2/L gate. Moreover, the structure has many circuit applications where a current scaling factor is required, e.g., threshold and ternary logic. Some of these circuits are given.     

Integrated injection logic for VLSI

This study shows that reducing the basewidth of I²L structures improves the intrinsic βuibut improvements in the extrinsic βueand the delay times at low-current levels are less significant while high-current performance is degraded. Narrowing the epi region improves both βuiand βueand the delay times at high currents, but degrades injection region efficiency λ, and delay times at low currents.     

New v-groove integrated injection logic

A new V-groove integrated injection logic (v.i.i.l.) is proposed which combines the V-groove technology and the double-diffused bipolar technology. The fabrication processes arc qualitatively described. The lateral p?n?p transistor of the i.i.l. is located on the vertical V-shape surface, and the effective base width is controlled by the combination of the vertical diffusion process and the V-groove etching rate. A 1-dimensional analysis is used and an approximate expression for the collector current of the lateral p?n?p transistor is given. The v.i.i.l. is expected to have a higher production yield than that of the ordinary i.i.l.     

Some considerations on high-speed injection logic

After a brief review of the factors that limit the switching speed of standard I/SUP 2/L, the propagation delay time of some special high-speed I/SUP 2/L gates is computed. For a gate realized in oxide-isolated, shallow epitaxial layers, the delay time is directly dependent on the injector base width. Generally, the n-p-n switching transistor hardly contributes to the time delay. For a modified I/SUP 2/L gate in which saturation of the injector is avoided, the delay time is mainly determined by the unity gain frequency of the switching transistor. However, due to the heavy saturation of this transistor, values of /spl tau//SUB d/ already realized indicate that the speed improvement is less than an order of magnitude.     

Device physics of integrated injection logic

After a brief review of relevant device parameters, characterizing the inversely operating multicollector n-p-n transistor and the lateral p-n-p transistor which make up anI^{2}Lbasic cell, some electronic circuit properties of this gate are discussed quantitively. Analytic expressions are derived for the transfer characteristics, the noise margin and the propagation delay time per gate in relation to the cell geometry, fan-out, doping profiles, and recombination properties. These expressions are compared with experimental and numerical circuit simulation results.     

The development of heterojunction integrated injection logic

The development of heterojunction integrated injection logic (HI ²L) since 1982 is described. The baseline process that uses AlGaAs/GaAs emitter-down HBTs (heterojunction bipolar transistors) as the switching element is presented. Two sets of design rules, one using a 7.0-μm collector and 8.0-μm metal pitch and another using a 5.0-μm collector and 5.0-μm metal pitch, have been developed for the pilot line circuit fabrication. Typical propagation delays obtained for a fan-out=4 HI²L gate using the 7.0- and 5.0-μm collector processes are 250 and 150 ps, respectively, at a power dissipation of 5 mW per gate. LSI and VLSI circuits as complex as 4 K-gate arrays and 32-bit MIPS microprocessors have been fabricated successfully using the HI²L technology     

Gamma radiation effects on integrated injection logic cells

Integrated injection-logic (I²L) cells were tested to determine their characteristics after exposure to a total dose gamma-radiation environment. These particular devices were not designed or fabricated with radiation hardness as a goal. The common-base current gain of the lateral p-n-p transistor, the common-emitter current gain of the vertical n-p-n transistor and the forward current-voltage characteristics of the injector-substrate junction were measured over the current range of 100 nA to 300 µA as a function of dose. In addition, the propagation delay time versus power dissipation per gate at various dose levels was determined from frequency of oscillation measurements of a multiple inverter circuit.     

Vertical handover-decision-making algorithm using fuzzy logic for the integrated Radio-and-OW system

Abstract-Due to the complementary nature of radio and optical wireless (OW) both in capacity and coverage, the combined use of both for data transmission could have advantages over a single media. However, big technical challenges for vertical-handover (VHO) strategy arise for such an integrated system. According to different interruption types and traffic modes, two basic VHO schemes can be applied: immediate VHO (I-VHO) and dwell VHO (D-VHO). This paper proposes a novel fuzzy-logic (FL)-based decision-making algorithm for VHO, which is capable of combining the merits of both schemes to achieve excellent handover in terms of packet transfer delay for all the cases considered here. The strength of FL in handling uncertain and conflicting decision metrics is exploited. Since excessive transfer delay results in disrupted connection and corrupted service, the proposed FL-based VHO decision-making algorithm has the potential to provide a better quality of service (QoS) to users in future wireless broadband communications.     

Isoplanar integrated injection logic: a high-performance bipolar technology

A newly developed technology is discussed. The emphasis of this approach is on achieving high packing density and high performance by use of various process innovations combined with topological design variations. Factors affecting packing density, DC as well as power delay product in I/SUP 2/L are analyzed and design considerations for the new structure are given. The results of computer simulations and measured device parameters and power delay are given. The following gate performance has been obtained at 100-/spl mu/A injector current, /spl beta/u/spl sime/2-4 for all four collectors, speed <10 ns for fan-out of four, speed <5 ns for a fan-out of one. At low currents a speed power product is 0.15 pJ. A packing density of more than 300 gates/mm/SUP 2/ including interconnect and power bussing has been achieved.     

Integrated injection logic: a new approach to LSI

Multicollector transistors fed by carrier injection are used. A simplified (five masks) standard bipolar process is used resulting in a packing density of 400 gates/mm/SUP 2/ with interconnection widths and spacings of 5 /spl mu/m. The power-delay time product is 0.4 pJ per gate. An additional advantage is a very low supply voltage (less than 1 V). This, combined with the possibility of choosing the current level within several decades enables use in very low-power applications. With a normal seven-mask technology, analog circuitry has been combined with integrated injection logic (I/SUP 2/L).     

Gate delays of InGaAs/InP heterojunction integrated injection logic

The delay time of an InGaAs/InP heterojunction bipolar transistor integrated injection logic gate is calculated as a function of the npn transistor upward current gain and for fan-outs of one and four. It is shown that intrinsic gate delays under 300 psec are possible with a fan-out of 4 for a gate designed with 3 µm design rules and having 0.5 µm npn and pnp base widths. Gate delays well under 100 psec are predicted for less conservative designs.     

Current hogging injection logic-a new logic with high functional density

A new design concept for bipolar integrated circuits with high functional density will be presented. The basic current hogging injection logic (CHIL) gate consists of a lateral intermediate collector structure, where the last collector simultaneously forms the base region of an inversely operated vertical output transistor. Thus a CHIL gate can be looked at as a CHL gate with a functionally integrated output transistor, or as an integrated injection logic (I/SUP 2/L) inverter with controlled injection. Dc and pulse measurements are discussed and calculated results with a simple model suitable for computer-aided design (CAD) are presented. The static noise immunity of CHIL circuits is compared to CHL and I/SUP 2/L. CHIL circuits are well suitable for large-scale integration (LSI) and are technologically compatible to all circuits fabricated in a standard buried collector (SBC) process.     

Integrated injection logic for a linear/digital LSI environment

The dc and transient performance of Integrated Injection Logic (I²L) structures in a linear/digital LSI environment is analyzed and modeled. The analysis is based on a functional modeling approach and uses a one-dimensional regional computer device analysis program which includes heavy doping effects and doping level mobility dependence. The computed results are used to evaluate the performance of I²L structures in five bioplar technologies. Means of decreasing the effective epitaxial layer thickness and decreasing the effective epi-resistivities of the I²L part of the chip, without affecting the breakdown voltage of the linear part, are given and evaluated. The computed results are compared to experiments.     

A 30-ps Josephson current injection logic (CIL)

A family of novel Josephson logic circuits called current injection logic (CIL) is presented. In contrast to previous approaches, it combines magnetically coupled interferometers with novel nonlinear injection gates to obtain ultra-fast logic speeds, wide margins, and greater fan-in and fan-out capabilities. Fastest logic delay of 30 ps/gate is measured averaged over two- and four-input OR and AND gates (average fan-in=4.5, average fan-out=2.5) fabricated using 2.5 /spl mu/m nominal design rules. The average power dissipation of these experimental circuits is 6 /spl mu/W/gate. An unprecedented logic delay of 13 ps/stage is measured on a chain of two-input OR gates, and the logic delay for a circuit consisting of two two-input OR gates, the outputs of which are `AND'ed, is measured at 26 ps. The experimental results are found to be in excellent agreement with delay estimates based upon computer simulations.     

基于模糊逻辑的多终端协同的垂直切换决策算法

针对异构网下多终端协同的垂直切换决策问题,提出一种基于模糊逻辑和层次分析法的垂直切换决策算法,它分为2部分:切换时机的判断和虚拟终端的构建.首先采用模糊逻辑判断切换的时机,然后采用层次分析算法与简单加权求和结合的方法选择虚拟终端的最优构成方式.仿真结果表明,算法能够降低切换次数和不必要切换率,并且能够充分体现应用需求和用户偏好.     

A vertical injection logic watch IC with CMOS equivalent current drain

Vertical injection logic (VIL), an improved structure of I/SUP 2/L, was applied to an analog watch IC with a 1.5-V supply voltage, which resulted in a CMOS equivalent current drain of 2 /spl mu/A and half the chip size of CMOS. The design consideration and experimental work that support the characteristics are described.     

Fabrication of integrated injection logic with electron-beam lithography and ion implantation

Integrated injection logic gates have been fabricated using electron-beam lithography and ion implantation. A factor of five reduction in gate area over conventional designs was achieved by using minimum linewidths of 1.25 µm. Average propagation delay of 6 ns at 100 µA/gate injector current and speed-power product of 0.13 pJ at 5 µA have been measured on five collector, stick geometry, n⁺guard ring device structures. The delay time is a factor of three and the speed-power product is a factor of five better than typical conventionally sized structures fabricated with photolithography. A minimum delay of 3.6 ns has been achieved on five collector device structures designed for maximum speed.