Step-repeat pattern generation technique

A simple technique of generating step - repeat patterns of wide area fine geometry devices, e.g. S.A. W. Colour TVI.F. filter on the wafer by using the single pattern photomask is described. The various advantages of the technique are also pointed out.     

Precise delay generation using the Vernier technique

The authors show a new technique for generating precise clock delays. The Vernier technique exploits the difference between two coarse delays to achieve delay resolutions much smaller than an intrinsic gate delay. This resolution limit is usually smaller than a conventional gate delay, the limit for most conventional delay generation methods. The Vernier technique has the additional advantage of being easy to implement. Simulations show that this technique is capable of resolutions as small as 50 ps using 2.0 μm CMOS     

Function-based compact test pattern generation for path delay faults

We present a function-based nonenumerative automatic test pattern generation (ATPG) methodology for detecting path delay faults (PDFs). The proposed technique consists of a number of topological circuit traversals during each a linear number of Boolean functions is generated per circuit line. From each such function we derive a test that detects many PDFs. The two major strengths of the approach, that stem from the function-based formulations used, are very compact test sets, and scalability in test efficiency. The performance of an implementation based on binary decision diagrams is evaluated and compared with existing compact methods to demonstrate the superiority of the proposed method.     

Precise delay generation using coupled oscillators

A new delay generator based on a series of coupled ring oscillators has been developed; it produces precise delays with subgate delay resolution for chip testing applications. It achieves a delay resolution equal to a buffer delay divided by the number of rings. The coupling employed forces the outputs of a linear array of ring oscillators oscillating at the same frequency to be uniformly offset in phase by a precise fraction of a buffer delay. The buffer stage used in the ring oscillators is based on a source-coupled pair and achieves high supply noise rejection while operating at low supply voltages. Experimental results from a 2-μm N-well CMOS implementation of the delay generator demonstrate that it can achieve an output delay resolution of 101 ps while operating at 141 MHz with a peak error of 58 ps     

基于DDS的数字延迟信号产生方法研究

提出了基于DDS的数字延迟信号产生方法。分析了宽带线性调频信号通过时延后实现天线方向图在不同频率上的稳定指向,并在此基础上根据DDS信号产生的原理设计了适用于DDS核的非线性迭代算法。通过仿真试验验证了该方法的有效性。     

4G中的MIMO-OFDM技术

第四代移动通信提供高的数据传输速率,而MIMO和OFDM提高了频谱效率,从而提供高传输速率和系统容量的技术.两者的结合已经成为第四代移动通信技术研究中的热点.通过这两种技术的优势互补,可以为系统提供高传输速率,同时也能提高系统容量,降低成本.文中详细介绍了这两种技术及信道估计.     

BIST test pattern generator for delay testing

To detect delay faults in a digital circuit requires a test sequence applied at the nominal frequency of the circuit. Built-in self-test (BIST) is a technique that provides such testing possibilities at speed, without expensive test equipments. A BIST test pattern generator (TPG) design, targeting the detection of delay faults is proposed     

A simple method for sub-100 nm pattern generation with I-line double-patterning technique

We have developed a simple method adopting double-patterning technique to extend the I-line stepper limit for the sub-100 nm poly-Si pattern generation in this work. Through in-line and cross-sectional scanned electron microscopic analyses of the generated patterns, we confirmed the feasibility of the double-patterning technique for the fabrication of nano-scale devices. Resolution capability of this technique has been confirmed to be at least 100 nm, which is much superior to the resolution limit of conventional I-line lithography. This approach has also been applied for fabricating p-channel metal-oxide-semiconductor field-effect transistors. Excellent device characteristics were verified.     

High-speed pulse-train generation using single-mode-fibre recirculating delay lines

A simple technique is described, whereby the delay properties of a series of two single-mode-fibre recirculating delay lines were used to generate a sequence of uniform, high-speed pulse trains. A single, short input was used to generate a sequence of 1.25 Gbit/s pulse trains that were uniform to better than ±0.3 dB.     

Functional delay test generation based on software prototype

The paper presents two methods of functional delay test development based on the software prototype as well as the results of their application to benchmark circuits. The first method is used to construct the functional delay test on the base of a pin pair test generated at the functional level for detection of stuck-at faults at the gate-level. The constructed test is a single input transition test. The latter appears to be quite large. Therefore, we provide the method for compacting it. The compacted single input transition test becomes a multi-input transition test. The second method is used to generate a multi-input transition test. The generated functional test pattern pairs possess function-robust and/or function-non-robust properties. The introduction of the function-non-robust property enriches the functional delay test. The presented test construction approach based on the software prototype allows obtaining a functional delay test, which detects the transition faults at the gate-level of a circuit quite completely.     

Efficient test generation algorithm for path delay faults

A new algorithm has been developed to perform efficient delay testing. The algorithm enables applications of a new implication of value using indirect implication. The results of ISCAS benchmark circuits show the effectiveness of the new algorithm     

The statistical distribution of switch-on delay in single-modesemiconductor lasers II: pattern effects

For part I see, p. 2006, 1995. The theory of stochastic processes as applied to photon emission and absorption events is used to calculate the distribution of switch-on delay in directly modulated semiconductor lasers down to a probability of 10^-10. In this second paper, the influence of a previous light pulse on the delay of a given pulse is investigated. The probability distribution of photon number in the dying remnants of the first pulse is examined under the relevant transient conditions of gain and loss, and is found to evolve in relative width and shape in a way which depends on only one parameter. This parameter, which consists of an integral over time of the reciprocal of the average photon number, is obtained from a solution of the deterministic rate equations and is used to deduce the delay distribution of the subsequent pulse. The results, although sensitively dependent on the conditions, are supported by experiment     

Photonic generation of ultrawideband signals using a delay interferometer

We demonstrate a novel scheme to generate ultrawideband (UWB) monocycle and doublet pulses byinputting a dark return-to-zero (RZ) signal into a delay interferometer (DI), which accords with the general features in future applied UWB system, namely, single optical source input, simple configuration and passive device. The two polarized interferential beams have a time delay and a phase difference when they propagate through the DI. By adjusting polarization controllers (PCs), the total phase difference, i.e., the sum of the relative opticalphase difference between two orthogonally polarized components caused by PCs and the optical-phase shift due to birefringence of the polarization-maintaining fiber (PMF), the orientation angle of the polarization beamsplitter (PBS) relative to the two axes of the PMF are able to be changed and controlled. When the appropriate conditions are met, UWB monocycle and doublet pulses are generated conveniently.     

Laser scanning for semiconductor mask pattern generation

The use of laser scanning to generate semiconductor masks is reviewed. Following a brief historical introduction that describes early pattern generator implementations, current and future industry mask requirements are described with the consequences for pattern generator design: the need for small features, tight CD control, and high pixel delivery rates. The system architecture of a current deep UV scanning system is described in detail along with important print strategies, such as grayscale printing and multipass error averaging. Several subsystem technologies are then explored with emphasis on the application to short wavelengths and multiple beams. Today, frequency-doubled lasers generate the 257-nm radiation used by DUV pattern generators; tomorrow, sum frequency generation will be required to reach the wavelengths at or below 200 nm. Acousto-optic modulation (AOM) technology is shown to scale favorably with shorter wavelengths and to have the bandwidth capability for future system. Acousto-optic beam deflection, polygonal mirror beam deflection, and the reduction of scan bow error through the use of an f /spl middot/ sin(/spl theta/) lens are examined. A section on scan optics and image formation presents the differences between partially coherent imaging as used by a wafer stepper and the incoherent superposition of Gaussian beams as used by a laser scanner. Partially coherent imaging is shown to have a sharper image slope but worse feature size linearity. This section also discusses the effect of finite AOM turn-on time on the aerial image in the scan direction.     

RMS delay spread estimation technique using non-coherent channelmeasurements

A method is presented for deriving the RMS delay spread from non-coherent wideband channel measurements (measured amplitude transfer functions). A frequency-domain model of the frequency-selective, Rician fading channel is used, allowing a theoretical evaluation of the transfer function's level crossing statistics     

Frequency-multiple generation technique using Chebyshev polynomials

A frequency-multiple generation technique based on Cheby?shev polynomials is presented in this letter. The circuit contains a minimum number of multipliers and operational-amplifier summers.     

Efficient generation technique for polynomial codesets

The letter introduces a new technique for the generation of a set of polynomial codewords. Each word is generated with a single modulo-2 addition, rather than by using the conventional polynomial multiplication technique. The method is simple to apply and can form the basis for set generation by a minicomputer or microprocessor.     

The use of a quantitative differential mode delay technique to improve fiber bandwidth

Three iterations of a simple quantitative differential mode delay (DMD) technique increased the bandwidth of multimode graded-index fibers at 1300 nm from an average of 530 MHz, km to an average of 1417 MHz . km. The bandwidth at other wavelengths showed a commensurate increase.     

Efficient third-harmonic generation of a picosecond laser pulsewith time delay

A new configuration based on the polarization-mismatching scheme with time delay for efficient frequency tripling conversion is proposed in this paper. The calculated results showed that the requirement for the efficient frequency tripling conversion of a 1-ps laser pulse is not only the optimization of peak intensity of the second-harmonic pulse, but also the optimization of the pulse duration ratio and temporal difference between the o-polarization second-harmonic pulse and the e-polarization first-harmonic pulse due to group-velocity mismatch among the interacting pulses. With the proposed scheme the group velocity mismatch can be compensated. Overall energy conversion efficiency increases from 55% to 75% under the optimized conditions at the intensity of 6 GW/cm². The temporal shape of the third-harmonic pulse with 1 ps pulse duration has no subpulses. The optimization of the efficient frequency tripling conversion for intensities of over 75 GW/cm² is also described. The results showed that the maximum tripling energy conversion efficiency is close to 80% with the optimized doubler and tripler     

低功耗测试矢量生成技术的研究

在集成电路内建自测试的过程中,电路的测试功耗通常显著高于正常模式产生的功耗,因此低功耗内建自测试技术已成为当前的一个研究热点。为了减少被测电路内部节点的开关翻转活动率,研究了一种随机单输入跳变（Random Single Input Change,RSIC）测试向量生成器的设计方案,利用VHDL语言描述了内建自测试结构中的测试向量生成模块,进行了计算机模拟仿真并用FPGA（EP1C6Q240C8）加以硬件实现。实验结果证实了这种内建自测试原理电路的正确性和有效性。