A CMOS high-speed data recovery circuit using the matched delaysampling technique

This paper presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique. By simultaneously propagating data and clock signals through two different delay taps, the sampler achieves a very fine sampling resolution which is determined by the difference between the data and clock delays. This high resolution sampling capability of the matched delay sampler can be used in the oversampling data recovery circuit. A data recovery circuit using the matched delay sampling technique has been designed and fabricated in 1.2-μm CMOS technology. The chip has been tested at 417 Mb/s [2.4 ns nonreturn to zero (NRZ)] input data and demultiplexes serial input data into four 104 Mb/s (9.6 ns NRZ) output streams with 800 mW power consumption at 4 V power supply. While recovering data, the sampling clock running at 1/4 of the data frequency is phase-tracking with the input data based on information extracted from a digital phase control circuit     

An integrated high resolution CMOS timing generator based on anarray of delay locked loops

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for time-to-digital converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with subgate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing generator has been mapped into a 1.0 μm CMOS process and an r.m.s. error of the time taps of 48 ps has been measured with a bin size of 0.15 ns. Used as a TDC device, an r.m.s. error of 76 ps has been obtained, A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives     

A sampling technique and its CMOS implementation with 1 Gb/sbandwidth and 25 ps resolution

This paper presents a technique and circuitry for high-resolution sampling of a digital waveform. Very fine sampling resolution is achieved by simultaneously propagating both data and clock signals through delay elements in such a way that resolution is controlled by the difference in the delay of clock and data signals. Delay units were designed using biased CMOS and differential CMOS inverters. A sampler circuit with 64 stages has been fabricated in 1.2 μm CMOS technology, and test results show a bandwidth of up to 1 Gb/s for the input data and a sampling resolution externally adjustable between 25 and 250 ps. The fabricated circuit has shown sampling stability, monotonicity in sampling, and uniformity in sampling resolution     

基于FPGA的平板显示器件驱动电路的设计

介绍了一种基于FPGA的平板显示器件驱动电路的设计方法。在FPGA内部设计了数字GAMMA校正、时基校正、时钟发生器、锁相环、I2C控制等模块,替代了各个专用集成芯片的功能,用数字技术取代传统模拟技术实现电路各模块,简化了电路;能够完成平板显示器件显示时序及控制方面的要求且控制灵活;能驱动大部分的平板显示器件,通用性好;设计了丰富的扩展信号接口,FPGA外挂SDRAM可应用于更大规模的平板显示驱动,可移植性强。采用高分辨率液晶投影显示屏LCX029CPT来验证所设计的驱动电路,通过电路实现,显示出质量很好的图像。     

A low-power direct digital synthesizer using a self-adjustingphase-interpolation technique

A complete direct digital synthesizer (DDS) using a self-adjusting phase-interpolation technique is fabricated using 0.35-μm CMOS process technology. A self-adjusting delay generator reduces the periodic jitter in the most significant bit (MSB) of the accumulator in this DDS. To improve the spectral performance, a method of spurious signal reduction that uses offset current sources (OCSs) is newly adopted in the delay generator. Test results confirm that the delay generator produces highly accurate delay timing without the need to adjust circuit constants. The measured spurious free dynamic range (SFDR) is 62 dBc for a dc to 10-MHz output and the power consumption of the complete DDS is 39.2 mW at a 100-MHz clock rate     

Efficient logic-level timing analysis using constraint-guidedcritical path search

As the operating speed of digital circuits dramatically increases with the advance of VLSI technology, it is becoming more critical to ensure that the circuits are free from timing-related design errors. In a traditional static timing approach nonfunctional paths cannot be distinguished from functional ones since the functionality of a circuit is ignored. This often results in overestimation of circuit delay and can degrade the circuit performance. In today's design methodology where the use of automated logic synthesis and module-based design are popular, circuits with a very large number of nonfunctional (false) paths are common. This paper describes an efficient logic-level timing analysis approach that can provide an accurate delay estimate of a digital circuit which may have many long false paths. By using logic incompatibilities in a circuit as constraints for critical path search, the algorithm determines the longest sensitizable path without explicit path enumeration. Since the number of false paths that can be implicitly eliminated is potentially exponential to the number of path constraints, performance improvement is significant     

A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM

An ultrahigh-speed 4.5-Mb CMOS SRAM with 1.8-ns clock-access time, 1.8-ns cycle time, and 9.84-μm² memory cells has been developed using 0.25-μm CMOS technology. Three key circuit techniques for achieving this high speed are a decoder using source-coupled-logic (SCL) circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array. The proposed decoder can reduce the delay time between the address input and the word-line signal of the 4.5-Mb SRAM to 68% of that of an SRAM with conventional circuits. The sense amplifier with nMOS source followers can reduce not only the delay time of the sense amplifier but also the power dissipation. In the SRAM, the sense-amplifier activation pulse must be input into the sense amplifier after the signal from the memory cell is input into the sense amplifier. A large timing margin required between these signals results in a large access time in the conventional SRAM. The sense-amplifier activation pulse generator that uses a duplicate memory-cell array can reduce the required timing margin to less than half of the conventional margin. These three techniques are especially useful for realizing ultrahigh-speed SRAM's, which will be used as on-chip or off-chip cache memories in processor systems     

Certified timing verification and the transition delay of a logiccircuit

Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multivector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification     

基于反馈调节的闪烁脉冲稀疏量化电平方法

PET探测器采用SQL采样电路对闪烁脉冲进行处理,可固定量化电平。零点噪声引起的电平翻转导致电压比较器长时间非正常发热,无法设置较低的量化电平,限制了探测器符合时间分辨率的提高。文中提出一种基于反馈调节的闪烁脉冲处理方法,该方法通过使用三极管饱和状态下的开关特性,对SQL量化样本进行反馈调节。利用延迟元件对量化样本进行延迟同步,产生可以随样本逻辑电平变化的量化电平,避免了零点噪声对SQL采样电路的影响。实验结果表明,在相等时间内,优化的SQL采样电路的采样量比原SQL采样电路的采样量减少了29%,符合时间分辨率提升了179.3 ps,有效减少了PET探测器无用功耗,提高了PET系统的符合时间分辨率。     

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results

Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. In this paper we first discuss the general framework of the test generation algorithm followed by computational results. Comparison of results with SPICE simulations confirms the accuracy of this approach.     

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique

Coupling effect due to line-to-line capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual V/sub t/ technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low V/sub t/ is applied properly.     

Analysis of the switching speed of BiCMOS buffer under high current

A nonlinear analytical transient response model that is suitable for BiCMOS driver circuits operating under the Kirk and Van der Ziel effect is presented. The model accounts for both base vertical push-out and lateral stretching phenomena where the forward transit time τ _f has a square law dependence on the collector current. Based on the new transient model, a closed-form BiCMOS delay expression is derived that shows excellent agreement with measured gate delay from a 0.8-μm BiCMOS technology. The comparison is made for a wide range of circuit parameters. The delay model can be used to develop timing analyzers, timing simulators, and circuit optimization tools for ULSI circuit design. As an application of the delay model, a circuit design algorithm is derived to optimize the speed-area performance of the BiCMOS buffers     

A portable digitally controlled oscillator using novel varactors

This work presents a portable digitally controlled oscillator (DCO) by using two-input NOR gates as a digitally controlled varactor (DCV) in fine-tuning delay cell design. This novel varactor uses the gate capacitance difference of NOR gates under different digital control inputs to establish a DCV. Thus proposed DCO can improve delay resolution 256 times better than a single buffer design. This study also examines different types of NOR/NAND gates (2-input or 3-input) for DCV. The proposed DCO with novel DCV can be implemented with standard cells, and thus it can be ported to different processes in short time. Furthermore, the final circuit layout can be generated using an auto placement and routing (APR) tools. A test chip demonstrates that LSB resolution of the DCO can be improved to 1.55 ps with standard 0.35-/spl mu/m 2P4M CMOS digital cell library. The proposed DCO has good performance in terms of fine resolution, high portability, and short design turnaround cycle compared with conventional DCO designs.     

Physical timing modeling for bipolar VLSI

An approach for the analytical timing modeling of bipolar VLSI circuits that is based on average branch current analysis and the parametric correction scheme is presented. The combination of these techniques permits complex delay-sensitive effects of bipolar digital circuits to be incorporated in the derivation of the bipolar delay models. The delay functions of two basic bipolar subcircuit configurations (the series-gated structure and the emitter follower) are derived using the proposed techniques. It is shown that accurate timing information for the high-speed bipolar digital circuit, such as ECL, CML, and BiCMOS, can be obtained by repeated processing of these subcircuit delay functions. The delay estimates obtained with these timing models have been shown to be accurate typically within 10% of SPICE estimates. Applications include switch-level timing simulation, timing analysis and verification cell optimization, and technology mapping     

单光子探测InGaAs雪崩焦平面像素级高分辨率低误码时间数字转换电路

单光子探测在量子信息、生物医学、激光雷达成像等领域具有重要应用前景,InGaAs盖革雪崩焦平面具有单光子探测灵敏度,通过计量光子飞行时间实现距离探测,时间数字转换精度决定整个探测系统的测距精度,是近年来单光子探测领域的研究热点。设计了一款64×64面阵型像素级高分辨低误码时间数字转换阵列电路（Time to Digital Converter, TDC）,采用局部共享型高中低三段式异步周期TDC结构。低段位TDC全阵列共享,基于压控延迟链（Voltage Control Delay Line, VCDL）分相时钟实现亚纳秒计时;中高段位每个像素独享,中段位采用分频计数器降低时钟频率,降低阵列整体功耗,高段位采用线性反馈移位寄存器实扩展计时量程并实现计时、数据存储、输出一体化。采用延迟采样方案显著降低了因段间计数时钟不匹配导致的数据锁存误码问题。采用0.18 μm CMOS工艺流片,实测250 MHz参考时钟频率下分辨率0.5 ns,积分非线性?0.4~0.6 LSB,微分非线性?0.4~0.4 LSB,TDC转换单调,有效量程位数13位,20 kHz帧频功耗380.5 mW。     

Phase interpolation direct digital synthesiser with precise delaygenerator using two-step integration

A new delay generator using two-step integration is proposed for direct digital synthesis. The new delay generator can provide precise delay timing since delay timing is unaffected by the propagation delay dispersion of the voltage comparator. Experimental results show that the frequency synthesiser operated successfully     

支持像移补偿功能面阵CCD相机驱动电路系统

为了设计一种支持电子式像移补偿功能的高帧频大面阵CCD驱动电路,满足像移补偿功能.论文首先给出了大面阵CCDFTF5066M的基本驱动电路,然后在其基础上通过增加一个像移补偿时序发生器与主时序发生器SAA8103配合工作来实现电子像移补偿,给出了像移补偿发生器内部设计结构,所增加的像移补偿时序发生器只用于产生曝光期间所需的几个垂直转移驱动时序和转发SAA8103 产生的时序信号.选择了FPGA作为像移补偿时序发生器,并且进行了时序仿真.最后对设计的驱动电路进行了室内像移补偿实验验证,取得了很好的补偿效果,该驱动电路系统支持最大帧频可达2.7 F/s,信噪比达到了66 dB.该驱动电路能方便地选择输出通道数量和输出方式,使相机适用于不同的场合.     

Hybrid DPWM implementation using coarse and fine programmable ADLL

In the paper we propose a novel architecture and implementation of 11-bit Digital Pulse Width Modulator (DPWM) circuit based on previously known building blocks. Linearized Class-AD Double-sided (LADD) algorithm has been used to calculate the DPWM signals of the 11-bit resolution hybrid DPWM for a Class-AD digital audio amplifier. Noise-shaping process is used to support high fidelity with practical values of time resolution. The proposed DPWM circuit is composed of 8-bit counter and Analog Delay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fine programmable delay element is used to adjust the delay time of delay line and lock it to required time. The coarse- as well as fine-delay lines are implemented as a cascade of variable-delay elements based on shunt capacitor delay element or single-ended Schmitt trigger. The proposed 11-bit DPWM circuit, at a switching frequency of 352.8 kHz and clock generator frequency of 90.3 MHz allows us to attain SNR of 120 dB and THD of the output signal less than 0.1% within the audio baseband and modulation index M=0.95. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) for real CMOS process are presented.     

High-speed demonstration of single-flux-quantum cross-bar switch up to 50 GHz

We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.     

Design of reversible parity generator and checker for the implementation of nano-communication systems in quantum-dot cellular automata

Complementary metal-oxide semiconductor (CMOS) technology may face so much problems in future due to the smaller size of transistors and increase in circuits’ volume and chips temperature. A new technology that can be a good alternative to CMOS circuits is quantum-dot cellular automata (QCA). These technologies have features such as a very low power consumption, high speed and small dimensions. In nano-communication system, error detection and correction in a receiver message are major factors. In addition, circuit reversibility in QCA helps designs a lot. In this research, generator and checker circuit of the reversible parity and eventually their nano-communication system are designed reversible using odd parity bit. The proposed circuits and the theoretical values are tested by QCADesigner 2.0.3 simulator to show the correct operation of the circuits. According to the simulation results, the proposed circuits compared with the previous structure improve delay by 90–75–35% in generator and checker structures of parity and their reversibility of nano-communication system, respectively. The proposed circuits are used in nano-transmitters and nano-receivers.