The Dynamic Phase Transition Modulation of Ion‐Liquid Gating VO2 Thin Film: Formation,Diffusion, and Recovery of Oxygen Vacancies

Electrolyte gating with ionic liquids (IL) on correlated vanadium dioxide (VO₂) nanowires/beams is effective to modulate the metal‐insulator transition (MIT) behavior. While for macrosize VO₂ film, the gating treatment shows different phase modulation process and the intrinsic mechanism is still not clear, though the oxygen‐vacancy diffusion channel is always adopted for the explanation. Herein, the dynamic phase modulation of electrolyte gated VO₂ films is investigated and the oxygen vacancies formation, diffusion, and recovery at the IL/oxide interface are observed. As a relatively slow electrochemical reaction, the gating effect gradually permeates from surface to the inside of VO₂ film, along with an unsynchronized changes of integral electric, optical, and structure properties. First‐principles‐based theoretical calculation reveals that the oxygen vacancies can not only cause the structural deformations in monoclinic VO_2, but also account for the MIT transition by inducing polarization charges and thereby adjusting the d‐orbital occupancy. The findings not only clarify the oxygen vacancies statement of electrolyte gated VO₂ film, but also can be extended to other ionic liquid/oxide systems for better understanding of the surface electrochemical stability and electronic properties modulation.     

Low‐Operating‐Voltage Organic Transistors Made of Bifunctional Self‐Assembled Monolayers

Self‐assembled monolayers (SAMs) are molecular assemblies that spontaneously form on an appropriate substrate dipped into a solution of an active surfactant in an organic solvent. Organic field‐effect transistors are described, built on an SAM made of bifunctional molecules comprising a short alkyl chain linked to an oligothiophene moiety that acts as the active semiconductor. The SAM is deposited on a thin oxide layer (alumina or silica) that serves as a gate insulator. Platinum–titanium source and drain electrodes (either top‐ or bottom‐contact configuration) are patterned by using electron‐beam (e‐beam) lithography, with a channel length ranging between 20 and 1000 nm. In most cases, ill‐defined current–voltage (I–V) curves are recorded, attributed to a poor electrical contact between platinum and the oligothiophene moiety. However, a few devices offer well‐defined curves with a clear saturation, thus allowing an estimation of the mobility: 0.0035 cm² V^–1 s^–1 for quaterthiophene and 8 × 10^–4 cm² V^–1 s^–1 for terthiophene. In the first case, the on–off ratio reaches 1800 at a gate voltage of –2 V. Interestingly, the device operates at room temperature and very low bias, which may open the way to applications where low consumption is required.     

Reversible Ferromagnetic Phase Transition in Electrode‐Gated Manganites

The electronic phase transition has been considered as a dominant factor in the phenomena of colossal magnetoresistance, metal‐insulator transition, and exchange bias in correlated electron systems. However, the effective manipulation of the electronic phase transition has remained a challenging issue. Here, the reversible control of ferromagnetic phase transition in manganite films through ionic liquid gating is reported. Under different gate voltages, the formation and annihilation of an insulating and magnetically hard phase in the magnetically soft matrix, which randomly nucleates and grows across the film instead of initiating at the surface and spreading to the bottom, is directly observed. This discovery provides a conceptually novel vision for the electric‐field tuning of phase transition in correlated oxides. In addition to its fundamental significance, the realization of a reversible metal‐insulator transition in colossal magnetoresistance materials will also further the development of four‐state memories, which can be manipulated by a combination of electrode gating and the application of a magnetic field.     

High‐Performance,Air‐Stable,Top‐Gate,p‐Channel WSe2 Field‐Effect Transistor with Fluoropolymer Buffer Layer

High‐performance, air‐stable, p‐channel WSe₂ top‐gate field‐effect transistors (FETs) using a bilayer gate dielectric composed of high‐ and low‐k dielectrics are reported. Using only a high‐k Al₂O₃ as the top‐gate dielectric generally degrades the electrical properties of p‐channel WSe₂, therefore, a thin fluoropolymer (Cytop) as a buffer layer to protect the 2D channel from high‐k oxide forming is deposited. As a result, a top‐gate‐patterned 2D WSe₂ FET is realized. The top‐gate p‐channel WSe₂ FET demonstrates a high hole mobility of 100 cm²_­ V^?1 s^?1 and a I_ON/I_OFF ratio > 10⁷ at low gate voltages (V_GS ca. ?4 V) and a drain voltage (V_DS) of ?1 V on a glass substrate. Furthermore, the top‐gate FET shows a very good stability in ambient air with a relative humidity of 45% for 7 days after device fabrication. Our approach of creating a high‐k oxide/low‐k organic bilayer dielectric is advantageous over single‐layer high‐k dielectrics for top‐gate p‐channel WSe₂ FETs, which will lead the way toward future electronic nanodevices and their integration.     

High‐Sensitivity Floating‐Gate Phototransistors Based on WS2 and MoS2

In recent years, 2D layered materials have been considered as promising photon absorption channel media for next‐generation phototransistors due to their atomic thickness, easily tailored single‐crystal van der Waals heterostructures, ultrafast optoelectronic characteristics, and broadband photon absorption. However, the photosensitivity obtained from such devices, even under a large bias voltage, is still unsatisfactory until now. In this paper, high‐sensitivity phototransistors based on WS₂ and MoS₂ are proposed, designed, and fabricated with gold nanoparticles (AuNPs) embedded in the gate dielectric. These AuNPs, located between the tunneling and blocking dielectric, are found to enable efficient electron trapping in order to strongly suppress dark current. Ultralow dark current (10^?11 A), high photoresponsivity (1090 A W^?1), and high detectivity (3.5 × 10¹¹ Jones) are obtained for the WS₂ devices under a low source/drain and a zero gate voltage at a wavelength of 520 nm. These results demonstrate that the floating‐gate memory structure is an effective configuration to achieve high‐performance 2D electronic/optoelectronic devices.     

Charge Disproportionation and Voltage‐Induced Metal–Insulator Transitions Evidenced in β‐PbxV2O5 Nanowires

The roster of materials exhibiting metal–insulator transitions with sharply discontinuous switching of electrical conductivity close to room temperature remains rather sparse, despite the fundamental interest in the electronic instabilities manifested in such materials and the plethora of potential technological applications ranging from frequency‐agile metamaterials to electrochromic coatings and Mott field‐effect transistors. Here, unprecedented, pronounced metal‐insulator transitions induced by application of a voltage are demonstrated for nanowires of a vanadium oxide bronze with intercalated divalent cations, β‐Pb_xV₂O₅ (x ≈ 0.33). The induction of the phase transition through application of an electric field at room temperature makes this system particularly attractive and viable for technological applications. A mechanistic basis for the phase transition is proposed based on charge disproportionation evidenced at room temperature in near‐edge X‐ray absorption fine structure (NEXAFS) spectroscopy measurements, ab initio density functional theory calculations of the band structure, and electrical transport data, suggesting that transformation to the metallic state is induced by melting of specific charge localization and ordering motifs extant in these materials.     

Electrochemically Triggered Metal–Insulator Transition between VO2 and V2O5

Distinct properties of multiple phases of vanadium oxide (VO_x) render this material family attractive for advanced electronic devices, catalysis, and energy storage. In this work, phase boundaries of VO_x are crossed and distinct electronic properties are obtained by electrochemically tuning the oxygen content of VO_x thin films under a wide range of temperatures. Reversible phase transitions between two adjacent VO_x phases, VO₂ and V₂O₅, are obtained. Cathodic biases trigger the phase transition from V₂O₅ to VO₂, accompanied by disappearance of the wide band gap. The transformed phase is stable upon removal of the bias while reversible upon reversal of the electrochemical bias. The kinetics of the phase transition is monitored by tracking the time‐dependent response of the X‐ray absorption peaks upon the application of a sinusoidal electrical bias. The electrochemically controllable phase transition between VO₂ and V₂O₅ demonstrates the ability to induce major changes in the electronic properties of VO_x by spanning multiple structural phases. This concept is transferable to other multiphase oxides for electronic, magnetic, or electrochemical applications.     

Broad Range Tuning of Phase Transition Property in VO2 Through Metal‐Ceramic Nanocomposite Design

Vanadium dioxide (VO₂) is a well‐studied Mott‐insulator because of the very abrupt physical property switching during its semiconductor‐to‐metal transition (SMT) around 341 K (68 °C). In this work, through novel oxide‐metal nanocomposite designs (i.e., Au:VO₂ and Pt:VO₂), a very broad range of SMT temperature tuning from ≈ 323.5 to ≈ 366.7 K has been achieved by varying the metallic secondary phase in the nanocomposites (i.e., Au:VO₂ and Pt:VO₂ thin films, respectively). More surprisingly, the SMT T_c can be further lowered to ≈ 301.8 K (near room temperature) by reducing the Au particle size from 11.7 to 1.7 nm. All the VO₂ nanocomposite thin films maintain superior phase transition performance, i.e., large transition amplitude, very sharp transition, and narrow width of thermal hysteresis. Correspondingly, a twofold variation of the complex dielectric function has been demonstrated in these metal‐VO₂ nanocomposites. The wide range physical property tuning is attributed to the band structure reconstruction at the metal‐VO₂ phase boundaries. This demonstration paved a novel approach for tuning the phase transition property of Mott‐insulating materials to near room temperature transition, which is important for sensors, electrical switches, smart windows, and actuators.     

High‐Speed,Low‐Voltage,and Environmentally Stable Operation of Electrochemically Gated Zinc Oxide Nanowire Field‐Effect Transistors

Single‐crystal, 1D nanostructures are well known for their high mobility electronic transport properties. Oxide‐nanowire field‐effect transistors (FETs) offer both high optical transparency and large mechanical conformability which are essential for flexible and transparent display applications. Whereas the “on‐currents” achieved with nanowire channel transistors are already sufficient to drive active matrix organic light emitting diode (AMOLED) displays; it is shown here that incorporation of electrochemical‐gating (EG) to nanowire electronics reduces the operation voltage to ≤2 V. This opens up new possibilities of realizing flexible, portable, transparent displays that are powered by thin film batteries. A composite solid polymer electrolyte (CSPE) is used to obtain all‐solid‐state FETs with outstanding performance; the field‐effect mobility, on/off current ratio, transconductance, and subthreshold slope of a typical ZnO single‐nanowire transistor are 62 cm²/Vs, 10⁷, 155 μS/μm and 115 mV/dec, respectively. Practical use of such electrochemically‐gated field‐effect transistor (EG FET) devices is supported by their long‐term stability in air. Moreover, due to the good conductivity (≈10^?2 S/cm) of the CSPE, sufficiently high switching speed of such EG FETs is attainable; a cut‐off frequency in excess of 100 kHz is measured for in‐plane FETs with large gate‐channel distance of >10 μm. Consequently, operation speeds above MHz can be envisaged for top‐gate transistor geometries with insulator thicknesses of a few hundreds of nanometers. The solid polymer electrolyte developed in this study has great potential in future device fabrication using all‐solution processed and high throughput techniques.     

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V_FB < V_G < 0 V and the second for V_G < V_FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.     

Transition Metal Dichalcogenide‐Based Transistor Circuits for Gray Scale Organic Light‐Emitting Displays

Two types of transition metal dichalcogenide (TMD) transistors are applied to demonstrate their possibility as switching/driving elements for the pixel of organic light‐emitting diode (OLED) display. Such TMD materials are 6 nm thin WSe₂ and MoS₂ as a p‐type and n‐type channel, respectively, and the pixel is thus composed of external green OLED and nanoscale thin channel field effect transistors (FETs) for switching and driving. The maximum mobility of WSe₂‐FETs either as switch or as driver is ≈30 cm² V^?1 s^?1, in linear regime of the gate voltage sweep range. Digital (ON/OFF‐switching) and gray‐scale analogue operations of OLED pixel are nicely demonstrated. MoS₂ nanosheet FET‐based pixel is also demonstrated, although limited to alternating gray scale operation of OLED. Device stability issue is still remaining for future study but TMD channel FETs are very promising and novel for their applications to OLED pixel because of their high mobility and I _D ON/OFF ratio.     

Orders‐of‐Magnitude Reduction of the Contact Resistance in Short‐Channel Hot Embossed Organic Thin Film Transistors by Oxidative Treatment of Au‐Electrodes

In this study we report on the optimization of the contact resistance by surface treatment in short‐channel bottom‐contact OTFTs based on pentacene as semiconductor and SiO₂ as gate dielectric. The devices have been fabricated by means of nanoimprint lithography with channel lengths in the range of 0.3 μm < L < 3.0 μm. In order to reduce the contact resistance the Au source‐ and drain‐contacts were subjected to a special UV/ozone treatment, which induced the formation of a thin AuO_x layer. It turned out, that the treatment is very effective (i) in decreasing the hole‐injection barrier between Au and pentacene and (ii) in improving the morphology of pentacene on top of the Au contacts and thus reducing the access resistance of carriers to the channel. Contact resistance values as low as 80 Ω cm were achieved for gate voltages well above the threshold. In devices with untreated contacts, the charge carrier mobility shows a power‐law dependence on the channel length, which is closely related to the contact resistance and to the grain‐size of the pentacene crystallites. Devices with UV/ozone treated contacts of very low resistance, however, exhibit a charge carrier mobility in the range of 0.3 cm² V^–1 s^–1 < μ < 0.4 cm² V^–1 s^–1 independent of the channel length.     

Photoinduced Magnetization with a High Curie Temperature and a Large Coercive Field in a Co‐W Bimetallic Assembly

The crystal structure, magnetic properties, and temperature‐ and photoinduced phase transition of [{Co^II(4‐methylpyridine)(pyrimidine)}₂{Co^II(H₂O)₂}{W^V(CN)₈}₂]·4H₂O are described. In this compound, a temperature‐induced phase transition from the Co^II (S = 3/2)‐NC‐W^V(S = 1/2) [high‐temperature (HT)] phase to the Co^III(S = 0)‐NC‐W^IV(S = 0) [low temperature (LT)] phase is observed due to a charge‐transfer‐induced spin transition. When the LT phase is irradiated with 785 nm light, ferromagnetism with a high Curie temperature (T_C) of 48 K and a gigantic magnetic coercive field (H_c) of 27 000 Oe are observed. These T_C and H_c values are the highest in photoinduced magnetization systems. The LT phase is optically converted to the photoinduced phase, which has a similar valence state as the HT phase due to the optically induced charge‐transfer‐induced spin transition.     

Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.     

Few‐Layered PtS2 Phototransistor on h‐BN with High Gain

The very recently rediscovered group‐10 transition metal dichalcogenides (TMDs) such as PtS₂ and PtSe₂, have joined the 2D material family as potentially promising candidates for electronic and optoeletronic applications due to their theoretically high carrier mobility, widely tunable bandgap, and ultrastability. Here, the first exploration of optoelectronic application based on few‐layered PtS₂ using h‐BN as substrate is presented. The phototransistor exhibits high responsivity up to 1.56 × 10³ A W^?1 and detectivity of 2.9 × 10¹¹ Jones. Additionally, an ultrahigh photogain ≈2 × 10⁶ is obtained at a gate voltage V _g = 30 V, one of the highest gain among 2D photodetectors, which is attributed to the existence of trap states. More interestingly, the few‐layered PtS₂ phototransistor shows a back gate modulated photocurrent generation mechanism, that is, from the photoconductive effect dominant to photogating effect dominant via tuning the gate voltage from the OFF state to the ON state. Such good properties combined with gate‐controlled photoresponse of PtS₂ make it a competitive candidate for future 2D optoelectronic applications.     

Full Energy Spectra of Interface State Densities for n‐ and p‐type MoS2 Field‐Effect Transistors

2D materials are promising to overcome the scaling limit of Si field‐effect transistors (FETs). However, the insulator/2D channel interface severely degrades the performance of 2D FETs, and the origin of the degradation remains largely unexplored. Here, the full energy spectra of the interface state densities (D_it) are presented for both n‐ and p‐ MoS₂ FETs, based on the comprehensive and systematic studies, i.e., full rage of channel thickness and various gate stack structures with h‐BN as well as high‐k oxides. For n‐MoS₂, D_it around the mid‐gap is drastically reduced to 5 × 10¹¹ cm^?2 eV^?1 for the heterostructure FET with h‐BN from 5 × 10¹² cm^?2 eV^?1 for the high‐k top‐gate. On the other hand, D_it remains high, ≈ 10¹³ cm^?2 eV^?1, even for the heterostructure FET for p‐MoS₂. The systematic study elucidates that the strain induced externally through the substrate surface roughness and high‐k deposition process is the origin for the interface degradation on conduction band side, while sulfur‐vacancy‐induced defect states dominate the interface degradation on valance band side. The present understanding of the interface properties provides the key to further improving the performance of 2D FETs.     

Positively K+‐Responsive Membranes with Functional Gates Driven by Host–Guest Molecular Recognition

A novel positively K⁺‐responsive membrane with functional gates driven by host‐guest molecular recognition is prepared by grafting poly(N‐isopropylacrylamide‐co‐acryloylamidobenzo‐15‐crown‐5) (poly(NIPAM‐co‐AAB₁₅C₅)) copolymer chains in the pores of porous nylon‐6 membranes with a two‐step method combining plasma‐induced pore‐filling grafting polymerization and chemical modification. Due to the cooperative interaction of host‐guest complexation and phase transition of the poly(NIPAM‐co‐AAB₁₅C₅), the grafted gates in the membrane pores could spontaneously switch from “closed” state to “open” state by recognizing K⁺ ions in the environment and vice versa; while other ions (e.g., Na⁺, Ca²⁺ or Mg²⁺) can not trigger such an ion‐responsive switching function. The positively K⁺‐responsive gating action of the membrane is rapid, reversible, and reproducible. The proposed K⁺‐responsive gating membrane provide a new mode of behavior for ion‐recognizable “smart” or “intelligent” membrane actuators, which is highly attractive for controlled release, chemical/biomedical separations, tissue engineering, sensors, etc.     

Non‐Lithographic Fabrication of All‐2D α‐MoTe2 Dual Gate Transistors

As one of the emerging new transition‐metal dichalcogenides materials, molybdenum ditelluride (α‐MoTe₂) is attracting much attention due to its optical and electrical properties. This study fabricates all‐2D MoTe₂‐based field effect transistors (FETs) on glass, using thin hexagonal boron nitride and thin graphene in consideration of good dielectric/channel interface and source/drain contacts, respectively. Distinguished from previous works, in this study, all 2D FETs with α‐MoTe₂ nanoflakes are dual‐gated for driving higher current. Moreover, for the present 2D dual gate FET fabrications on glass, all thermal annealing and lithography processes are intentionally exempted for fully non‐lithographic method using only van der Waal's forces. The dual‐gate MoTe₂ FET displays quite a high hole and electron mobility over ≈20 cm² V^?1 s^?1 along with ON/OFF ratio of ≈10⁵ in maximum as an ambipolar FET and also demonstrates high drain current of a few tens‐to‐hundred μA at a low operation voltage. It appears promising enough to drive organic light emitting diode pixels and NOR logic functions on glass.     

A High‐k Fluorinated P(VDF‐TrFE)‐g‐PMMA Gate Dielectric for High‐Performance Flexible Field‐Effect Transistors

A newly synthesized high‐k polymeric insulator for use as gate dielectric layer for organic field‐effect transistors (OFETs) obtained by grafting poly(methyl methacrylate) (PMMA) in poly(vinylidene fluoride‐trifluoroethylene) (P(VDF‐TrFE)) via atom transfer radical polymerization transfer is reported. This material design concept intents to tune the electrical properties of the gate insulating layer (capacitance, leakage current, breakdown voltage, and operational stability) of the high‐k fluorinated polymer dielectric without a large increase in operating voltage by incorporating an amorphous PMMA as an insulator. By controlling the grafted PMMA percentage, an optimized P(VDF‐TrFE)‐g‐PMMA with 7 mol% grafted PMMA showing reasonably high capacitance (23–30 nF cm^?2) with low voltage operation and negligible current hysteresis is achieved. High‐performance low‐voltage‐operated top‐gate/bottom‐contact OFETs with widely used high mobility polymer semiconductors, poly[[2,5‐bis(2‐octyldodecyl)‐2,3,5,6‐tetrahydro‐3,6‐dioxopyrrolo [3,4‐c]pyrrole‐1,4‐diyl]‐alt‐[[2,2′‐(2,5‐thiophene)bis‐thieno(3,2‐b)thiophene]‐5,5′‐diyl]] (DPPT‐TT), and poly([N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)) are demonstrated here. DPPT‐TT OFETs with P(VDF‐TrFE)‐g‐PMMA gate dielectrics exhibit a reasonably high field‐effect mobility of over 1 cm² V^?1 s^?1 with excellent operational stability.     

Network Structure Modification‐Enabled Hybrid Polymer Dielectric Film with Zirconia for the Stretchable Transistor Applications

Stretchable electronic devices should be enabled by the smart design of materials and architectures because their commercialization is limited by the tradeoff between stretchability and electrical performance limits. In this study, thin‐film transistors are fabricated using strategies that combine the unit process of a novel hybrid gate insulator and low‐temperature indium gallium tin oxide (IGTO) channel layer and a stress‐relief substrate structure. Novel hybrid dielectric films are synthesized and their molecular structural configurations are analyzed. These films consist of a polymer [poly(4‐vinylphenol‐co‐methylmethacrylate)], cross‐linkers having different binding structures [1,6‐bis(trimethoxysilyl)hexane (BTMSH), dodecyltrimethoxysilane, and poly(melamine‐co‐formaldehyde)], and an inorganic zirconia component (ZrO_x). The hybrid film with BTMSH cross‐linker and 0.2 M ZrO_x exhibits excellent insulating properties as well as mechanical stretchability. IGTO transistors fabricated on polyimide‐coated glass substrates are transferred to the rubber substrate to offer stretchability of the transistor pixelated thin‐film transistors. IGTO transistors fabricated on stretchable substrates using these strategies show promising electrical performance and mechanical durability. After 200 stretchability test cycles under uniaxial elongation of approximately 300%, the IGTO transistor still retains a high carrier mobility of 21.7 cm² V^?1 s^?1, a low sub‐threshold gate swing of 0.68 V decade^?1 and a high I_ON/OFF ratio of 2.0 × 10⁷.