荧光灯电子驱动器VKO5CFL及其应用

<正> VK05CFL是意法半导体(ST)公司采用“VIPower M3-3”专利技术、专门为驱动5～23W小功率紧凑型荧光灯(CFL)而设计的单片IC。这种新型器件集成了新颖的功率开关及控制电路,可以用来组成自振荡半桥式逆变器去驱动CFL。     

TL镇流器电子驱动器VK06TL的应用

VK06TL是ST公司生产的带有控制电路和复合功率开关的TL电子镇流器驱动器。用该器件设计电子镇流器时，其灯预热频率、稳态工作频率及灯寿终定时保护等一些参数均可通过外部元件来设定。文中介绍了VK06TL的结构与特点，给出了其工作原理和典型应用电路。     

基于VK06TL的荧光灯电子镇流器

本文介绍意法半导体公司最近推出的VK06TL镇流器电子驱动器，它集成了预热功能和过热关闭及灯寿终(EOL)保护电路，仅需用很少量的外部元件，即可组成20～60W荧光灯电子镇流器。     

带预热功能的CFL控制器

本文设计了一款用于CFL的新型控制器,带预热功能,从而大大提高了CFL的寿命。该控制器包括振荡器、集成高压启动电路、参考电压电流电路、时钟分频电路、死区时间控制电路、预热电荷泵电路、两个高/低端驱动器、电感电流饱和保护电路和电容模式保护电路等。在应用中仅需外加少量元件,就可组成简单、低成本的CFL镇流器。     

CFL可调光电子镇流器控制器ML4836

紧凑型(小型)荧光灯(Compact Fluorecent Lamp,缩写为CFL),是目前家庭照明的主要电光源。迄今为止,CFL电子镇流器控制器专用IC只有L6567和ML4835/ML4836等几种。其中,ML4836是美国Micro Linear公司于2000年7月发布的新产     

荧光灯驱动器UBA2021及应用

<正> UBA2021是飞利浦公司最近生产的一种高压IC,专门为控制和驱动小功率紧凑型荧光灯(CFL)和直管形(TL)荧光灯而设计的。UBA2021只需外加很少的元件,即可组成灯预热与点火时间、预热电流及灯功率可调节并带有各种保护功能的CFL和TL灯电子镇流器。     

UBA2028可调光节能灯控制器原理与应用

<正> UBA2028是恩智浦半导体推出的紧凑型荧光灯电子镇流器控制与驱动高压功率IC。这种新型芯片集成了与UBA2014相同的CFL电子镇流器控制电路和半桥MOSFET栅极驱动器及两个半桥功率MOSFET(即UBA2014+半桥功率MOSFET二合一IC)。U-BA2028为CFL提供预热、引燃和调光等控制功能,并为系统提供保护功能,为目前设计5～25W的可调光CFL电子     

IR开创荧光灯照明用IC的业界全新标准

据美国加里福尼亚洲ELSEGUND2004年8月讯，IR公司近日宣布了有关采用IR2520D型镇流器控制集成电路的三种小尺寸荧光灯（CFL）镇流器标准设计。设计人员应用这些标准设计可以缩短其产品的上市时间。这种CFL镇流器标准设计的特征是工作频率和预热时间可编程，具有诸如低压AC线路、灯线开路及失效一触发的安全和电路保护功能。     

带预热启动和保护功能的CFL电子镇流器

《电子产品世界》９８年第１０期发表了“节能灯镇流器芯片ＩＲ５１Ｈ４２０应用”一文,介绍了ＩＲ５１Ｈ４２０的内部结构及其应用电路。该文所提供的紧凑型荧光灯（ＣＦＬ）电子镇流器电路,没有灯阴极预热启动和必要的保护功能。图１１３Ｗ２Ｕ型紧凑型荧光灯（ＣＦＬ...     

新型自振荡电源转换器VK05CFL

1.技术概述 VK05CFL是一种用于驱动微型荧光灯的自振荡转换器,采用意法半导体的VIPower M3-3专利技术制造而成,允许在同一芯片上集成控制部分和电源级。电源级是一个“发射器开关”,其构成是在级联配置内放置一个双极高压复合晶体管和一个低压MOSFET,因此,在高击穿电     

Is Poly(vinylcarbazole) a Good Host for Blue Phosphorescent Dopants in PLEDs? Dimer Formation and Their Effects on the Triplet Energy Level of Poly(N‐vinylcarbazole) and Poly(N‐Ethyl‐2‐Vinylcarbazole)

The detailed measurement and analysis of the delayed emission from poly(vinylcarbazole) (PVK) and poly(N‐ethyl‐2‐vinyl‐carbazole) (P2VK) thin films is described. PVK has rapidly become a “polymer of choice” for hosting phosphorescent dopants in PLEDs, especially blue emitters. In this respect it is important to have a full understanding of the triplet properties of this host. It is concluded that in films, the electronic 0–0 peak energy of PVK phosphorescence is found at 2.88 eV (14 K). With an increase of temperature, >44 K, increasing emission from new long lived, lower energy species, previously ascribed to “trap states” in the literature, is observed. Increasing temperature enables thermally assisted triplet exciton hopping to these trap states. Critically it is shown that some of these triplet trap species are ground state triplet dimers in origin for both PVK (2.46 eV) and P2VK (2.1 eV), and not all of them are of excimer nature as previously thought. These species can quench the emission of blue heavy metal complexes doped in PVK and drastically effect performance over lifetime if the dimer formation increases over time and at elevated operating temperature. It is therefore concluded that PVK might not be such an ideal host material for blue phosphorescent emitters.     

Nanopatterning by an Integrated Process Combining Capillary Force Lithography and Microcontact Printing

A novel nanopatterning process was developed by combining capillary force lithography (CFL) and microcontact printing (µCP). Flat polydimethylsiloxane (PDMS) was used as the substrate in CFL, and after chemical functionalization, as the stamp in µCP, which increased the resolution of both methods. The polymer patterns, produced by CFL on a thin polymer film on the flat PDMS substrate, acted as a mask to oxidize the uncovered regions of the PDMS. The chemical patterns were subsequently formed by gas phase evaporation of a fluorinated silane. After removal of the polymer, these stamps were used to transfer thiol inks to a gold substrate by µCP. Gold patterns at a scale of less than 100 nm were successfully replicated by these chemically patterned flat PDMS stamps.     

基于双极载流子导电的新型恒流器件

提出了一种基于双极载流子导电、具有低开启电压VK和高反向击穿电压BVR的恒流器件,并进行了初步的试验验证。利用Tsuprem4和Medici仿真工具对器件的恒定电流IS、开启电压VK、正向击穿电压BVF和反向击穿电压BVR等电学参数进行了仿真,优化了外延层电阻率ρepi、外延层厚度Tepi、JFET注入剂量DJFET、P-well注入窗口间距WJFET等参数。试验结果显示,该器件工作于正向时,开启电压VK约为1.6 V,恒定电流IS约为31 mA,正向击穿电压BVF为55 V;该器件工作在反向时,反向击穿电压BVR约为200 V。     

Theoretical Proof of Unconditional Stability of the 3-D ADI-FDTD Method

In order to eliminate Courant-Friedrich-Levy(CFL) condition restraint and improvecomputational efficiency,a new finite-difference time-domain(FDTD)method based on the alternating-direction implicit(ADI) technique is introduced recently.In this paper,a theoretical proof of the stabilityof the three-dimensional(3-D)ADI-FDTD method is presented.It is shown that the 3-D ADI-FDTDmethod is unconditionally stable and free from the CFL condition restraint.     

An asynchronously controlled EEG-based virtual keyboard: improvement of the spelling rate

An improvement of the information transfer rate of brain-computer communication is necessary for the creation of more powerful and convenient applications. This paper presents an asynchronously controlled three-class brain-computer interface-based spelling device [virtual keyboard (VK)], operated by spontaneous electroencephalogram and modulated by motor imagery. Of the first results of three able-bodied subjects operating the VK, two were successful, showing an improvement of the spelling rate sigma, the number of correctly spelled letters/min, up to sigma = 3.38 (average sigma = 1.99).     

A new FDTD algorithm based on alternating-direction implicit method

In this paper, a new finite-difference time-domain (FDTD) algorithm is proposed in order to eliminate the Courant-Friedrich-Levy (CFL) condition restraint. The new algorithm is based on an alternating-direction implicit method. It is shown that the new algorithm is quite stable both analytically and numerically even when the CFL condition is not satisfied. Therefore, if the minimum cell size in the computational domain is required to be much smaller than the wavelength, this new algorithm is more efficient than conventional FDTD schemes in terms of computer resources such as central-processing-unit time. Numerical formulations are presented and simulation results are compared to those using the conventional FDTD method     

多余度飞控计算机通道故障逻辑技术研究

在航空电子系统中,飞控计算机系统用于控制飞机的飞行功能,要求具有极高的可靠性,必须采用容错技术来满足要求。容错的重要方法是冗余。目前的飞控计算机系统,大多采用双余度、三余度及四余度的容错计算机。在余度计算机中,每一余度称为一个通道,每个通道均具有输出控制能力,因此余度计算机输出控制权的确定和交接就变得至关重要。介绍了道故障逻辑的功能需求和结构,重点研究了一种3×2余度飞控计算机系统通道故障逻辑的设计。     

Noise performance of a Cartesian loop transmitter

The Cartesian loop transmitter is now a well-known linear transmitter architecture and is finding application in a number of mobile radio systems employing linear modulation technologies. In particular, systems utilizing π/4 DQPSK require a linear transmitter, and many emerging standards [e.g., trans-European trunked radio (TETRA)] provide applications for the Cartesian feedback linearization (CFL) technique. One problem with the CFL transmitter is that its output-noise performance is no longer dominated by that of the RF power module employed within it (as is the case in more conventional transmitter architectures). The use of significant degrees of attenuation, followed by a high level of gain, within the loop, means that the noise performance of the loop is significantly poorer than that of a conventional transmitter. There are a number of tradeoffs that are available to the designer of a CFL transmitter to aid in the optimization of the output-noise performance. This paper presents a derivation of the noise performance of a Cartesian loop transmitter and highlights the design methods that may be employed in order to optimize its noise performance. It also provides a comparison of the theoretically derived behavior with that of a practical transmitter operating in the TETRA (380-400 MHz) band