金属纳米二聚体结构的局域表面等离子体激元共振特性研究

将金属纳米粒子二聚体结构作为光学谐振腔,采用 时域有限差分(FDTD)法仿真模拟了一种新型局域表面等离子体激光器(SPASER)。 使用洛伦兹复介电常数模型研究二聚体的增益介质特性,探讨了二聚体结构中 两个纳米局域表面等离子体激元共振(LSPR)以及相互作用机制,进一步研究了 LSPR相互作用对SPASER的局域场增强的影响。 模拟结果表明,相比较单纳米颗粒SPASER,LSPR的相互作用使得二聚体SPASER的局域电场显著 增强,增强因子最 大可以相差27倍。本文研究为纳米光学器件尤其是激光器件的设计提 供了依据。LSPR效应的 研究可以用于探索一些光与物质相互作用的极限效 应,从而为有源光子线路、生物传感以及量子信息处理等研究开辟道路。     

金纳米颗粒增强富硅氮化硅发光特性的研究

采用时域有限差分(FDTD)方法,对Au纳米颗粒的尺寸和形貌对于其光学特性的影响进行了系统的理论研究。通过采用等离子体增强化学气相沉积(PECVD)、晶化处理、电子束蒸发和高温退火等工艺,制备基于局域表面等离子共振(LSPR)效应的富硅氮化硅发光芯片。利用拉曼光谱仪、扫描电子显微镜(SEM)、奥林巴斯显微镜等对不同结构Au纳米颗粒富硅氮化硅发光器件的特性进行了表征。研究表明,通过对Au纳米颗粒的大小、形状和分布合理优化,富硅氮化硅芯片的发光强度在570nm波长附近提升了7倍,增强峰的位置红移了10nm。     

表面等离子体共振类熊猫型光子晶体光纤传感器

分析了基于表面等离子体共振类熊猫型的光子晶体光纤传感器,采用基于全矢量有限元法（FEM）对光纤模式进行了数值计算,在各向异性完美匹配层（PML）边界条件下,求解模场的有效折射率。讨论了各个参量的尺寸对传感的影响。计算表明,激发的等离子体对环境介质折射率的变化非常敏感,所设计传感器最大光谱灵敏度达到2 μm/RIU,若光谱仪的分辨率为10 pm,则传感器的分辨率可以达到5×10-6 RIU。     

光电子显微术的原理和应用

近十年来,光电子显微技术取得了长足进步并已商业化。光电子显微是一种高衬度的成像技术,对材料表面电子结构高度敏感。本文介绍光电子显微镜的成像原理,并着重分析其衬度机制。简要总结光电子显微术在表面结构分析,表面化学,磁学,以及半导体器件表征等方面的应用。目前光电子显微术的两个重要发展方向是利用同步辐射光源和脉冲激光光源做激发源;利用脉冲激光的多光子激发光电子显微术可以对较高功函数（大于光子能量）的材料成像;而脉冲时间分辨光电子显微术可用来研究表面瞬态电子的弛豫动力学机制。文章介绍了在实现飞秒时间分辨以及多光子激发的光电子显微方面的进展。我们利用多光子光电显微术对溅射制备的纳米结构银薄膜表面进行成像,结果表明多光子成像照片上存在一些高强度的亮点,而在单光子成像照片未观察到类似现象。推测这些亮点源于纳米结构银表面的等离子激元的高局域选择性激发。文章还介绍了利用光电子显微术原位观察CuZnAl形状记忆合金的热诱导相变。     

Hierarchically Ordered Arrays of Noncircular Silicon Nanowires Featured by Holographic Lithography Toward a High‐Fidelity Sensing Platform

A novel, highly uniform and tunable hybrid plasmonic array is created via ion‐milling, catalytic wet‐etching and electron‐beam evaporation, using a holographically featured structure as a milling mask. A simple and low‐cost prism holographic lithography (HL) technique is applied to create an unprecedentedly coordinated array of elliptic gold (Au) holes, which act as the silicon (Si) etching catalyst in the reaction solution used to fabricate an elliptic silicon nanowire (SiNW) array; here, the SiNWs are arrayed hierarchically in such a way that three SiNWs are triangularly coordinated, and the triangles are arranged hexagonally. After removing the polymeric mask and metal thin film, the highly anisotropic thick Au film is deposited on the SiNW arrays. This hybrid substrate shows tunable optical properties in the near‐infrared (NIR) region from 875 nm to 1030 nm and surface‐enhanced Raman scattering (SERS) activities; these characteristics depend on the catalytic wet etching time, which changes the size of the vertical gap between the Au thick films deposited separately on the SiNWs. In addition, lateral interparticle coupling induces highly intensified SERS signals with good homogeneity. Finally, the Au‐capped elliptical SiNW arrays can be hierarchically patterned by combining prism HL and conventional photolithography, and the highly enhanced fluorescence intensity associated with both the structural effects and the plasmon resonances is investigated.     

Plasma immersion ion implantation for SOI synthesis: SIMOX and ion-cut

We have demonstrated feasibility to form silicon-on-insulator (SOI) substrates using plasma immersion ion implantation (PIII) for both separation by implantation of oxygen and ion-cut. This high throughput technique can substantially lower the high cost of SOI substrates due to the simpler implanter design as well as ease of maintenance. For separation by plasma implantation of oxygen wafers, secondary ion mass spectrometry analysis and cross-sectional transmission electron micrographs show continuous buried oxide formation under a single-crystal silicon overlayer with sharp Si/SiO₂ interfaces after oxygen plasma implantation and high-temperature (1300°C) annealing. Ion-cut SOI wafer fabrication technique is implemented for the first time using PIII. The hydrogen plasma can be optimized so that only one ion species is dominant in concentration and there are minimal effects by other residual ions on the ion-cut process. The physical mechanism of hydrogen induced silicon surface layer cleavage has been investigated. An ideal gas law model of the microcavity internal pressure combined with a two-dimensional finite element fracture mechanics model is used to approximate the fracture driving force which is sufficient to overcome the silicon fracture resistance.     

Ag、Au纳米颗粒的激光表面修饰

通过用Nd：YAG激光（λ=1064nm）对氧化还原法制备的Ag、Au纳米颗粒的修饰,使Ag、Au纳米颗粒的尺寸均匀性得到更好的改善。用透射电子显微镜（TEM）和紫外-可见表面等离于体吸收（SPA）光谱对激光修饰后的Ag、Au纳米颗粒进行了测量和表征,结果表明,这些被修饰过的Ag、Au纳米颗粒由于自身体系发生了改变,可以作为更高效表面增强拉曼光谱（SERS）的增强基底。     

Hybrid time and hardware redundancy to mitigate SEU effects on SRAM-FPGAs: Case study over the MicroLAN protocol

SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets caused by high-energy space radiation. Single Event Upset (In order to successfully deploy the SRAM-FPGA based designs in aerospace applications, designers need to adopt suitable hardening techniques. In this paper, we describe novel hybrid time and hardware redundancy (HT&HR) structures to mitigate SEU effects on FPGA, especially digital circuits that are designed with bidirectional ports. The proposed structures that combine time and hardware redundancy decrease the SEU propagation mechanisms among the redundant hard units. Analysis results and fault injection experiments on some standard ISCAS benchmarks and MicroLAN protocol, as a case study over the bidirectional ports, show that the capability of tolerating SEU effects in HT&HR technique increases up to 70 times with respect to solely hardware redundant versions. On average, the proposed method provides 39.2 times improvement against single upset faults and 14.9 times for double upset faults; however it imposes about 14.7% area overhead. Also, for the considered benchmarks, HT&HR circuits become 8.8% faster on the average than their TMR versions.     

Evolution from symbol‐level space–time coded MIMO to chip‐level space–time coded MIMO: a review

Space–time coded multiple‐input multiple‐output (MIMO) technology is an important technique that improves the performance of wireless communication systems significantly without consuming bandwidth resource. This paper first discusses the characteristics and limitations of traditional symbol‐level space–time coding schemes, which work largely on the basis of an assumption that signals are sent to a block‐fading channel. Therefore, the symbol‐level space–time coding schemes rely on symbol‐level signal processing. Taking advantage of orthogonal complementary codes, we propose a novel MIMO scheme, in this paper, based on chip‐level space–time coding that is different from the traditional symbol‐level space–time coding. With the help of space–time–frequency complementary coding and multicarrier modem, the proposed scheme is able to achieve multipath interference‐free and multiuser interference‐free communications with simple a correlator detector. The proposed chip‐level space–time coded MIMO works well even in a fast fading channel in addition to its flexibility to achieve diversity and multiplexing gains simultaneously in varying channel environments. Copyright © 2012 John Wiley & Sons, Ltd.