一种适合模拟与视频信号处理的高速IC工艺

Zetex 公司(位于纽约州的Hauppauge)推出了一种新的制造高速双极型模拟集成电路的新工艺技术,并且正用它来生产音响与视频信号处理集成电路产品。这种命名为ZA工艺的生产工艺,是0.6微米、两层金属层的工艺技术。它采用氧化物隔离技术,可以降低线     

A CMOS field-programmable analog array

The design details and test results of a field-programmable analog array (FPAA) prototype chip in 1.2-μm CMOS are presented. The analog array is based on subthreshold circuit techniques and consists of a collection of a homogeneous configurable analog blocks (CABs) and an interconnection network. Interconnections between CABs and the analog functions to be implemented in each block are defined by a set of configuration bits loaded serially into an onboard shift register by the user. Macromodels are developed for the analog functions in order to simulate various neural network applications on the field-programmable analog array     

Architecture of field-programmable gate arrays

A survey of field-programmable gate array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their volatility, size parasitic capacitance, resistance, and process technology complexity. FPGA architectures are divided into two constituents: logic block architectures and routing architectures. A classification of logic blocks based on their granularity is proposed, and several logic blocks used in commercially available FPGAs are described. A brief review of recent results on the effect of logic block granularity on logic density and performance of an FPGA is then presented. Several commercial routing architectures are described in the context of a general routing architecture model. Finally, recent results on the tradeoff between the flexibility of an FPGA routing architecture, its routability, and its density are reviewed     

Superconductive analog signal processing devices

Real-time signal processing is important in many emerging applications in areas such as pulse-compression radar, spread-spectrum communications, and electronic warfare. The required digitally equivalent computational rate for these applications is on the order of 10² arithmetic operations per second and the required instantaneous bandwidths could approach 10 GHz. These exceed by nearly three orders of magnitude the capabilities projected for digital systems in the near future, and even exceed that of recently developed analog technologies such as surface-acoustic-wave (SAW) signal-processing devices. To meet anticipated future system needs, superconductive analog signal-processing components with bandwidths of 2 GHz have recently been realized, and the technology is being developed for the realization of 10-GHz bandwidths. Issues of fabrication technology and subsystem integration are examined for superconductive analog signal-processing devices     

FIR filters with field-programmable gate arrays

Distributed arithmetic techniques are the key to efficient implementation of DSP algorithms in FPGAs. The distributed arithmetic process is briefly described. A representative DSP design application in the form of an 8 tap FIR filter is offered for the Xilinx XC3042 field programmable logic array (FPGA). The design is presented in sufficient detail—from filter specifications via filter design software through detailed logic of salient data and control functions to obtain a realistic placing and routing of configurable logic block (CLBs) and in/out block (IOBs) components for simulation verification and performance evaluation vis-a-vis commercially available dedicated 8 tap FIR filter chips.     

Configurable analogue building blocks for field-programmable analogue arrays

In this article, the design of configurable analogue blocks for field programmable analogue arrays is presented. The configurable blocks are capable of performing integration, differentiation, amplification, log, anti-log, add and negate functions. The realisation of these functions depends on differential continuous-time current-mode translinear loop techniques. To maintain high frequency operation, the programmability and configurability of the blocks are achieved by modifying the block's biasing conditions digitally. Simulation results for the presented circuits are included.     

The yield enhancement of field-programmable gate arrays

The fine granularity and reconfigurable nature of field-programmable gate arrays (FPGA's) suggest that defect-tolerant methods can be readily applied to these devices in order to increase their maximum economic sizes, through increased yield. This paper identifies the inability to contain faults within single cells and the need for fast reconfiguration as the key obstacles to obtaining a significant increase in yield. Monte Carlo defect modeling of the photolithographic layers of VLSI FPGA's is used as a foundation for the yield modeling of various defect-tolerant architectures. Results suggest that a medium-grain architecture is the best solution, offering a substantial increase in size without significant side effects. This architecture is shown to produce greater gate densities than the alternative approach of realizing ultralarge scale FPGA's-multichip modules     

CCD输出信号处理电路的研究

根据CCD输出视频信号的特点,对它进行处理时需要经过消除噪声、信号放大、模数转换等过程.使用集多种功能于一体的器件能够完成对视频信号的相关双采样、可编程放大、模数转换以及暗电平校正等功能.对该处理过程进行了详细的研究和分析,并将该芯片应用于面阵CCD相机系统中,使相机具有实时成像调节功能,得到了满意的数字图像.     

Nonuniformly coupled microstrip transversal filters for analog signal processing

The Fourier transform relationship between frequency response and impedance profile for single nonuniform transmission lines is used to derive the time-domain step response of single and coupled nonuniform lines. The expression for the step response of a characteristically terminated nonuniformly coupled transmission line structure is shown to correspond to the characteristic impedance profile. By using this relationship, any arbitrary step response can be realizing by utilizing nonuniformly coupled strip or microstrip lines for possible applications as waveform-shaping networks and chirp filters. A numerical procedure to compute the step response of the nonuniform coupled line four-port is also formulated in terms of frequency-domain parameters of an equivalent cascaded uniform coupled line model with a large number of sections. Sinusoidal and chirp responses are presented as examples that are readily implemented using coupling microstrip structures. The step response of an experimental nonuniformly coupled microstrip structure is presented to validate the theoretical results.<>     

Digital signal processing spectrum inversion for analog speech channels

Speech security communication systems applied to radio analog speech channels become more and more desirable as radio channel capacity increases and service area spreads. Analog spectrum inversion used in existing radio communication systems is suitable for preventing eavesdropping and ensuring security, but it suffers from inevitable speech quality degradations. It is shown that digital spectrum inversion can be accomplished merely by alternating the sign of the sampled data to avoid distortion. Digital inversion is theoretically deduced by the discrete Fourier transform and verified by experiments. The aperture effect is also discussed from the viewpoint of spectrum inversion. Digital spectrum inversion is implemented with exclusive OR gates and a one digit binary counter, which is easily integrated onto a large scale integration (LSI) chip to avoid element value deviation. Signal-to-noise ratio (SNR) and distortion are observed to be more than 50 dB and -50 dB right across the 0.3-3.7 kHz frequency band, when an 8 kHz sampling rate is adopted for digital processing.     

Optimum processing for delay-vector estimation in passive signal arrays

For the purpose of localizing a distant noisy target, or, conversely, calibrating a receiving array, the time delays defined by the propagation across the array of the target-generated signal wavefronts are estimated in the presence of sensor-to-sensor-independent array self-noise. The Cramér-Rao matrix bound for the vector delay estimate is derived, and used to show that either properly filtered beamformers or properly filtered systems of multiplier-correlators can be used to provide efficient estimates. The effect of suboptimally filtering the array outputs is discussed.     

A review of median filter systems for analog signal processing

This paper presents a review of existing analog implementations of the median and other ranked-order filter operations. The basic properties of median signal processing are first reviewed. Different analog median filter architectural approaches and implementations, introduced by several authors, are then discussed. These include filters based on analog delay lines and either nonlinear selection networks or ramp voltage generators. The Linear-Median Hybrid filter concept is presented and two examples of analog circuit implementations are given. Finally, a neural network approach is discussed.     

Charge-coupled device (CCD) analog signal processing

Analog charge-coupled devices and sampled data filtering have developed into mature disciplines. Each discipline offers the other wide systems advantages where alone it would be impractical. This letter explores these advantages in a number of implementations against the scale of wide low-cost applications.     

High-speed signal processing using systolic arrays over finiterings

A modular architecture for very fast digital signal processing (DSP) elements are presented. The computation is performed over finite rings (or fields) and is able to emulate processing over the integer ring using residue number systems. The computations are restricted to closed operations (ring or field binary operators) with the ability to perform limited scaling operations. Computations naturally defined over finite mathematical systems are also easily implemented using this approach. The technique evolves from the decomposition of each closed calculation using the ring/field associativity property. Linear systolic arrays, formed with multiple elements, each of a single generic form, are used for all calculations. The pipeline cycle is determined from the generic cell and is predicted to be very fast by a critical path analysis. The cells are matched to the VLSI medium, and the resulting array structures are very dense. Examples of DSP applications are given to illustrate the technique, and example cell and array VLSI layouts are presented for a 3-μm CMOS process     

A high-precision current-mode multifunction analog cell suitable for computational signal processing

In this paper, a high linear, low-voltage two-quadrant current squarer as multifunction analog cell, is presented. To implement the squarer circuit, translinear loops with matched NMOS transistors operating in weak inversion region are used. The proposed cell is used as a basic building block for current-mode computational analog functions such as rectifier (absolute-value), multi-input vector summation and exponential function generator. We perform post-layout plus Monte Carlo simulations of the presented functions with 0.18 μm (level-49 parameters) TSMC CMOS technology that prove their superiority over some other advanced works and robustness against PVT (process, voltage and temperature) variations.     

Electronic-nose for detecting environmental pollutants: signal processing and analog front-end design

Environmental monitoring relies on compact, portable sensor systems capable of detecting pollutants in real-time. An integrated chemical sensor array system is developed for detection and identification of environmental pollutants in diesel and gasoline exhaust fumes. The system consists of a low noise floor analog front-end (AFE) followed by a signal processing stage. In this paper, we present techniques to detect, digitize, denoise and classify a certain set of analytes. The proposed AFE reads out the output of eight conductometric sensors and eight amperometric electrochemical sensors and achieves 91 dB SNR at 23.4 mW quiescent power consumption for all channels. We demonstrate signal denoising using a discrete wavelet transform based technique. Appropriate features are extracted from sensor data, and pattern classification methods are used to identify the analytes. Several existing pattern classification algorithms are used for analyte detection and the comparative results are presented.     

Adaptive algorithms for signal processing in multichannel receiving systems with antenna arrays

An analytic review of adaptive algorithms for signal processing in multichannel receiving systems with antenna arrays is presented. Adaptive algorithms for detection of a desired signal in the presence of intense interferences with arbitrary laws of time modulation are synthesized and their efficiency is analyzed.     

Parallel spatial processing: A cure for signal cancellation in adaptive arrays

A spatial processing algorithm with parallel structure is presented for the prevention of signal caneellation phenomena in conventional adaptive arrays. This algorithm basically uses a parallel structure with a spatial averaging effect to combat coherent jamming. It results in a spatially smoothed maximum-likelihood estimate of the desired signal when the adaptive beamformer converges. Simulations have been conducted which verify the effectiveness of the proposed structure.