Efficient reversible NOR gates and their mapping in optical computing domain

Reversible logic is a computing paradigm in which there is a one to one mapping between the input and the output vectors. Reversible logic gates are implemented in an optical domain as it provides high speed and low energy computations. In the existing literature there are two types of optical mapping of reversible logic gates: (i) based on a semiconductor optical amplifier (SOA) using a Mach–Zehnder interferometer (MZI) switch; (ii) based on linear optical quantum computation (LOQC) using linear optical quantum logic gates. In reversible computing, the NAND logic based reversible gates and design methodologies based on them are widely popular. The NOR logic based reversible gates and design methodologies based on them are still unexplored. In this work, we propose two NOR logic based n-input and n-output reversible gates one of which can be efficiently mapped in optical computing using the Mach–Zehnder interferometer (MZI) while the other one can be mapped efficiently in optical computing using the linear optical quantum gates. The proposed reversible NOR gates work as a corresponding NOR counterpart of NAND logic based Toffoli gates. The proposed optical reversible NOR logic gates can implement the reversible boolean logic functions with a reduced number of linear optical quantum logic gates or reduced optical cost and propagation delay compared to their implementation using existing optical reversible NAND gates. It is illustrated that an optical reversible gate library having both optical Toffoli gate and the proposed optical reversible NOR gate is superior compared to the library containing only the optical Toffoli gate: (i) in terms of number of linear optical quantum gates when implemented using linear optical quantum computing (LOQC), (ii) in terms of optical cost and delay when implemented using the Mach–Zehnder interferometer.     

关于三值维持阻塞JK触发器的研究

提出了一种具有在输出的三值维持阻塞ＪＫ触发器电路，描述了该触发器电路的设计，对由ＴＴＬ门电路组成的试验电路进行了计算机模拟和测试，结果表明，该触发器能实现预定的功能。     

Differential switching operation of vertical cavity laser with depleted optical thyristor for optical logic gates

Optical logic gates with AND, OR, and INVERT functionality are demonstrated by the monolithic integration of a vertical cavity laser with depleted optical thyristor. All kinds of logic functions (AND, OR, NAND, NOR, and INVERT) are experimentally demonstrated using a differential switching operation scheme by simply controlling an intensity of a reference input light     

Inverting and latching optical logic gates based on the integrationof vertical-cavity surface-emitting lasers and photothyristors

Inverting optical logic gates based on the monolithic integration of a vertical-cavity surface-emitting laser (VCSEL) with a heterojunction photothyristor (PNPN) are described. Logic functions INVERT, NAND, and NOR are experimentally demonstrated for the first time using latchable and cascadable PNPN/VCSEL switches, which can be triggered with very low optical energy, while producing high optical gain and optical contrast. These gates are integrable on a single epitaxial structure to provide multifunctional logic and memory arrays     

基于误码统计的边沿触发器建立时间测量方法

建立时间是边沿触发器的一个重要技术参数,在设计跨时钟域电路和高速数字电路时起着关键性的作用。介绍了一种对集成边沿触发器或自制边沿触发器的建立时间进行物理测量的方法,利用同一脉冲分别作用于触发器的时钟端和输入端,通过延时器对两个端口的脉冲进行时延扫描调节,就可测得该触发器的误码统计分布曲线,从而获得较为精确的建立时间参数。对集成边沿触发器74LS74芯片进行了实测,测试精度可达1ps。     

Ultrahigh-speed reconfigurable logic gates based on four-wave mixing in a semiconductor optical amplifier

We have demonstrated simple reconfigurable all-optical logic operations based on four-wave mixing in semiconductor optical amplifier and encoding information in the polarization of the input signals. Experimental implementation of six logic functions (including XOR, XNOR, AND, NOR, etc.) operating at 10 Gb/s were realized by simply adjusting two polarization controllers in the setup.     

Using multi-threshold threshold gates in RTD-based logic design: A case study

The basic building blocks for resonant tunneling diode (RTD) logic circuits are threshold gates (TGs) instead of the conventional Boolean gates (AND, OR, NAND, NOR) due to the fact that, when designing with RTDs, TGs can be implemented as efficiently as conventional ones, but realize more complex functions. Recently, RTD structures implementing multi-threshold threshold gates (MTTGs) have been proposed which further increase the functionality of the original TGs while maintaining their operating principle and allowing also the implementation of nanopipelining at the gate level. This paper describes the design of n-bit adders using these MTTGs. A comparison with a design based on TGs is carried out showing advantages in terms of power consumption and power delay product.     

确定主从JK触发器次态的方法

讨论了主从JK触发器“一次变化”的由来及根据“一次变化”的概念确定主从JK触发器次态的方法。     

Fiber loop optical buffer

Fiber loop optical buffers enable data storage for discrete time intervals and therefore appear suitable for applications in optical asynchronous transfer mode (OATM)-based networks where data are transmitted in cells of fixed length. In this paper, the feasibility and the limitations of optical data storage in a fiber loop optical buffer are studied theoretically and experimentally, A model of a fiber loop buffer, incorporating semiconductor laser amplifiers (SLA) as switching gates, is described. The two major interfering quantities are cross talk and amplified spontaneous emission of the SLA gates. To limit the impact of cross talk on the signal quality, an on/off ratio of the SLA gates of at least 30 dB is required. The paper describes the optimum operation conditions, which enable data storage for more than 100 circulations even for data rates in the range from 10 to 160 Gb/s     

40 Gbit=s reconfigurable photonic logic gates based on various nonlinearities in single SOA

40 Gbit/s reconfigurable photonic logic gates with XNOR, AND, NOR, OR and NOT functions are demonstrated, based on various nonlinearities of a single semiconductor optical amplifier (SOA), including four-wave mixing (FWM), cross-gain modulation (XGM) and transient cross-phase modulation (T-XPM). Detuning optical bandpass filters are employed to enhance the SOA modulation bandwidth.     

IST-LASAGNE: towards all-optical label swapping employing optical logic gates and optical flip-flops

The Information Society Technologies-all-optical LAbel SwApping employing optical logic Gates in NEtwork nodes (IST-LASAGNE) project aims at designing and implementing the first, modular, scalable, and truly all-optical photonic router capable of operating at 40 Gb/s. The results of the first project year are presented in this paper, with emphasis on the implementation of network node functionalities employing optical logic gates and optical flip-flops, as well as the definition of the network architecture and migration scenarios.     

Shunt-feedback Schottky clamped logic gates

A new approach to digital circuit design is used to develop a new family of TTL-compatible shunt-feedback Schottky clamped logic gates. The virtual ground like input of the shunt-feedback amplifier and the low-impedance input of the familiar diode-biased current source are utilized to perform certain logic and fan-out operations without requiring full logic swings. Voting logic operations as well as conventional Boolean logic operations, such as AND, NAND, OR, NOR, AND-OR, AOI, etc., can all be performed with approximately the same one-gate delay of 2.5 ns. Average dissipation of the NAND gate is 17 mW. The series-terminated transmission-line connection without requiring full logic swing is described.     

Optical parallel logic gates using a shadow-casting system for optical digital computing

A new, simple method of optically implementing optical parallel logic gates has been described. Optical parallel logic gates can be implemented by using a lensless shadow-casting system with a light-emitting diode (LED) array as a light source. Pattern logic, i.e., parallel logic for two binary patterns (variables), is simply obtained with these gates; this logic describes a complete set of logical operations on a large array of binary variables in parallel. Coding methods for input images are considered. Applications of the method for a parallel shift operation and optical digital image processing, processing of gray-level images, and parallel operations of addition and subtraction for two binary variables are presented. Comparison of the operation of the proposed optical logic gate with that of array logic in digital electronics leads to a design concept for an optical parallel array logic system available for optical parallel digital computing.     

Digital optical signal processing with polarization-bistable semiconductor lasers

The operations of a complete set of optical AND, NAND, OR, and NOR gates and clocked opticalS-R, D, J-K,andTflip-flops are demonstrated, based on direct polarization switching and polarization bistability, which we have recently observed in InGaAsP/InP semiconductor lasers. By operating the laser in the direct-polarization-switchable mode, the output of the laser can be directly switched between the TM00and TE00modes with high extinction ratios by changing the injection-current level, and optical logic gates are constructed with two optoelectronic switches or photodetectors. In the polarization-bistable mode, the laser exhibits controllable hysteresis loops in the polarization-resolved power versus current characteristics. When the laser is biased in the middle of hysteresis loop, the light output can be switched between the two polarization states by injection of short electrical or optical pulses, and clocked optical flip-flops are constructed with a few optoelectronic switches and/or photodetectors. The 1 and 0 states of these devices are defined through polarization changes of the laser and direct complement functions are obtainable from the TE and TM output signals from the same laser. Switching of the polarization-bistable lasers with fast-rising current pulses has an instrument-limited mode-switching time on the order of 1 ns. With fast optoelectronic switches and/or fast photodetectors, the overall switching speed of the logic gates and flip-flops is limited by the polarization-bistable laser to < 1 ns. We have demonstrated the operations of these devices using optical signals generated by semiconductor lasers. The proposed schemes of our devices are compatible with monolithic integration based on current fabrication technology and are applicable to other types of bistable semiconductor lasers.     

A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter

A new low-power full-adder based on CMOS inverter is presented. This full-adder is comprised of inverters. Universal gates such as NOR, NAND and MAJORITY-NOT gates are implemented with a set of inverters and non-conventional implementation of them. In the proposed design approach the time consuming XOR gates are eliminated. As full-adders are frequently employed in a tree-structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is employed to evaluate the full-adders in a realistic application environment. The circuits being studied were optimized for energy efficiency using 0.18 μm and 90 nm CMOS process technologies. The proposed full-adder shows full swing logic, balanced outputs and strong output drivability. It is also observed that the presented design can be utilized in many cases especially whenever the lowest possible power consumption is targeted. Circuits layout implementations and checking their functionality have been done using Cadence IC package and Synopsys HSpice, respectively.     

Experimental operation of an RS flip-flop composed of nonlatchingJosephson gates

We present the experimental implementation of an RS flip-flop (RS-FF) composed of dc-biased coupled-SQUID (C-SQUID) gates. The C-SQUID gate is a combination of a single-junction SQUID and a double-junction SQUID. This gate utilizes nonhysteretic Josephson junctions and it is operated in nonlatching mode with dc-biasing. Several logical functions are able to be realized with a C-SQUID gate by adjusting the input bias and the input signal levels. The speed performance of the gate is evaluated by simulation for ring oscillators, and the minimum switching delay of 6.5 ps/stage is obtained under Josephson critical current density of 10 kA/cm². We have fabricated the RS-FF composed of two C-SQUID NOR gates. The circuit is integrated using a Nb/AlO_x /Nb junction technology and its operation is demonstrated experimentally     

低功耗双边沿触发器的逻辑设计

本文从消除时钟信号冗余跳变而致的无效功耗的要求出发,提出双边沿触发器的设计思想与基于与非门的逻辑设计．用ＰＳＰＩＣＥ程序模拟证实了该种触发器具有正确的逻辑功能,能够正常地应用于时序电路的设计,并且由于时钟工作频率减半而导致系统功耗的明显降低．     

Josephson edge-triggered gates for sequential circuits

A Josephson sequential logic family with a very wide operating margin (±67%) and insensitivity to global parameter variations is proposed. Derived from the original idea of the edge-triggered latching comparator by C. Hamilton et al. (see IEEE Trans Magnetics, vol.MAG-21, p.197-9, 1985), this logic gate consists of a pair of conventional gates in series biased by a delay clock. In normal operation, switching occurs in one and only one of the gates, depending on which one has the smaller critical current. The authors have built and tested a few circuits to illustrate this logic gate design: a 32-b shift register designed by OR gates with ±42% bias margin and ±89% input margin, a 4-b pseudorandom sequence generator designed by exclusive-OR gates with ±27% bias margin and ±78% input margin, and cross section of a 6-b NOR gate decoder with ±33% bias margin     

Semiconductor laser diode optical amplifiers/gates in photonicpacket switching

In this paper, we will describe how semiconductor laser diode optical amplifiers/gates can be used in the photonic packet switching systems based on wavelength division multiplexed (WDM) techniques. First, we show that cross-gain modulation (XGM) can be suppressed when the device is used in the transparent condition of the waveguide material even when the input signal power exceeds +18 dBm. We then discuss an appropriate encoding for the optical signal. Experimental results show that high bit rate Manchester-encoding enables the use of semiconductor laser diode optical amplifiers/gates in the gain condition as well as the transparent condition. Finally, a new photonic packet receiver which utilizes a semiconductor laser diode optical amplifier as a packet power equalizer is proposed. This receiver accepts 17 dB power fluctuation at nanosecond speed for 10 Gb/s Manchester-encoded signal     

All optical XOR logic gates: technologies and experiment demonstrations

This article reviews the current status and technologies of all-optical XOR gates. Various schemes with semiconductor optical amplifiers, particularly those associated with interferometric structures, are discussed and compared. Finally, the applications of all-optical XOR gates to emerging networks are explored, and the future direction is outlined.