数据中心供配电系统设计

主要介绍了数据中心对供配电系统的要求及其设计方法。将数据中心对供配电系统的可靠性要求分为极高可靠性要求、高可靠性要求、一般可靠性要求三个层次,数据中心供配电系统应根据不同的供电可靠性要求,在供电电源选择、供配电系统布置、供配电系统结构和形式等各方面采取相应的技术措施。数据中心供配电系统设计应遵循分区、分级的原则,并充分运用成熟有效的节能措施。     

大型数据中心供配电系统设计研究

主要介绍数据中心对供配电系统的要求及其设计方法;数据中心供配电系统应根据不同的供电可靠性要求,在供电电源选择、供配电系统布置、供配电系统结构和形式等各方面采取相应的技术措施;数据中心供配电系统设计应遵循分区、分级的原则,并充分运用成熟的节能措施。     

加固计算机用开关电源的可靠性设计

对加固计算机用开关电源的可靠性设计进行了系统的探讨。结合开关电源的原理．对影响其可靠性的因素和元器件的选用原则进行了阐述,着重分析了加固计算机用开关电源的可靠性设计：电应力设计、保护电路设计、热设计、电磁兼容性设计、安全性设计和三防设计。其目的在于提高加固计算机用开关电源的可靠性。     

低压供配电系统在高层建筑电气设计中的可靠性探讨

在高层建筑中低压供配电系统占据着很重要的地位,在设计该系统时应当对其可靠性给予高度的重视.由于高层建筑的电气设备的类型种类繁多,数量也较多,因此在安全问题上要尤为重视,因此做好高层建筑电气设计,就必须要围绕低压供配电系统的设计展开渗入的研究,然后才能形成方案,还要进行多次优化.本文结合高层建筑供配电系统设计要求进行阐述,提出关于高层建筑低压电源配置以及电气设计低压配电系统的可靠性的设计的研究观点,期望对于提高高层建筑设计质量具有参考价值.     

基于单片机的无线传感网络通信模块设计与实现

采用单片机进行无线传感网络通信模块设计,提高无线传感网络通信的保真性和稳定性,文章设计的无线传感网络通信系统主要包括了传感器模块电路设计、无线传感网络通信的时钟电路模块设计、晶振电路设计、AD电路设计以及单片机的JTAG电路设计等。建立嵌入式STM32开发环境实现硬件电路集成设计,首先进行了无线传感网络通信模块的总体设计描述,进行通信模块技术指标分析,采用单片机作为核心处理芯片,进行无线传感网络通信的模块化设计。系统调试结果表明,采用该设计的通信模块进行无线传感器网络通信的稳定性较好,通信误码率降低,电路系统的可靠性较高。     

磁偏转质谱计高压扫描电源的设计

文中针对磁偏转质谱计用高压扫描电源的应用需求,设计了一种可靠性较高的适用于卫星用磁偏转质谱计的高压扫描电源电路,详细论述了总体电路设计、串联调节母线设计、倍压整流电路设计、变压器设计等,最后进行了仿真和测试,给出了结论。     

稳压元件可靠性降额设计

本文对有关标准进行研究分析后,提出稳压元件可靠性降额设计的见解,可供有关可靠性设计、电路设计人员参考.     

电气工程供配电系统设计与分析

供配电系统设计对人们日常生活影响较大,其是一个复杂的系统工程,为此,对电气工程供配电系统进行设计与分析。使用低压断路器,起到漏电保护功能。使用防雷与及接地装置,避免雷击危害。根据电气工程接线需求,通过自动开关接通电路或断开。将插座和开关作为电气系统终端,确保设备在稳定安全环境中运行。分析照明供配电网设计要点,引出供电电源,实现对照明系统供电。设计微机防误操作方案,保证供配电系统能够严格按照操作要求进行工作,避免出现错误操作,提高供配电系统运行的可靠性。     

新型船用时统可靠性设计

针对某型测量船站时统可靠性设计不满足当前任务需求的现状,本文从其物理模型出发,建立了可靠性框图及可靠性数学模型。以该系统2年间的可靠性表现为基础,对新一代时统的可靠性进行设计,并通过比例组合法对各模块的可靠度进行了分配。为后续电路设计及元器件选型提供了参考。     

高科技制造工厂供配电系统探讨

阐述了高科技制造工厂对于电力的可靠性、稳定性、连续性的需求,从集成电路工厂供配电系统的特点和对供配电系统要求方面,进行了系统的说明和探讨。     

体硅集成电路版图抗辐射加固设计技术研究

辐射效应是电路在太空等领域应用时遇到的首要问题,常常会引起电路出错或失效。为了满足抗辐射电路设计的需求,必须提高电路抗辐射效应的能力。文章分析了辐射效应对器件产生的影响。针对电路在辐射环境中应用时存在的问题,文章从版图抗辐射设计加固的角度出发,介绍了抗总剂量的环形栅、倒比例器件,以及抗单粒子昆倾效应抗辐射版图的设计方法。在电路设计时,通过上述几种版图设计方法的应用,可以提高电路的抗辐射性能,进而提高电路的可靠性。     

基于空间应用的红外探测器驱动电路设计

以空间应用为目的,提出基于国产1024×6长波红外探测器的驱动电路设计方案。该方案利用LDO和电压跟随器产生探测器需要的驱动电压。通过对该方案进行论证及在某型号空间相机中应用,证明该方案切实有效,能够较好的满足空间应用需求。     

航天电子设备二次电源输入保护电路设计

针对航天电子设备在特殊工作环境下的电源电路设计要求的特殊性,分析了其供电环境和电源变换器的工作原理,提出了采用集成DC/DC变换器时外围保护电路设计的一般原则,结合工程实践给出了常用星载电子设备和火箭(导弹)载电子设备电源保护电路方案,并对保护电路设计参数提出控制指标的建议.     

Surrogating circuit design solutions with robustness metrics

With the increase in device variability, the performance uncertainty poses a daunting challenge to analog/mixed-signal circuit design. This situation requires a robust design approach to add large margins to the circuit and system-level specification to ensure correct operation and the overall yield. In this paper, we propose a new robust design approach by using norm metrics to quantify the robustness for both design parameters and performance uncertainty. In addition, we adopt a surrogating procedure to achieve robustness in design space and to reduce uncertainty in performance space. The end result of the proposed method is a Pareto-surface that provides the designer with trade-offs between design robustness and performance uncertainty. One advantage of this new approach is the ability to take into account the strong nonlinear relationship between performance and design parameters. Considering a set of highly nonlinear circuit performances, we demonstrate the effectiveness of this robust design framework on a fully CMOS operational amplifier circuit.     

基于自振混频的下变频接收电路设计

文中设计了一种基于自振混频(SOM)电路的小型化、低成本下变频接收电路。自振混频电路是基于 辅助源电路进行仿真分析与设计,以单器件场效应管(FET)实现了变频接收电路中变频与本振两种功能的电路。设 计中还将不同种类的功能电路通过垂直压叠的方式实现层间互联,进一步提高了系统集成度。文中提出了基于自 振混频的功能电路集成和基于分离器件层间填埋的结构集成相结合的设计方法,最终在58 mm×20 mm×2. 9 mm 的 空间内实现了融天线为一体的小型化、低成本、低功耗的下变频接收通道,变频增益-4~-8 dB,整体功耗<0. 13 W。     

Measuring the uniqueness and variety of analog circuit design features

Analog circuit design activity is currently a less formalized process, in which the main source for innovation is the designer's ability to produce new designs by combining basic devices, sub-circuits, and ideas from similar solutions. There are few systematic methods that can fuse and transform the useful features of the existing designs into new solutions. Moreover, most automated circuit synthesis tools are still limited to routine tasks, like transistor sizing and layout design. Developing new design techniques that can combine the existing design features requires metrics that describe the uniqueness and variety of the features. This paper evaluates for analog circuits two such general-purpose metrics proposed in [1] and [2]. Three case studies are discussed on using the metrics to characterize the design features of current mirrors, transconductors, and operational amplifiers. The two metrics and the presented study is useful in producing an overall characterization of analog circuit features. This can help in enhancing the circuit design process, training of young designers, and developing new automated synthesis tools that can explore more solution space regions that are likely to include novel design features.     

Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits

The proportion of interconnect delay in the critical path on a chip is increasing and becomes over 20% in sub-10nm technologies, which means in order to capture post-Si performance accurately, the representative critical path circuit should reflect not only FEOL (front-end-of-line) but also BEOL (back-end-of-line) variations. Since the number of BEOL metal layers exceeds ten and the layers have variation on resistance and capacitance intermixed with resistance variation on vias between them, a very high dimensional design space exploration is necessary to synthesize a representative critical path circuit which is able to provide an accurate performance prediction. To this end, we propose a BEOL-aware methodology of synthesizing a representative critical path circuit, which is able to incrementally explore, starting from an initial path circuit on the post-Si target circuit, routing patterns (i.e., BEOL reconfiguring) as well as gate resizing on the path circuit. Precisely, our synthesis framework of critical path circuit integrates a set of novel techniques: (1) extracting and classifying BEOL configurations for lightening design space complexity, (2) formulating BEOL random variables for fast and accurate timing analysis, and (3) exploring alternative (ring oscillator) circuit structures for extending the applicability of our work. In summary, our synthesis framework is able to reduce the prediction error by 54% and 19% on average over that using the conventional critical path replica and using the conventional method exploiting gate sizing only, respectively.     

序列二次逼近下的集成电路统计最优化方法

基于对电路特性函数的序列正交二次逼近，本文给出了考虑工艺参数随机起伏引起电路特性随机变化的统计最优化方法。该方法是根据集成电路设计和制造的特殊性提出的，它与传统的统计最优化模型和方法有显著区别，适合于电路设计参数和工艺扰动参数不在同一空间的最优化问题。本文给出了这一模型的理论框架及其证明，并结合ＣＭＯＳ电路的最优设计证明了该方法的可行性和实用性，得到了满意的结果。     

Expediting analog design retargeting by design knowledge re-use and circuit synthesis: a practical example on a Delta-Sigma modulator

In the past decade or two, due to constant and rapid technology changes, analog design re-use or design retargeting to newer technologies has been brought to the table in order to expedite the design process and improve time-to-market. If properly conducted, analog design retargeting could significantly cut down design cycle compared to designs starting from the scratch. In this article, we present an empirical and general method for efficient analog design retargeting by design knowledge re-use and circuit synthesis (CS). The method first identifies circuit blocks that compose the source system and extracts the performance parameter specifications of each circuit block. Then, for each circuit block, it scales the values of design variables (DV) from the source design to derive an initial design in the target technology. Depending on the performance of this initial target design, a design space is defined for synthesis. Subsequently, each circuit block is automatically synthesised using state-of-art analog synthesis tools based on a combination of global and local optimisation techniques to achieve comparable performance specifications to those extracted from the source system. Finally, the overall system is composed of those synthesised circuit blocks in the target technology. We illustrate the method using a practical example of a complex Delta-Sigma modulator (DSM) circuit.     

一种基于进化的电路网络建模方法

针对电路设计繁冗、复杂及周期长等特点,提出了一种基于进化的电路网络建模方法,该方法把电路网络建模过程转变为电路元器件选择和元件值确定的搜索优化过程.利用遗传程序设计进化电路网络的结构,对元器件和元件值相互影响的复杂解空间进行全局寻优,实现电路网络的进化.