Fault Coverage on RF VCOs and BIST for Wafer Sort Using Peak-to-Peak Voltage Detectors

A complete study of the fault coverage achievable on two Radio Frequency (RF) Voltage Controlled Oscillators (VCO) is carried out. The peak-to-peak output voltage detection grants the maximal catastrophic and parametric fault coverage. The VCOs and the BIST (Built-In Self-Test) circuitry are designed using the STM CMOS 65 nm process. The frequency of oscillation is 3.6 GHz and the phase noise obtained at 1 MHz offset from the carrier is of −121.7 dBc/Hz for VCO1 and of −118.8 dBc/Hz for VCO2. The performances of the VCOs are simulated before and after the insertion of the circuitry for the BIST, in order to confirm the transparency of the BIST.     

A BIST TPG for Low Power Dissipation and High Fault Coverage

This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can lead to performance degradation. Experimental results for ISCAS'89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS'89 benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the proposed BIST can be implemented with low area overhead.     

A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis

This paper presents a partitioned and embedded BIST technique for data path like circuits. The BIST scheme is defined at behavioral level for full optimization of both system and BIST modes during High Level Synthesis. Test time, area overhead and fault coverage are under the scope of the method. User-given constraints on fault coverage to achieve on data path operators and on test time are used to guide the BIST insertion technique towards the lowest area overhead solution.     

A BIST Circuit for DLL Fault Detection

A built-in-self-test (BIST) circuit for the test of a delay-locked loop circuit (DLL) is proposed. This circuit is based on a simple xnor logic gate and uncalibrated delay lines to sample the output of the xnor gate, so very little area overhead is introduced. In addition, no external stimulus is required for this BIST circuit, besides the “start test” signal. Fault simulation results show high fault coverage of structural faults, combined with some coverage of parametric variations.      

Design of the Input Matching Network of RF CMOS LNAs for Low-Power Operation

Optimum design of input matching network of CMOS low-noise amplifiers (LNAs) for low-power applications is discussed in this paper. This is done through an investigation of the effect of four different matching methodologies on the gain of radio frequency CMOS LNAs by means of compact analytical expressions. It is demonstrated that methods that convert the MOSFET's input impedance to 50 Omega for power matching are more suitable for low-power applications than methods that create a real 50-Omega resistance at the input of the LNA, such as source inductive degeneration. As it is analytically shown, this is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFET's input resistance. The impact of each matching methodology on the noise figure (NF) of the LNA is also discussed in detail and design guidelines for optimum gain-NF performance are developed using analytical models of MOSFET's noise parameters. It is demonstrated that all four methods could achieve very good NF values, provided that the size of active and passive components are chosen carefully based on the given guidelines. Measured results of two monolithic 5.7-GHz LNAs, designed and fabricated in a 0.18-mum CMOS technology, are also presented. The input matching networks of these LNAs are optimized for low-power operation based on the theory presented in this paper. It is experimentally shown that this optimization results in approximately 60% reduction in the dc power consumption and up to 300% improvement in the overall performance of the LNA when compared with some of the most recently published LNAs     

基于射频直放站的WCDMA网室内覆盖解决方案

描述了在WCDMA网络中,射频（RF）直放站是怎样延伸宏蜂窝不能解决的室内覆盖和容量问题,并且使用仿真结果显示了其效果。另外,还分析了直放站是怎样减少施主区域内上行链路的覆盖和容量,从而说明为了避免施主单元内的主要性能丢失,直放站的使用要经过仔细设计才能达到高容量高覆盖的效果。     

A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters

Specifications of Radio Frequency (RF) analog integrated circuits have increased strictly as their applications tend to be more complicated and high test cost demanding. This makes them very expensive due to an increased test time and to the use of sophisticated test equipment. Alternative test measures, extracted by means of Built-In Self Test (BIST) techniques, are useful approaches to replace standard specification-based tests. One way to evaluate the efficiency of the CUT measures at the design stage is by estimating the Test Escapes (T _E ) and the Yield Loss (Y _L ) at ppm level. Unfortunately, an important number of Monte Carlo simulations must be run in order to guarantee their accuracy. For certain types of circuits, this requires many months or even years to generate millions of circuits. To overcome this limitation, we present in this paper a new technique where a small number of simulations is sufficient to reach an important precision. This method is based on a classification using machine learning methods, such as SVM and Neural Networks based classifiers to determine pass/fail regions. The proposed approach requires a few number of simulations only to determine the region separating the process parameters generating good and faulty, or pass and fail circuits. Then only this region is needed to estimate the test metrics without running any additional simulation. The proposed methodology is illustrated for the evaluation of a filter BIST technique.     

Scalable Delay Fault BIST for Use with Low-Cost ATE

We present a BIST architecture based on a Multi-Input Signature Register (MISR) expanding single input vectors into sequences, which are used for testing of delay faults. Input vectors can be stored on-chip or in the ATE; in the latter case, a low speed tester can be employed though the sequences are applied at-speed to the block-under-test. The number of input vectors (and thus the area demand on-chip or ATE memory requirements) can be traded for the test application time.We propose several methods for generating input vectors, which differ in test application time, area requirements and algorithm run-time. As all of them require only a two-pattern test as input, IP cores can be handled by these methods.The block-under-test can be switched off for some amount of time between application of consecutive input vectors. We provide arguments why this approach may be the only way to meet thermal and power constraints. Furthermore, we demonstrate how the BIST scheme can use these cool-down breaks for re-configuration.     

Incorporating I DDQ Testing with BIST for Improved Coverage: An Experimental Study

In this paper we present an experimental study on the effectivenessof incorporating at-speed I _DDQ testing with traditionalBIST for improved test coverage. The high speed I _DDQtesting is conducted using the differential built-in on-chip current sensor(BICS) that we have recently developed. Two test chips were designed andfabricated implementing a CMOS version of the 74181 ALU chip. In copies ofthis circuit we included the capability of activating 45 differentrealistic CMOS faults: inter- and intra-layer shorts andopens. We examine the fault coverage of both Boolean (voltage) testing andI _DDQ testing for these realistic faults. An interestingfinding of our study is that I _DDQ testing also detectedseveral of the open faults. Moreover, these include precisely those openfaults for which two pattern voltage tests can get invalidated because oftransient switching states. Our results show that combining both Boolean andcurrent testing does enhance test coverage in a BIST environment.     

BIST/Digital-Compatible Testing of RF Devices Using Distortion Model Fitting

Testing of Radio Frequency (RF) circuits for nonlinearity specifications generally requires the use of multiple test measurements thereby contributing to increased test cost. Prior RF test methods have suffered from significant test calibration effort (training for supervised learners) when using compact tests or from increased test time due to direct specification measurement. On the other hand, due to aggressive technology scaling, there are plenty of digital transistors available that can be used to simplify testing of Analog/Mixed-Signal (AMS) and RF devices. In this paper, an RF test methodology is developed that: (a) allows RF devices to be tested for several distortion specifications using distortion model fitting algorithms in test time comparable to what can be achieved using supervised learning techniques while retaining the accuracy of direct specification measurement, (b) allows multiple RF specifications to be determined concurrently from a single data acquisition and (c) allows digital-compatible testing/BIST to be performed using digital testers or on-chip built in self-test (BIST) circuitry. With regard to (a), a key benefit is that no training of supervised learning algorithm is necessary. The proposed method based on distortion model fitting is shown to give excellent results across common RF performance metrics while providing ~10× improvements in test time compared to previous methods.     

On Non-Statistical Techniques for Fast Fault Coverage Estimation

We present fast, dynamic fault coverage estimation techniques for sequential circuits that achieve high degrees of accuracy and significant reductions in the number of injected faults and faulty-event evaluations. In the proposed techniques, we dynamically reduce injection of hyperactive faults as well as faults whose effects never propagate to a flip-flop or primary output. Suppression and over-specification of potential fault-effects are also investigated to reduce faulty-event evaluations. Experiments show that our methods give very accurate estimates with frequently greater speedups than the sampling techniques for most circuits. Most significantly, the proposed techniques can be combined with the sampling approach to obtain speedups comparable to small sample sizes and retain estimation accuracy of large fault samples.     

Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit

This paper presents a new low-cost RF BIST (Built-In Self-Test) scheme that is capable of measuring input impedance, gain, noise figure and input return loss for a low noise amplifier (LNA) in RF systems. The RF BIST technique requires an additional RF amplifier and two peak detectors, and its output is a DC voltage level. The BIST circuit is designed using 0.18 μm SiGe technology. The test technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the developed mathematical equations. Simulation results are presented for an LNA working at 5 GHz. Measurement data are compared with simulation results to validate the developed mathematical equations. The technique is simple and inexpensive. Jee-Youl Ryu received the BS and MS degrees in 1993 and 1997 from Pukyong National University in Electronic Engineering, Pusan, South Korea respectively. He also received the PhD degree in 2004 from Arizona State University in Electrical Engineering, Arizona, USA. He is currently with Samsung SDI Co., Ltd. His current research interests include RF IC design and testing, MMIC design and testing, analog IC design and testing, passives modeling, testing and analysis, and MEMS technology. Dr. Bruce Kim received the B.S.E.E. degree from the University of California, Irvine in 1981, the M.S. degree in electrical engineering from the University of Arizona in 1985, and the Ph.D. degree in electrical engineering from Georgia Institute of Technology in 1996. He was an Associate Professor at Arizona State University until 2005. Currently, he is an Associate Professor at The University of Alabama. His current research interests include RF IC testing, MEMS integration and VLSI circuits. He has been working on SiP testing technologies, package electrical modeling, and measurements of RF IC packages. Dr. Kim is a 1997 recipient of the National Science Foundation's CAREER Award and received the Meritorious Award from IEEE. He serves as the Chair of the IEEE CPMT Society TC-Electrical Test, associate editor of the IEEE Transactions on Advanced Packaging, associate editor of Design and Test of Computers, and program committee member of Electronic Components and Technology Conference. He is a senior member of IEEE.     

Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing

Test techniques for analog circuits characterize the input-output relationship based on coefficients of transfer function, polynomial expansion, wavelet transform, V-transform or Volterra series. However, these coefficients always suffer from errors due to measurement accuracy and noise. This paper presents closed form expressions for an upper bound on the defect level and a lower bound on fault coverage achievable in such analog circuit test methods. The computed bounds have been validated on several benchmark circuits. Further, application of these bounds to scalable RC ladder networks reveal a number of interesting characteristics. The approach adopted here is general and can be extended to find bounds on defect level and fault coverage in other component based test methods for linear circuits.     

应用于GPS接收机的宽带低噪声放大器

本文介绍了一种适用于GPS接收机的CMOS宽带低噪声放大器,带宽设计在1．16Hz-1．7GHz。采用源极电感负反馈结构,并在输入端加入了宽带匹配网络来扩展带宽,放大器提供30dB的增益,使用了两级放大,第二级采用了电流复用技术来节省功耗,最后一级使用了源极跟随器,用来阻抗匹配。采用TSMC55nmCMOS工艺,仿真结果表明,噪声系数小于1．3dB,S21大于29dB,S11小于-10dB,1．2V电源供电下功耗为20mW。     

基于分组网络结构NoC的BIST串扰测试方法

针对大规模NoC芯片设计中BIST测试时间长和消耗面积大的问题,提出一种测试NoC内switch间互连线串扰的BIST方法。对于互连线工作在1 GHz以下的大规模NoC,电容耦合是影响串扰的主要因素。通过并行测试结构,同时对几条受害线进行测试,有效减小了测试时间和电路面积。从理论角度对所提方法的测试时间和功率损耗进行了分析,以3×3 mesh结构的NoC为例,验证了所提方案和理论分析的正确性。     

A Generalized Fault Coverage Model for Linear Time-Invariant Systems

This paper proposes a fault coverage model for linear time-invariant (LTI) systems subject to uncertain input. A state-space representation, defined by the state-transition matrix, and the input matrix, is used to represent LTI system dynamic behavior. The uncertain input is considered to be unknown but bounded, where the bound is defined by an ellipsoid. The state-transition matrix, and the input matrix must be such that, for any possible input, the system dynamics meets its intended function, which can be defined by some performance requirements. These performance requirements constrain the system trajectories to some region of the state-space defined by a symmetrical polytope. When a fault occurs, the state-transition matrix, and the input matrix might be altered; and then, it is guaranteed the system survives the fault if all possible post-fault trajectories are fully contained in the region of the state-space defined by the performance requirements. This notion of guaranteed survivability is the basis to model (in the context of LTI systems) the concept of fault coverage, which is a probabilistic measure of the ability of the system to keep delivering its intended function after a fault. Analytical techniques to obtain estimates of the proposed fault coverage model are presented. To illustrate the application of the proposed model, two examples are discussed.     

Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits

We present a technique to statistically estimate path-delay fault coverage for synchronous sequential circuits. We perform fault-free simulation using a multivalue algebra and accumulate signal transition statistics, from which we calculate controllabilities of all signals and sensitization probabilities for all gates and flip-flops. We use a rated clock testing model where all time frames operate at the rated clock. We obtain path observabilities either by enumerating paths in the all-paths method, or by a nonenumerative method considering only the longest paths. The path-delay fault detectability is the product of observabilities of signals on paths from primary inputs (PIs) or pseudo-primary inputs (PPIs) to primary outputs (POs) or pseudo-primary outputs (PPOs), and the controllability on the corresponding PI or PPI. We use the optimistic update rule of Bose et al. for updating latches during logic simulation. When compared with exact fault simulation, the average absolute deviation in our statistical fault coverage estimation technique is 1.23% and the very worst absolute deviation was 6.59%. On average, our method accelerates delay fault coverage computation four times over an exact path delay fault simulator.     

基于真实信号强度的覆盖分析

随着城乡一体化的快速发展,城市大型建筑密度增大,乡镇建筑增多,导致部分场所信号覆盖减弱甚至无信号覆盖.已建成的专网通信系统无法满足不断变化的信号覆盖需求,迫切需要通过新增站点的方式进行扩容补盲.为掌控PDT系统信号覆盖情况,有效实现对PDT系统的扩容补盲,文章研究了一种信号覆盖检测技术,通过整合PDT系统的场强数据达到对信号覆盖的准确分析,为扩容补盲提供有力依据.     

Modeling Fault Coverage of Random Test Patterns

We present a new probabilistic fault coverage model that is accurate, simple, predictive, and easily integrated with the normal design flow of built-in self-test circuits. The parameters of the model are determined by fitting the fault simulation data obtained on an initial segment of the random test. A cost-based analysis finds the point at which to stop fault simulation, determine the parameters, and estimate fault coverage for longer test lengths. Experimental results on benchmark circuits demonstrate the effectiveness of this approach in making accurate predictions at a low computational cost. As compared to the cost of fault-simulating all the test vectors, the savings in computational time for larger circuits ranged from four to fourteen times. We also present an analysis of the mean and the variance of the fault coverage achieved by a random test of a given length. This analysis and simulation results demonstrate that while the mean coverage is determined by the distribution of the detectabilities of individual faults, the dual distribution of fault coverage of individual test vectors determines the variance.