The planar 6H-SiC ACCUFET: a new high-voltage power MOSFETstructure

A novel planar accumulation channel SiC MOSFET structure is reported in this paper. The problems of gate oxide rupture and poor channel conductance previously reported in SiC UMOSFETs are solved by using a buried P⁺ layer to shield the channel region. The fabricated 6H-SiC unterminated devices had a blocking voltage of 350 V with a specific on-resistance of 18 mΩ.cm² at room temperature for a gate bias of only 5 V. This measured specific on-resistance is within 2.5× of the value calculated for the epitaxial drift region (10¹⁶ cm^-3, 10 μm), which is capable of supporting 1500 V     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

An optimized bidirectional lightning surge protection semiconductordevice

This paper addresses the analysis of a bidirectional lightning surge protection power semiconductor device called the bidirectional breakover diode (BBD). The BBD has a high-speed response, high current capability, and low conduction and switching losses. The influence of the layout on the trigger and holding current values has been studied by means of two-dimensional (2-D) electrical simulations. The length of the peripheral N⁺ diffusion together with the location of the edge contact between the metallization and the P⁺/N⁺ diffusions are crucial in optimizing the trigger mechanism and the trigger and holding current values. The turn on of the inner cells has also been analyzed by numerical simulations, showing the effect of the central parasitic P⁺NP⁺ bipolar transistor at the initial phase of the turn on process. Experimental results have been obtained from fabricated 180-V BBD devices with holding current values in the range of 150-250 mA. The BBD surge protection capability has been corroborated by impulsive tests using a 10/1000 μs, 50 A, 1000 V, current pulse. In addition, transient losses have been monitored in order to improve the surge protection capability of the device. Finally, the static and dynamic BBD thermal behaviour has also been analyzed     

Strained-layer InGaAs-GaAs-AlGaAs lasers with monolithicallyintegrated photodiodes by selective-area MOCVD

Fabrication, design, and operation of strained layer, InGaAs-GaAs-AlGaAs lasers with monolithically integrated photodiodes fabricated by selective-area epitaxy are presented. Threshold currents as low as 8 mA (~300 A/cm²) were obtained for uncoated devices operating cw at room temperature. A responsivity of 71 μA/mW was obtained for a device with a photodiode etched facet angle of 3° and a photodiode bias of 0 V     

一种硅光电接收处理集成电路的技术研究

介绍了一种在硅衬底上集成光电二极管探测器和双极接收放大处理电路的单芯片光电集成电路OEIC。从理论上阐述了光电器件实现的原理;为实现光电探测二极管与单片双极集成电路的兼容,设计了光电探测器的专用结构,并研制了光电探测器的专用模型。对接收处理电路进行了模拟仿真和优化设计。建立了与双极工艺兼容的制作光电二极管探测器的专用工艺;采用该工艺,对光电器件进行了版图设计、工艺制作和测试研究,给出了初步试验的方法和结果。     

Backside-illuminated lateral PIN photodiode for CMOS image sensor on SOS substrate

In this paper, we propose a method to design charge-sensing elements for CMOS image sensor pixels on a silicon-on-sapphire (SOS) substrate. To address the low quantum efficiency problem due to very thin active film used, a backside illuminated lateral PIN photodiode on an SOS substrate is proposed and developed. It has the advantages of higher photo response with a PIN structure and improved optical transmission with a backside illumination through a transparent sapphire substrate. An active pixel sensor (APS) based on the PIN and backside illumination has been implemented in a commercially available SOS CMOS process. Acceptable sensitivity in optical conversion from the APS can be achieved, even with the ultrathin silicon film. The APS is demonstrated to function at 1.2 V, giving a dynamic range of 51 dB.     

Photon counting 1060-nm hybrid photomultiplier with high quantumefficiency

An ultra-low-noise, high-speed, hybrid photomultiplier tube sensitive from 900 to 1300 nm optical wavelength is described. The device, also known as an intensified photodiode (IPD), uses an active transferred electron (TE) photocathode with the quaternary In_.69 Ca_.31As_.67P_.33 photo-absorbing layer and a GaAs Schottky avalanche photodiode (SAPD) anode. The detector has a combined electron bombarded and avalanche gain of over 15000 which is sufficient to overcome preamplifier noise and provide high internal counting efficiency of approximately 85%. At an active cathode bias of 1.5 V the room temperature cathode dark count rate is 6.67×10⁵/s. Cooling reduces this substantially corresponding to a dark current activation energy almost equal to the bandgap of the In_.69Ca_.31As_.67P_.33 layer     

A selective epitaxial SiGe/Si planar photodetector for Si-basedOEIC's

A P-i-N SiGe/Si superlattice photodetector with a planar structure has been developed for Si-based opto-electronic integrated circuits. To make the planar structure, a novel SiGe/Si selective epitaxial growth technology which uses cold wall ultrahigh-vacuum/chemical vapor deposition has been newly developed. The P-i-N planar SiGe/Si photodetector has an undoped 30-Å Si_0.9Ge_0.1/320-Å Si, 30 periods, superlattice absorption layer, a 0.1-μm P-Si buffer layer, and a 0.2-μm P⁺-Si contact layer on a bonded silicon-on-insulator (η_ext). The bonded SOI is used to increase the external quantum efficiency (η_ext) of the photodetector. Moreover, a 63-μm deep/128-μm wide trench, to achieve simple and stable coupling of an optical fiber to the photodetector, is formed in the silicon chip. The P-i-N planar photodetector exhibits a high η_ext of 25-29% with a low dark current of 0.5 pA/μm² and a high-frequency photo response of 10.5 GHz at λ=0.98 μm     

Monolithic PIN-HEMT receiver with internal equaliser for long-wavelength fibre optic communications

An optical receiver, in which a GaInAs PIN photodiode, an AlInAs/GaInAs HEMT high impedance amplifier and even an equaliser were integrated monolithically on an InP substrate, has been fabricated. An optical sensitivity of -30.4 dBm was obtained at 1.2 Gbit/s and 1.3 mu m wavelength.<>     

A low dark current InGaAs/InP p-i-n photodiode with covered mesa structure

A new InGaAs p-i-n photodiode with a covered mesa (CM) structure having extremely low dark current characteristics and high yields has been developed. The device consists of only two epitaxial layers: n^--InP and n^--InGaAs, continuously grown on an n⁺-InP substrate by liquid-phase epitaxy. The InGaAs layer is chemically etched to be a tapered shape in order to make the fabrication process simple, as compared with a conventional mesa diode. The Zn diffusion to form a p-n junction is carried out without a diffusion mask such as Si3N4or SiO2, which induces damage due to the thermal stress. The tapered-shape InGaAs layer is covered with the Zn-diffused layer because a surface p-n junction occurring in an InGaAs region is leaky. Therefore, the surface p-n junction of the photodiode appears in the n^--InP layer, which has a bandgap about two times wider than the InGaAs. Finally, the passivation of the surface p-n junction is carried out with a Si3N4film formed by a plasma-assisted chemical vapor deposition. We have successfully achieved an extremely low dark current of 20 pA at a reverse bias voltage of 10 V and a high yield of 80 percent, by adopting the CM structure and the simple fabrication process.     

Basic module for an integrated optical phase difference measurementand correction system

A basic module for an integrated optical phase difference measurement and correction system was developed and fabricated in the AlGaAs-GaAs material system. The relative phase difference between two waveguides is measured using waveguide couplers to sample the optical field in each waveguide, a Y-junction interferometer with a small sinusoidal phase dither applied to one arm and a vertically integrated metal-semiconductor-metal detector. P⁺-n^-n⁺ phase modulators are used to control the phase difference between the waveguides. This implementation makes it possible to measure and correct the relative phase difference between adjacent waveguides using only a few percent of the optical power of each guide     

High current p/p+-diamond Schottky diode

Epitaxial p-type Schottky diodes have been fabricated on p⁺ -substrate. While the activation energy of the epitaxial layer conductivity is 390 meV, that of the substrate is only 50 meV. At forward bias the substrate conductivity dominates above 150°C, leading for a 5×10^-5 cm² area contact to a series resistance of 14 Ω at 150°C reducing to 8 Ω at 500°C. To our knowledge, this is the lowest series resistance reported so far for a diamond Schottky diode enabling extremely high current densities of 10³ A/cm and a current rectification ratio at ±2 V of 10⁵ making these diodes already attractive as high temperature rectifiers     

Two-dimensional numerical analysis of the minimum isolationdistance for GaAs digital large-scale integration

The minimum device isolation distance (L_min) applicable to GaAs digital large-scale integrated circuits is presented. The leakage current between two n-type layers formed in a semi-insulating (SI) substrate is simulated using a two-dimensional numerical model, and the results are compared with measurements. It is found that the leakage current is restricted by a potential hump formed by residual acceptors in the SI GaAs substrate when an isolating layer loses its compensated SI property. L_min is defined as the distance at which there is a leakage current of 1 mA for an isolating layer width of 1 cm. The calculated value of L_min at room temperature is 1.3 μm with a bias voltage of 2 V and an acceptor concentration of 10¹⁵ cm^-3. L_min decreases to 2/3 of this value when the temperature is reduced from 400 to 100 K, to 1/3 when the acceptor concentration is increased by one order, and to 2/3 when the bias voltage is reduced from 5 to 2 V     

The origin of channel currents associated with P+regions in silicon

The mechanism by which very large channel currents can result in P⁺N junctions or in PNP transistors having annular P⁺diffused channel-stop regions was studied in detail using experimental structures whose oxides were intentionally contaminated with sodium ions. It is shown that the onset of channel current flow corresponds quantitatively to the formation of an inversion layer over the P⁺region. Possible mechanisms by which carriers can be supplied to the inversion layer, thereby resulting in a channel current, are considered. It is demonstrated that the mechanism involves the breakdown of the field-induced junction formed between the inversion layer and the underlying P⁺region. The breakdown characteristics of this field-induced junction are considered experimentally in detail. It is shown that breakdown can proceed through either a tunneling or an avalanche mechanism depending on the surface concentration of the P⁺region, and that the breakdown characteristics of field-induced junctions are much like those of narrow alloyed silicon junctions studied earlier by Chynoweth et al.     

Amorphous silicon/silicon carbide superlattice avalanchephotodiodes

An a-Si/SiC:H superlattice avalanche photodiode (SAPD) has been successfully fabricated on an ITO/glass substrate by plasma-enhanced chemical vapor deposition. The room-temperature electron and hole impact ionization rates, α and β, have been determined for the a-Si/SiC:H superlattice structure by photocurrent multiplication measurements. The ratio α/β is 6.5 at a maximum electric field of 2.08×10⁵ V/cm. Avalanche multiplications in the superlattice layer yields an optical gain of 184 at a reverse bias V_R=20 V and an incident light power P_in=5 μW. An LED-SAPD photocouple exhibited a switching time of 4.5 μs at a load resistance R-1.8 kΩ     

Monolithic PIN/preamplifier circuit integrated on a GaAs substrate

An AlGaAs/GaAs PIN photodiode and a GaAs transimpedance amplifier including six FETs have been monolithically integrated on a GaAs substrate. A photoreceiver operation exhibiting an excellent linearity has been demonstrated. The photodiode sensitivity of 0.44 A/W and the amplifier transimpedance of 1.0 × l04 V/A have been determined from the measurement.     

A normal amorphous silicon-based separate absorption andmultiplication avalanche photodiode (SAMAPD) with very high optical gain

A normal amorphous silicon-based separate absorption and multiplication avalanche photodiode (SAMAPD) with very high optical gain of the avalanche photodiode has been developed successfully by plasma-enhanced chemical vapor deposition (PECVD). Based on experimental results, using undoped α-Si:H as avalanche layer material and α-Si_1-xGe_x:H as absorption layer material, the hole-injection (HI) type SAMAPD yields a very high optical gain of 686 at a reverse bias of 16 V under an incident light power of P_in =1 μW and has a rise time of 145 μs at a load resistance R=10 kΩ. Thus the amorphous silicon-based SAMAPD is a good candidate for the long-range optical communication applications     

An optical integrated circuit for time-division 2-D velocitymeasurement

An LiNbO₃ optical integrated circuit pigtailed with two single-mode fibres, which allows time-division two-dimensional velocity measurement, is discussed. To detect time-division multiplexed beat signals corresponding to velocity components v_X and v_γ of a moving object, a waveguide switch is integrated on a Z-propagating LiNbO₃ substrate of 28×7 mm² in addition to a waveguide interferometer with a frequency shifter. In the optical IC, either v_X or v_γ could be measured selectively with signal-to-noise ratio of 20 dB by driving an electronic gate placed after a photodiode in synchronization with the waveguide switch     

A high-packing density pixel with punchthrough read-out method foran HDTV interline CCD

A new pixel structure for a high-packing-density interline CCD is proposed, in which signal charges are read out from the photodiodes to the vertical CCD by a punchthrough mechanism. This read-out method makes it possible to reduce the depth of the VCCD channel and the second p-well by implanting these two layers after diffusion of the photodiode n layer. Spreading resistance measurements on dummy wafers show that the depths of these layers are 0.28 μm and 0.6 μm, respectively. Moreover, the photodiode n-layer is covered with a surface p⁺-layer, even at the transfer region. We describe the results of simulations and experiments on a test image sensor with pixel dimensions of 7.3 μm (H)×7.6 μm (V). From the experimental data, we estimate the characteristics of an image sensor with pixel dimension 5.0 μm (H)×5.2 μm (V). Such a device should have a maximum charge handling capability of 1.4×10⁵ electrons, a smear level of -88 dB, a sensitivity of 1.5×10³ electrons/Ix with a 30% fill factor, no image lag, and a low photodiode dark signal of less than 14 electrons at 60°C. These results indicate that an IL-CCD with a punchthrough readout structure is suitable for image sensors with a high pixel density such as 2/3 inch 2 million pixel image sensors for high-definition TV applications     

Light-soaking effects on a-Si:H photodiodes deposited by thelaminar-flow photo-CVD method

A 2/3-in, 2-Mpixel, STACK-CCD imaging sensor has been developed for HDTV solid-state imagers. A new a-Si:H photo-conversion layer, fabricated by the laminar-flow photo-chemical-vapor-deposition method, is overlaid on the vertical CCD scanning circuitry in the sensor. The photodegradation behavior of a-Si:H photodiodes is investigated in terms of dark-current density, electron μτ product and transient photocurrent. These properties are degraded as a result of light-induced defects in the a-Si:H layer. The Staeblar-Wronski constants, C_sw , are estimated to be 7.5×10^-7 at no voltage and 1.1×10^-7 at a reverse voltage of 6 V applied to the photodiode during light-soaking with an AM-1 lamp. The lifetime of the photodiode is determined by the degradation of the transient photocurrent, and is estimated to be about 2.2×10⁸ h for 1 lx light exposure. The lifetime is considered to be improved compared with that of previous-type photodiode reported before (1.5×10⁷ h for 1.5 lx light exposure) and clearly satisfies the needs for practical use of the device