A 2-V, 1.8-GHz BJT phase-locked loop

This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for ΣΔ fractional-N frequency-synthesis applications. Implemented in a 0.8-μm BiCMOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single -2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-voltage current-mode logic circuit configuration is used in most of the PLL's functional blocks to minimize phase jitter and achieve low-voltage operation. The multimodulus frequency divider is designed to support multibit digital modulation. The new phase and frequency detector and loop filter contain only npn transistors and resistors and thus achieve excellent resolution in phase comparison. When phase locked to a 53.4-MHz reference clock, the measured phase noise of the 16-GHz output is -91 dBc/Hz at 10-kHz offset. The frequency switching time from 1.677 to 1.797 GHz is 150 μs. Die size is 4300×4000 μm², including the passive loop filter     

A 1.5-V, 1.5-GHz CMOS low noise amplifier

A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-μm CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate noise in MOS devices     

2-GHz CMOS锁相环时钟发生器研究与设计

采用包含预充电通路,自适应偏置的压控振荡器,设计了一种2-GHz锁相环时钟发生器,并用0.18μm混合信号CMOS工艺实现.分析了环路参数对锁相环输出噪声影响,并对环路参数进行优化.1.8V电源电压下2GHz时钟的rms抖动,peak-peak抖动的测试结果分别为7.27ps,37.5ps,功耗为42mW.     

A 2-V amplitude-linear phase-locked loop

An amplitude-linear phase-locked loop which consumes less than 1 mW from a 2-V supply when operating at 100 kHz has been implemented in conventional 4-/spl mu/m CMOS. Obtaining reliable MOS analog operation at low voltages constrains the circuit approaches available and forces large device geometries. Sample-data techniques are applied to realize a low-voltage CMOS equivalent to the bipolar multiplier, and a voltage-controlled oscillator control buffer is used to define a linear frequency characteristic. The measured performance demonstrates suitability for portable tone-decoding and FM demodulation applications.     

A fully integrated 24-GHz phased-array transmitter in CMOS

This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to- ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area.     

A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-/spl mu/m CMOS process

A 1-V 24-GHz 17.5-mW fully integrated phase-locked loop employing a transformer-feedback voltage-controlled oscillator and a stacked divide-by-2 frequency divider for low voltage and low power is presented. Implemented in a 0.18-/spl mu/m CMOS process and operated at 24 GHz with a 1-V supply, the PLL measures in-band phase noise of -106.3 dBc at a frequency offset of 100 kHz and out-of-band phase noise of -119.1 dBc/Hz at a frequency offset of 10 MHz. The PLL dissipates 17.5 mW and occupies a core area of 0.55 mm/sup 2/.     

A fully integrated 0.5-5.5 GHz CMOS distributed amplifier

A fully integrated 0.5-5.5-GHz CMOS-distributed amplifier is presented. The amplifier is a four stage design fabricated in a standard 0.6-μm three-layer metal digital-CMOS process. The amplifier has a unity-gain cutoff frequency of 5.5 GHz, and a gain of 6.5 dB, with a gain flatness of ±1.2 dB over the 0.5-4 GHz band. Input and output are matched to 50 Ω, with worst-case return losses on the input and output of -7 and -10 dB, respectively. Power dissipation is 83.4 mW from a 3.0 V supply, input-referred 1-dB compression point varies from +6 dBm at 1 GHz to 8.8 dBm at 5 GHz. From a circuit standpoint, the fully integrated nature of the amplifier on the given substrate results in a heavily parasitic-laden design. Discussion emphasis is therefore placed on the practical design, modeling, and CAD optimization techniques used in the design process     

A 6-GHz integrated phase-locked loop using AlGaAs/GaAsheterojunction bipolar transistors

A fully integrated 6-GHz phase-locked-loop (PLL) fabricated using AlGaAs/GaAs heterojunction bipolar transistors (HBTs) is described. The PLL is intended for use in multigigabit-per-second clock recovery circuits for fiber-optic communication systems. The PLL circuit consists of a frequency quadrupling ring voltage-controlled oscillator (VCO), a balanced phase detector, and a lag-lead loop filter. The closed-loop bandwidth is approximately 150 MHz. The tracking range was measured to be greater than 750 MHz at zero steady-state phase error. The nonaided acquisition range is approximately 300 MHz. This circuit is the first monolithic HBT PLL and is the fastest yet reported using a digital output VCO. The minimum emitter area was 3 μm×10 μm with f_t=22 GHz and f_max=30 GHz for a bias current of 2 mA. The speed of the PLL can be doubled by using 1-μm×10-μm emitters in next-generation circuits. The chip occupies a die area of 2-mm×3-mm and dissipates 800 mW with a supply voltage of -8 V     

A 2-GHz 1.6-mW phase-locked loop

This paper describes the design of a 2 GHz 1.6 mW phase-locked loop (PLL) fabricated in an 18 GHz 0.6 μm BiCMOS technology. Employing cross-coupled delay elements and inductive peaking, the circuit merges the oscillator and the mixer into one stage to lower the power dissipation. An experimental prototype exhibits an r.m.s. jitter of 2.8 ps, a tracking range of 100 MHz, and a capture range of 70 MHz while operating from a 3 V supply. The phase noise in the locked condition is -115 dBc/Hz at 400 kHz offset     

A symmetrical 6-GHz fully integrated cascode coupling CMOS LC quadrature VCO

A fully symmetrical integrated quadrature LC oscillator with a wide tuning range of 1.2GHz is presented. The quadrature voltage-controlled oscillator (QVCO) is implemented using a symmetrical coupling method which has been used to produce the large tuning range with a low control voltage and to achieve good phase noise performance in 0.18/spl mu/m complementary metal oxide semiconductor technology. The measured phase noise at 1MHz offset from the center frequency (5.5GHz) is -115 dBc/Hz. The QVCO draws 3.2mA from a 1.8V supply. The equivalent phase error between I and Q signal was at most 0.5/spl deg/.     

A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers

An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13-mum CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is 4 dBm for a 0.1-MHz IF frequency and 10 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.     

一种3.3 V 2-GHz CMOS低噪声放大器

介绍了一个针对无线通讯应用的2-GHz低噪声放大器(LNA)的设计。该电路采用标准的0.6μm CMOS工艺，电源电压为3．3V，设计中使用了多个片上电感。对低噪声放大器的噪声进行了分析，模拟结果显示，该电路能提供18dB的正向增益(S21)及良好的反向隔离性能(S12为-44dB)，功耗为33．94mW，噪声系数为2．3dB，IIP3为-4．9dBm。     

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

A fully integrated 5-GHz low-power ESD-protected low-noise amplifier (LNA), designed and fabricated in a 90-nm RF CMOS technology, is presented. This 9.7-mW LNA features a 13.3-dB power gain at 5.5 GHz with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB. An on-chip inductor, added as "plug-and-play," i.e., without altering the original LNA design, is used as ESD protection for the RF pins to achieve sufficient ESD protection. The LNA has an ESD protection level up to 1.4 A transmission line pulse (TLP) current, corresponding to 2-kV Human Body Model (HBM) stress. Experimental results show that only minor RF performance degradation is observed by adding the inductor as a bi-directional ESD protection device to the reference LNA.     

0.5-V 5.6-GHz CMOS Receiver Subsystem

The building blocks of a 0.5-V receiver, including a receiver front-end and a low-pass filter (LPF), are fabricated using 0.18- $mu{hbox{m}}$ CMOS technology. At 5.6 GHz, the receiver front-end achieves a voltage gain of 17.1 dB and a noise figure of 8.7 dB, while dissipating at 19.4 mW. The fifth-order low-pass Chebyshev filter achieves a corner frequency of 2.6 MHz and an input-referred noise of 28.5 nV/sqrt (Hz) at 6.8 mW. The receiver front-end is further integrated with the LPFs to form a highly integrated receiver subsystem at ultra-low voltage.      

A 1.5-V high drive capability CMOS op-amp

A novel CMOS operational amplifier with a 1.5 V power supply is presented. It is based on a folded-mirror transconductance amplifier and a high-efficiency output stage. The amplifier achieves an open-loop gain and a gain-bandwidth product higher than 65 dB and 1 MHz, respectively. In addition, a 1 V peak-to-peak output voltage into a 500 Ω and 50 pF output load is provided with a total harmonic distortion of -77 dB. This performance was achieved using maximum aspect ratios of 120/1.2 and 360/1.2 for the NMOS and PMOS transistors, respectively, and a quiescent current as low as 60 μA for the driver transistors. The amplifier was implemented in a standard 1.2 μm CMOS process with threshold voltages around 0.8 V. It dissipates less than 300 μW     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

1.5-V CMOS exponential current generator

A new low-voltage CMOS exponential current generator is proposed in this work. MOS transistors in weak-inversion region and a master?Cslave technique for the temperature compensation were used. The circuit was fabricated with standard CMOS 0.35???m process using a single supply voltage of 1.5?V. Experimental results validate the theoretical analysis and verify the effectiveness of the proposed structure. A 40?dB range linearly in dB controlled output current with less than 1.5?dB linearity error was achieved. The structure features ±1 and ±3?dB deviations for ±10% supply voltage and 80°C temperature variations, respectively.