反应离子深刻蚀中硅/玻璃结构footing效应的实验研究

针对反应离子深刻蚀中硅/玻璃键合结构的footing效应问题,用实验方法进行了研究.通过2～4和0.01～0.03Ω·cm两种不同电导率的硅结构过刻蚀的对比,以及对50,20和5μm三组不同间隙高度的器件结构过刻蚀的对比,揭示了单晶硅结构的电导率及器件结构和玻璃衬底间隙高度对footing效应的影响.实验结果显示电导率为2～4Ω·cm的硅结构比电导率为0.01～0.03Ω·cm的硅结构footing效应严重;硅结构和玻璃衬底的间隙为5μm的比间隙为20和50μm的footing效应严重, 对这一现象的理论分析认为,被刻蚀的硅的电导率越高, 硅结构与玻璃衬底的间隙越大,footing效应越不明显.本文中不同电导率和不同间隙高度的实验对比结果可以为硅微传感器材料类型的选取和器件的优化设计提供参考.     

A micromachined, shadow-mask technology for the OMVPE fabrication of integrated optical structures

A micromachined, silicon shadow-mask technology is described which extends the capabilities of shadow-masked OMVPE for the fabrication of nonplanar micro-optical elements. The deep reactive ion etched (DRIE) shadow mask is inexpensive, reusable and produces smooth, nonplanar structures with precise control of position, shape and size. Direct fusion bonding of the mask to the substrate was found to be a reliable and reproducible method for attaching the mask to the substrate during growth. The DRIE shadow mask technology allows the deposition of microlenses with focal lengths out to 3 mm without the central flattening that was previously observed in shadow masked lenses grown under the epitaxial mask. We also describe novel applications of this technology in the fabrication of micromirrors and concentrically-variable Bragg reflectors, which should improve mode discrimination in large aperture VCSELs.     

A Laterally‐Driven Bistable Electromagnetic Microrelay

In this letter, a laterally‐driven bistable electromagnetic microrelay is designed, fabricated, and tested. The proposed microrelay consists of a pair of arch‐shaped leaf springs, a shuttle, and a contact bar made from silicon, low temperature oxide (LTO), and gold composite materials. Silicon‐on‐insulator wafers are used for electrical isolation and releasing of the moving microstructures. The high‐aspect‐ratio microstructures are fabricated using a deep reactive ion etching (DRIE) process. The tandem‐typed leaf springs with a silicon/gold composite layer enhance the mechanical performances while reducing the electrical resistance. A permanent magnet is attached at the bottom of the silicon substrate, resulting in the generation of an external magnetic field in the direction vertical to the surface of the silicon substrate. The leaf springs show bistable characteristics. The resistance of the pair of leaf springs was 7.5 Ω, and the contact resistance was 7.7 Ω. The relay was operated at ±0.12 V.     

Reliability of a Silicon Stacked Module for 3-D SiP Microsystem

Solder joint reliability of 3-D silicon carrier module were investigated with temperature cycle and drop impact test. Mechanical simulation was carried out to investigate the solder joint stress using finite element method (FEM), whose 3-D model was generated and solder fatigue model was used. According to the simulation results, the stress involved between flip chip and Si substrate was negligible but stress is more concentrated between Si carriers to printed circuit board (PCB) solder joint area. Test vehicles were fabricated using silicon fabrication processes such as DRIE, Cu via plating, SiO deposition, metal deposition, lithography, and dry or wet etching. After flip chip die and silicon substrate fabrication, they were assembled by flip chip bonding equipment and 3-D silicon stacked modules with three silicon substrate and flip chip dies were fabricated. Daisy chains were formed between flip chip dies and silicon substrate and resistance measurement was carried out with temperature cycle test (C, 2 cycles/h). The tested flip chip test vehicles passed T/C 5000 cycles and showed robust solder joint reliability without any underfill material. Drop test was also carried out by JEDEC standard method. More details on test vehicle fabrication and reliability test results would be presented in the paper.     

圆片级真空封装技术在MEMS陀螺中的应用

为维持MEMS硅微陀螺的真空度,利用两次硅-玻璃阳极键合和真空长期维持技术,实现了MEMS硅微陀螺的圆片级真空气密性封装。制作过程包括:先将硅和玻璃键合,在硅-玻璃衬底上采用DRIE工艺刻蚀出硅振动结构;再利用MEMS圆片级阳极键合工艺在10-5 mbar(1 mbar=100 Pa)真空环境中进行封装;最后利用吸气剂实现圆片的长期真空气密性。经测试,采用这种方式制作出的硅微陀螺键合界面均匀平整无气泡,漏率低于5.0×10-8 atm.cm3/s。对芯片进行陶瓷封装,静态下测试得出品质因数超过12 000,并对样品进行连续一年监测,性能稳定无变化。     

MOEMS chip-level optical fiber interconnect

A package design, fabrication process, and assembly process to hermetically seal the microstructure area of a microoptoelectromechanical system (MOEMS) at the chip level is presented and evaluated. The packaged chip is fabricated using the Bosch deep reactive ion etching (DRIE) process on silicon on insulator (SOI) substrates. The packaging structures are formed during the batch fabrication of the MOEMS device. A hermetic seal is formed via an indium solder ring around the perimeter of the MOEMS chip that span channels etched in the silicon for optical fibers. The seal is made between the device chip, metallized optical fibers, and a cap chip with a fluxless soldering process. The integrity of the package is evaluated through die shear, fiber pull, and highly accelerated life testing (HALT).     

A Micromachined Reconfigurable Metamaterial via Reconfiguration of Asymmetric Split‐Ring Resonators

A micromachined reconfigurable metamaterial is presented, whose unit cell consists of a pair of asymmetric split‐ring resonators (ASRRs); one is fixed to the substrate while the other is patterned on a movable frame. The reconfigurable metamaterial and the supporting structures (e.g., microactuators, anchors, supporting frames, etc.) are fabricated on a silicon‐on‐insulator wafer using deep reactive‐ion etching (DRIE). By adjusting the distance between the two ASRRs, the strength of dipole–dipole coupling can be tuned continuously using the micromachined actuators and this enables tailoring of the electromagnetic response. The reconfiguration of unit cells endows the micromachined reconfigurable metamaterials with unique merits such as electromagnetic response under normal incidence and wide tuning of resonant frequency (measured as 31% and 22% for transverse electric polarization and transverse magnetic polarization, respectively). The reconfiguration could also allow switching between the polarization‐dependent and polarization‐independent states. With these features, the micromachined reconfigurable metamaterials may find potential applications in transformation optics devices, sensors, intelligent detectors, tunable frequency‐selective surfaces, and spectral filters.     

Fabrication and application of metallic nano-cantilevers

A new approach was developed in this work to fabricate metallic nano-cantilevers using a one-mask process and a deep reactive ion etch (DRIE) technique. 40-nm-thick Al and 70-nm-thick Au cantilevers of lengths from 5 μm and widths in the range of 200-300 nm were fabricated on a silicon substrate. The silicon underneath the suspended beams was completely etched. Short Al nano-cantilevers were used to find local residual stress induced in rapid thermal oxidation and the oxidized spots according to the deflection profiles of the nano-cantilevers. The deflection profiles were determined with the aid of a scanning electron microscope (SEM). Compared with a single feedback in the existing cantilever-based static methods, i.e., the deflection of the open end of a cantilever, the whole deflection profile provides more information regarding the effect of surface stresses on a cantilever.     

Substrate interconnect technologies for 3-D MEMS packaging

We report the development of 3-dimensional silicon substrate interconnect technologies, specifically for reducing the package size of a MOSFET relay. The ability to interconnect multiple chips at different elevations on a single substrate can significantly improve device performance and size. We present the process development of through-hole interconnects fabricated using deep reactive ion etching (DRIE), with an emphasis on achieving positively tapered, smooth sidewalls to ease deposition of a seed layer for subsequent Cu electroplating. Gray-scale technology is integrated on the same substrate to provide smooth inclined surfaces between multiple vertical levels (>100 μm apart), enabling interconnection between the two levels via simple metal evaporation and lithography. The developments discussed for each technique may be used together or independently to address future packaging and integration needs.     

Silicon Micromachined W-Band Hybrid Coupler and Power Divider Using DRIE Technique

In this letter, a silicon micromachined W-band hybrid coupler and a power divider using deep-reactive ion etching (DRIE) technique are presented. They are designed in the H-plane of rectangular waveguide to utilize DRIE technique. The hybrid coupler adopts a ridged waveguide 90deg phase shifter and a joint waveguide. The power divider utilizes a T-shape configuration. The simulated and measured response of each circuit are presented in this letter where good agreement between them is achieved. Then, the measured combining efficiency is reported by cascading the power divider and the hybrid coupler.     

Warpage measurement of large area multitilted silicon substrates atvarious processing conditions

In order to find a low-cost solution for the future MCM-D packaging, a multitiling approach through the incorporation of several tiles on a large carrier substrate was studied. The multitiling format provides simultaneous processing of several small silicon wafers on a carrier glass with a coefficient of thermal expansion (CTE) comparable to that of silicon. The wafers (tiles) are attached to the carrier glass (pallet) using a low modulus adhesive that can be released at an elevated temperature (~450°C). The objective of this study is to develop materials and processes for a 12-in×12-in (300-mm×300-mm) large area substrate that can be scalable up to a 600-mm×600-mm format. The fabrication process begins with a carrier CTE matched Borofloat glass on which silicon wafers are attached using a low modulus adhesive. This composite structure is exposed to high temperature thin-film processes that are required for the MCM-D manufacturing. The warpage of these structures is a critical factor that determines the processability of the thin films in a manufacturing environment. Specimen warpage was obtained using the shadow moire technique. Warpage measurement was performed (i) on as-received glasses, (ii) glasses after polishing, and (iii) pallet assembly after tiling was completed. Although polishing reduced the overall warpage of the as-received pallets, the warpage of the tile and pallet assembly was increased after the adhesive was cured at 150°C. This paper discusses the warpage issues associated with various stages of processing of the proposed large area MCM-D structures     

基于MEMS工艺的硅基红外辐射源研制

利用微机电系统( MEMS)制造工艺制备出了一种硅基红外辐射源.该辐射源采用单晶硅为衬底,通过直流溅射沉积Pt/Ti薄膜,并利用深反应离子刻蚀与湿法腐蚀工艺制备隔离槽和释放支撑层.研究了支撑层厚度对红外辐射源辐射特性的影响.结果表明,随着支撑层厚度的减小,红外辐射源的调制驱动电压会降低.当支撑层厚度为1μm时,辐射源调...     

Moldless encapsulation for LED wafer level packaging using integrated DRIE trenches

This paper demonstrates a LED wafer level packaging process which employs the glob-top dispensing technique for encapsulation. The process utilizes the constraint effect introduced by the trenches to limit the spreading of encapsulant. This enables the geometry control of encapsulation. Several design and process parameters have been investigated. The study has considered the effect of the trench patterns. A 4-in. silicon wafer is fabricated with a pattern etched by the DRIE process. It serves as a substrate for an LED array employed in the present study. Using the wafer substrate and the glop-top dispensing technique, wafer level LED packaging incorporated with a moldless encapsulation process is realized.     

Deep reactive ion etching for lateral field emission devices

The authors describe the design, fabrication and testing of lateral field emission diodes utilizing the deep reactive ion etch (DRIE). Devices were fabricated on silicon-on-insulator (SOI) wafers of varied thickness, by etching the device silicon in the STS DRIE system in a single mask process. After subsequent oxidation sharpening and oxide removal, diodes were tested on a probing station under vacuum. A typical diode exhibited very high currents on the order of ~100 μA at 60 V, and turn-on voltage between 35 V and 40 V. The high electron current is emitted in such a diode by multiple sharp tips vertically spaced by 450 nm along the etched sidewall due to the pulsed nature of the DRIE process     

Reliability and failure in single crystal silicon MEMS devices

In single crystal silicon (SCSi) MST devices, crystalline imperfection is recognized to favor failure. Defects are introduced by DRIE etching which is commonly used in SCSi structuring. However, thermal annealing improves the crystal quality. High resolution X-ray diffraction methods such as the rocking curve method and reciprocal space mapping can monitor crystalline imperfection in SCSi devices. A DRIE etched SCSi structure was built to study the crystal strain profile in dependence of the SCSi deformation by applying a mechanical force. Our investigations also include the numerical simulation of deformations.     

A technology for high-performance single-crystal silicon-on-insulator transistors

A process for forming transistors and circuits in a thin single-crystal silicon film on a glass substrate is presented. The process involves the electrostatic bonding of a silicon wafer to glass and the subsequent thinning of the wafer using doping-sensitive etchants to retain only the epitaxial layer. NMOS transistors have shown channel mobilities of 640 cm²/V-s, while leakage currents have been measured at less than 10^-14A/µm.     

用于高产量MEMS以及3D互联技术的低成本深层反应离子刻蚀系统

新兴的 3D 互联技术以及高产量的 MEMS 应用需要成本低廉以及高产量的深层反应离子刻蚀系统。最优化的 Alcatel 深层反应离子刻蚀系统可以同时满足工艺以及硬件生产性能的高要求。这些都已经在典型刻蚀工艺上进行了研究, 包括斜面刻蚀、堆叠时的 CMOS 刻蚀侧壁角度、3D 高精度惯性传感器的良好控制的形貌、大面积刻蚀的打印机喷头和硅麦克风应用。优化的工艺参数意味着在刻蚀率, 刻蚀的深宽比, notch free 的工艺, 光滑度以及高精度控制各方面的显著提高。Alcatel AMS 200 “I-Productivity”DRIE 机台用于高产量的工艺同时也确保了生产参数如整机效率的提高以及使用成本的降低, 这是通过机台的无可替代的硬件以及工艺方案实现的。     

DRIE技术加工W波段行波管折叠波导慢波结构的研究

简要介绍了利用深反应离子刻蚀制作折叠波导慢波结构的现状及制作的工艺流程。对深反应离子刻蚀掩膜制作即光刻工艺,以及折叠波导慢波结构的深刻加工进行了深入的研究。详细分析了各光刻工艺对光刻胶图形的影响,尤其是前烘对光刻胶图像侧壁垂直度的影响;在深反应离子刻蚀中,还详细分析了刻蚀时间、下电极功率以及刻蚀气体气压对刻蚀结果的影响。经参数优化后获得最佳工艺参数,并制作出带有电子注通道的W波段折叠波导慢波结构,慢波结构深为946μm,侧壁垂直度为91°,电子注通道深为225μm,侧壁垂直度为90°。     

Fabrication of Precise Die Edges for Micro-Optical and MEMS Applications

A method for fabricating precise silicon die edges aligned to a precision of 0.5 mum to the features on the front side of the die without damaging these features is described in this paper. A two step die edge fabrication process with die edge defined by silicon DRIE on the front side of the die and edge grinding on the backside of the die was developed. The features on the front-side of the die close to the edge are not mechanically damaged by this technique. Test structure design and fabrication to measure the precision of die edge with respect to the features on the front side is discussed. Die cleaning process using a protective coating deposited prior to the sawing and grinding processes is also presented.     

基于MEMS技术的微型气相色谱柱的研制

描述了一种采用MEMS技术加工的微型气相色谱柱,这种色谱柱采用深刻蚀技术加工出色谱通道,再与Pyrex7740玻璃进行键合密封。色谱柱全长6m,色谱通道截面为矩形(宽100μm,深100μm),针对苯和甲苯的混合气进行了分离试验,理论塔板数达到了4800,分离时间为185s。