蒸栅前退火与AlGaN/GaN HEMT噪声性能关系的研究

为进一步提高AlGaN/GaN HEMT的噪声性能,如何才能降低其相对较高的栅漏电是较为棘手的问题之一。作者通过实验证明了可降低其噪声的器件制作过程中的一项工艺步骤。两个AlGaN/GaN样片在刻蚀栅槽后被分别不同处理,一个蒸发栅金属前退火,另一个直接蒸发栅金属。比较二者的Ig－Vgd直流特性曲线,可发现蒸栅前进行退火处理可大大降低栅漏电。数据分析表明：退火可提高肖特基势垒;刻蚀过程中的等离子体可引发损伤,退火导致的损伤消除是栅漏电减小的主要原因。作者引用了一个噪声模型来证明蒸栅前退火确实可以有效地提高AlGaN/GaN HEMT的噪声性能。     

背栅应力对LOCOS隔离的SOI器件背栅阈值电压的影响

LOCOS隔离的SOI器件的性能强烈依赖于其背栅特性,而背栅应力会影响到背栅的特性。常温下在SOI器件的背栅上施加大电压并持续30秒以上可以显著改变背栅的阈值电压。这种改变是稳定的和时不变的。对NMOS加正的背栅压和对PMOS加负的背栅压都可以提高其背栅阈值电压。实验结果表明沿着硅岛的边缘有一条从源到漏的寄生漏电通道,而且将栅,源,漏接地并在背栅上加大的偏压可以强烈影响漏电通道。因此我们可以得到结论,背栅应力会影响与漏电流直接相关的背栅阈值电压。     

高栅压下超薄栅nMOSFET的RTS噪声

在深入研究SMIC 90nm工艺1.4nm栅厚度nMOS器件RTS噪声时域特性的基础上,提出了该类噪声电子隧穿栅介质的物理起源,并对高栅压下RTS噪声机理作了深入阐述.结合IMEC和TSMC的研究,建立了栅压与RTS噪声时间参数的物理模型,实验结果和模型模拟结果的一致说明了模型的有效性.该研究为边界陷阱动力学和此类器件可靠性提供了新的研究手段.     

4H-SiC MESFET结构与直流特性研究

运用二维器件模拟器ISETCAD对4H-SiCMESFET不同结构的直流特性进行了模拟,重点考虑表面陷阱对直流特性的影响。与凹栅结构相比,埋栅结构的器件降低了表面陷阱对电流的影响,饱和漏电流提高了37%,而且阈值电压的绝对值增大、跨导升高,对提高4H-SiCMES-FET器件的输出功率起到一定的作用。     

钝化处理对CdZnTe Γ射线探测器漏电流的影响

表面漏电流引起的噪声会限制CdZnTe探测器的性能 ,尤其对于共面栅探测器 ,漏电噪声的大小与器件的电极设计和表面处理工艺密切相关。研究了化学钝化的工艺条件对CdZnTe表面状态的影响 ,借助原子力显微镜、电子探针和微电流测试仪等手段 ,研究了CZT表面形貌、组成等特性与器件电学性能之间的关系 ,有效地降低了器件的表面漏电流     

HfO2高K栅介质薄膜的电学特性研究

研究了高 K(高介电常数 )栅介质 Hf O2 薄膜的制备工艺 ,制备了有效氧化层厚度为 2 .9nm的超薄MOS电容。对电容的电学特性如 C-V特性 ,I-V特性 ,击穿特性进行了测试。实验结果显示 :Hf O2 栅介质电容具有良好的 C-V特性 ,较低的漏电流和较高的击穿电压。因此 ,Hf O2 栅介质可能成为 Si O2 栅介质的替代物。     

堆叠栅介质MOS器件栅极漏电流的计算模型

采用顺序隧穿理论和传输哈密顿方法并考虑沟道表面量子化效应,建立了高介电常数堆叠栅介质MOS器件栅极漏电流的顺序隧穿模型。利用该模型数值,研究了Si3N4/SiO2、Al2O3/SiO2、HfO2/SiO2和La2O3/SiO2四种堆叠栅介质结构MOS器件的栅极漏电流随栅极电压和等效氧化层厚度变化的关系。依据计算结果,讨论了堆叠栅介质MOS器件按比例缩小的前景。     

深亚微米器件中氧空位对栅漏电流的影响

描述了影响硅器件性能的二氧化硅中的缺陷,介绍了氧空位的概念,分析计算了随机氧空位对栅漏电流的影响.模拟结果表明:当氧空位在栅氧化层中随机变化时,引起的栅漏电流的变化是在一定值附近上下波动;栅漏电流随氧化层厚度的减小而增大,因此,在小尺寸器件中,必须考虑氧空位对栅漏电流的影响.但当厚度在特定值及特定电场下时,单个氧空位引起的栅漏电流增加可以忽略.     

3—6nm超薄SiO_2栅介质的特性

采用栅氧化前硅表面在 H2 SO4/ H2 O2 中形成化学氧化层方法和氮气稀释氧化制备出 3.2、 4和 6 nm的 Si O2超薄栅介质 ,并研究了其特性 .实验结果表明 ,恒流应力下 3.2和 4nm栅介质发生软击穿现象 .随着栅介质减薄 ,永久击穿电场强度增加 ,但恒流应力下软击穿电荷下降 .软击穿后栅介质低场漏电流无规则增大 .研究还表明 ,用软击穿电荷分布计算超薄栅介质有效缺陷密度比用永久击穿场强分布计算的要大 .在探讨软击穿和永久击穿机理的基础上解释了实验结果     

干法刻蚀和氢等离子体处理制备增强型p-GaN栅AlGaN/GaN HEMT特性

增强型p-GaN栅AlGaN/GaN高电子迁移率晶体管(HEMT)的栅与源漏之间的沟道特性对器件性能具有重要的影响.在同一晶圆衬底上,采用干法刻蚀和氢等离子体处理栅与源、漏之间的p-GaN,制备增强型p-GaN栅AlGaN/GaN HEMT.对器件静态、动态特性和栅极漏电特性进行研究,采用两种方法制备的器件均具有较高的击穿电压(＞850 V@10 μA/mm).通过氢等离子体处理制备的器件的方块电阻较大,导致输出电流密度较低,在动态特性和栅极漏电方面具有明显的优势,氢等离子体处理技术提高了界面态的缺陷激活能,从而实现了较低的栅极反向漏电.     

Noise model of gate-leakage current in ultrathin oxide MOSFETs

A physics-based analytical model of the gate-leakage current noise in ultrathin gate oxide MOSFETs is presented. The noise model is based on an inelastic trap-assisted tunneling transport. We employ the barrier height fluctuation model and the Lorentzian-modulated shot noise of the gate-leakage current stemming from the two-dimensional electron gas channel to explain the excess noise behavior. The excess noise can be interpreted as the sum of 1/f/sup /spl gamma// noise and the Lorentzian-modulated shot noise. Trap-related processes are the most likely cause of excess current noise because slow traps in the oxide can result in low-frequency dissipation in the conductance of oxides and fast traps can produce the Lorentzian-modulated shot noise associated with generation-recombination process at higher frequencies. In order to verify the proposed noise model, the simulation results are compared with experimental data, and excellent agreement is observed.     

Accurate evaluation of mobility in high gate-leakage-current MOSFETs by using a transmission-line model

The effect of high gate-leakage current on the accuracy of mobility evaluation was investigated. This investigation showed that a high gate leakage current makes it difficult to measure the mobility accurately in the case of using a conventional equivalent circuit with lumped circuit elements. To measure the mobility accurately, the authors therefore used a transmission-line model. Its validity was experimentally confirmed by using the capacitance-frequency characteristic of the gate of MOSFETs. The transmission-line model shows that a high gate-leakage current induces a voltage distribution in the channel, which causes a serious error in the mobility evaluation. Accordingly, a precision parameter, which clarifies the relation between channel length and measurement error, was defined. This parameter was then used to define a criterion for channel length for accurately measuring mobility. The channel-length criterion was used to successfully evaluate the mobility of n-MOSFETs with gate dielectrics of 1.4-nm-thick oxynitride (SiON).     

Gate current dependence of low-frequency noise in GaAs MESFET'S

Characteristics of low-frequency noise generators in ion-implanted GaAs MESFET's on semi-insulating substrates were determined using measurements at 300°K and 105°K in the frequency range of 10Hz to 50KHz. The noise magnitude shows strong dependence on gate leakage current and its spectral response is a combination of both 1/f and 1/f²types. The high-field gate-leakage current dependence of excess LF noise suggests the tunneling of electrons into deep level defects and their subsequent thermal emission to the conduction band.     

Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Reduction in static-power dissipation (gate leakage) by using nitrided oxides comes at the expense of enhanced negative-bias temperature instability (NBTI). Therefore, determining the nitrogen content in gate oxides that can simultaneously optimize gate-leakage and NBTI degradation is a problem of significant technological relevance. In this paper, we experimentally and theoretically analyze wide range of gate-leakage and NBTI stress data from a variety of plasma-oxynitride gate dielectric devices to establish an optimization scheme for gate-leakage and NBTI degradation. Calculating electric fields and leakage current both numerically and using simple analytical expressions, we demonstrate a design diagram for arbitrary nitrogen concentration and effective oxide thickness that may be used for process and IC design.     

Plasma charging damage on MOS devices with gate insulator ofhigh-dielectric constant material

Plasma charging effects on the gate insulator of high-dielectric constant (k) material in MOS devices deserve to be investigated because of different trap-assisted conduction mechanisms. Plasma-induced degradation in gate-leakage current and time to breakdown is clearly observed in this work. MOS device with Si₃N₄ film seems to have smaller degradation of gate-leakage current while it suffers shorter time to breakdown as compared to Ta₂O₅ samples. For devices with Ta₂O₅ film, a larger physical thickness suffers more reliability degradation from plasma charging damage because of the richer traps. Thus, a smaller physical thickness of high-k dielectric film is favorable for sub-micron MOS devices of ULSI application     

Current Collapse and High-Electric-Field Reliability of Unpassivated GaN/AlGaN/GaN HEMTs

Long-term ON-state and OFF-state high-electric-field stress results are presented for unpassivated GaN/AlGaN/GaN high-electron-mobility transistors on SiC substrates. Because of the thin GaN cap layer, devices show minimal current-collapse effects prior to high-electric-field stress, despite the fact that they are not passivated. This comes at the price of a relatively high gate-leakage current. Under the assumption that donor-like electron traps are present within the GaN cap, two-dimensional numerical device simulations provide an explanation for the influence of the GaN cap layer on current collapse and for the correlation between the latter and the gate-leakage current. Both ON-state and OFF-state stresses produce simultaneous current-collapse increase and gate-leakage-current decrease, which can be interpreted to be the result of gate-drain surface degradation and reduced gate electron injection. This study shows that although the thin GaN cap layer is effective in suppressing surface-related dispersion effects in virgin devices, it does not, per se, protect the device from high-electric-field degradation, and it should, to this aim, be adopted in conjunction with other technological solutions like surface passivation, prepassivation surface treatments, and/or field-plate gate     

Design of a high-performance PJFET for the input stage of an integrated operational amplifier

With Shockley's approximate-channel theory and TCAD tools, a high-voltage, ultra-shallow junction PJFET for the input stage of an integrated operational amplifier (OPA) was realized. The high-performance PJFET device was developed in the Bi-FET process technology. The measured specifications are as follows. The top-gate junction depth is about 0.1 μm, the gate-leakage current is less than 5 pA, the breakdown voltage is more than 80 V, and the pinch-off voltage is optional between 0.8 and 2.0 V. The device and its Bi-FET process technology were used to design and process a high input-impedance integrated OPA. The measured results show that the OPA has a bias current of less than 50 pA, voltage noise of less than 50 nV/Hz~(1/2), and current noise of less than 0.05 pA/Hz~(1/2).     

A model for the drain voltage and gate voltage dependence of the current fluctuation spectrum of unsaturated JFET's

From the standpoint of the number fluctuation model of the generation-recombination noise and 1/fnoise, a model for the drain and gate voltage dependences of the current fluctuation spectrum of an unsaturated JFET ot MESFET can be established. The derived formula can explain the various experimental results, especially the square-law dependence of the drain voltage throughout almost all of the unsaturated region, and the increasing characteristic of the current fluctuation spectrum with increasing reverse gate voltage. It can also explain the dependence of drain current fluctuation on the device geometric parameters, and finally, it points out that Hooge's expression for the spectral intensity of the current fluctuation can be valid only in the linear region of the device.     

Investigation of NiSi and TiSi as CMOS gate materials

NiSi is a promising new candidate for CMOS gate metal material because its workfunction can be adjusted by the implantation of dopants into the silicon before silicidation. In this report, NiSi and TiSi are studied, and the work functions of each are found to be adjustable over a wider range than previously published. This range covers the work function values required to achieve correct threshold voltages (V/sub t/) for both deep-scaled bulk CMOS and fully depleted, silicon-on-insulator MOSFETs. The influence of these silicides on the gate oxide and interface quality is also examined thoroughly via measurements of capacitance, minority carrier mobility, and gate-leakage current. While no degradation of the interface is observed with NiSi gates, TiSi gates generate interface traps and significantly degrade transistor device performance. With all the merits of a metal gate and no apparent degradation of interface quality, NiSi can be integrated with minor modification into a standard CMOS process and is a promising gate metal material for future CMOS technology generations.     

Microwave-Rectification RFI Response in Field-Effect Transistors

This paper discusses the rectification of microwave energy in low-medium frequency feld-effect transistors (FET's) and develops a small-signal model for RHI noise analysis in low-frequency linear circuitry. The modeling procedure centers on a Taylor series expansion of the gate voltage-drain current characteristic which shows a small increase in drain current due to a nicrowave voltage at the gate. The increase in drain current is proportional to the variation in transconductance with gate voltage, and the square of the microwave voltage. Analysis of the microwave power in the transistor shows that critical parameters in determnination of the sensitivity are the gate capacitance and the real part ofthe device input impedance, which ultimately is limited by the parasitic resistance between the active channel and contacts.