GF(2m)域上快速模乘处理局部并行结构

在分析EC上点乘操作的基础上,构造了MSB方式下局部并行线性systolic结构的模乘递推形式,设计了具体的单元结构,给出了性能分析和模拟比较结果。实验证明MSB方式下局部并行、域多项式可变的阵列结构能适应多种EC上模乘,实现灵活、高速的模乘处理,而局部并行、固定域多项式结构能在较优的硬件代价下高效实现特定EC上模乘,有效提高GF(2m)上ECC算法的性能。     

一种通用GF(2m)模乘加速器的快速实现

在椭圆曲线密码体制(ECC)中,有限域GF(2m)上模乘运算是最基本的运算,加速模乘运算是提高ECC算法性能的关键。针对不同不可约多项式广泛应用的现状,提出了一种通用GF(2m)模乘加速器设计方案。该加速器通过指令调度的方式,能快捷地完成有限域上模乘运算。实现结果表明,该设计完全适用于智能卡等应用要求。     

传输触发体系结构指导下的ECC整体算法处理器设计

以传输触发体系结构(TTA)为基础,为支持大数运算扩展寄存器堆,并增加模乘单元以加速模乘操作,提出一种ECC整体算法处理器.该处理器具有如下特点: ①利用TTA工具链可快速开发出ECC公钥系统;②模乘单元将以基数为处理字长的高基数Montgomery算法与行共享流水结构相结合,具有良好的可扩展性;③流水站实现矢量乘操作,并同时支持GF(p)和GF(2n)双有限域;④通过调整总线宽度和流水站个数,可满足不同性能/面积要求.在0.18μm CMOS工艺下,其高性能和紧缩面积版本的电路等效门数分别为117.4×103和40.6×103,可分别在0.87ms和7.83ms内完成一次GF(p)或GF(2n)上的192位EC标量乘运算.     

TTA-EC:一种基于传输触发体系结构的ECC整体算法处理器

以传输触发体系结构(TTA)为基础,为支持大数运算扩展寄存器堆,增加模乘单元以加速模乘操作,提出一种ECC整体算法处理器TTA-EC.该处理器具有如下特点:(1)利用TTA工具链,可快速开发出基于TTA-EC的完整ECC公钥系统;(2)模乘单元将以基数为处理字长的高基数Montgomery算法与行共享流水结构相结合,具有良好的可扩展性;(3)流水单元实现矢量乘操作,并同时支持GF(p)和GF(2n)双有限域;(4)通过调整总线宽度和流水单元个数,可满足不同性能/面积约束.在0.18μm 1P6M CMOS工艺下,其高性能和紧缩面积版本的规模分别为117.4K和40.6K,可分别在0.87ms和7.83ms内完成一次GF(p)或GF(2n)上的192位EC标量乘运算,峰值功耗分别为242.1mW和28.5mW.     

基于Kogge-Stone加法器改进的双域模乘器

模乘作为椭圆曲线公钥密码算法的核心运算,调用频率最高,提高其运算速度对于提高椭圆曲线密码处理器的性能具有重要意义。基于Kogge-Stone加法结构,结合可重构技术,实现一种能够同时支持素数域GF(p)和二元域GF(2~m)上模乘运算的双域模乘器,并对模块进行合理复用,节省硬件资源。用Verilog VHDL语言对该模乘器进行RTL级描述,并采用0.18μm CMOS工艺标准单元库进行逻辑综合。实验结果表明,该双域模乘器的最大时钟频率为476 MHz,占用硬件资源66 518 gates,实现256位的模乘运算仅需0.27μs。     

可编程可伸缩的双域模乘加器研究与设计

模乘和模加减作为椭圆曲线公钥体制的核心运算,在ECC算法实现过程中使用频率极高。如何高效率、低成本地实现模乘模加减是当前的一个研究热点。针对FIOS类型Montgomery模乘算法和模加减算法展开研究,结合可重构设计技术,并对算法进行流水线切割,设计实现了一种能够同时支持GF(p)和GF(2n)两种有限域运算、长度可伸缩的模乘加器。最后对设计的模乘加器用Verilog HDL进行描述,采用综合工具在CMOS 0.18μm typical工艺库下综合。实验结果表明,该模乘加器的最大时钟频率为230 MHz,不仅在运算速度和电路面积上具有一定优势,而且可以灵活地实现运算长度伸缩。     

GF(2n)域上基于ONB的ECC运算单元设计与实现

分析了GF(2n)域上基于优化正规基(ONB)的椭圆曲线的运算法则，讨论了域划分对芯片实现速度和硬件资源占用二者的影响，设计了一种串-并行结构的基于ONB的高速有限域运算单元，用于完成GF(2191)域上基于ONB的ECC芯片实现，在50MHz时钟下，GF(2191)域上的点乘运算速度平均为981次/s。     

椭圆曲线密码算法的硬件设计与实现

本文重点介绍了椭圆曲线密码体制(ECC)的实施过程以及用到的相关算法和优化方案。文中利用大数模运算硬件实现中常用的蒙哥马利(Montgomery)算法和心缩(Systolic)算法实现了模乘运算,并在此基础上用Ver- ilog硬件描述语言实现了ECC最核心的点乘运算。     

基于FIOS类型的Montgomery双域模乘器设计

针对FIOS类型的Montgomery模乘扩展算法的比特级-字级和字级-字级的两种实现形式进行研究,设计多处理单元的流水线组织结构实现算法,并对模乘器进行双有限域统一结构设计,使之能够同时支持两个有限域GF(p)和GF(2n)上的运算。最后对设计的两种模乘器用Verilog硬件描述语言进行代码描述,采用Synopsys公司的Design Compiler在Artisan SIMC 0.18μm typical工艺库下综合。实验结果表明,该模乘器不仅在运算速度和电路面积方面各具有优势,而且具有运算长度可变的灵活性。     

并行设计的高性能随机椭圆曲线加密协处理器

为加速椭圆曲线加密的运算,本文提出了一种新的并行设计的椭圆曲线加密处理器结构。该处理器采用的模运算单元的特点是含有两个模乘、一个模加和一个模平方模块。两个模乘可以并行运算,而且在模乘运算的同时可并行完成模加或模平方的运算。Xilinx公司的VirtexE XCV2600 FPGA硬件实现结果表明,完成有限域GF(2163)上任意椭圆曲线上的一次标量乘的全部运算只需3064个时钟,时间消耗为31.17μs,资源消耗为3994个寄存器和15527个查找表,适合高性能椭圆曲线加密应用的要求。     

Applying systolic multiplication–inversion architectures based on modified extended Euclidean algorithm for GF(2) in elliptic curve cryptography

Elliptic curve cryptography is a very promising cryptographic method offering the same security level as traditional public key cryptosystems (RSA, El Gamal) but with considerably smaller key lengths. However, the computational complexity and hardware resources of an elliptic curve cryptosystem are very high and depend on the efficient design of EC point operations and especially point multiplication. Those operations, using the elliptic curve group law, can be analyzed in operations of the underlined GF(2^k) Field. Three basic GF(2^k) Field operations exist, addition–subtraction, multiplication and inversion–division. In this paper, we propose an optimized inversion algorithm that can be applied very well in hardware avoiding well known inversion problems. Additionally, we propose a modified version of this algorithm that apart from inversion can perform multiplication using the architectural structure of inversion. We design two architectures that use those algorithms, a two-dimensional multiplication/inversion systolic architecture and an one-dimensional multiplication/inversion systolic architecture. Based on either one of those proposed architectures a GF(2^k) arithmetic unit is also designed and used in a EC arithmetic unit that can perform all EC point operations required for EC cryptography. The EC arithmetic unit’s design methodology is proposed and analyzed and the effects of utilizing the one or two-dimensional multiplication/inversion systolic architecture are considered. The performance of the system in all its design steps is analyzed and comparisons are made with other known designs. We manage to design a GF(2^k) arithmetic unit that has the space and time complexity of an inverter but can perform all GF(2^k) operations and we show that this architecture can apply very well to an EC arithmetic unit required in elliptic curve cryptography.     

基于高基阵列乘法器的高速模乘单元设计与实现

蒙哥马利模乘算法是最适合硬件实现的模乘算法,被应用在RSA密码和ECC密码的协处理器设计中.目前性能最高的是高基蒙哥马利模乘算法,分析了高基蒙哥马利算法的实现,提出了一种新的基于高基阵列乘法器的Montgomery模乘高速硬件实现结构,基于这种结构位长为n的比特模乘仅需要约n/w+6个时钟周期,该结构设计的电路只与最小单元有关,在硬件实现时可以大大提高频率,并提高设计的性能,可以设计高速的RSA和椭圆曲线密码大规模集成电路.     

分割式Montgomery模乘运算的线性高基心动阵列新结构

本文基于提高并行性、加速模乘的思想，利用分割操作数的方法，提出了分割式Montgomery模乘算法（PMMM），并且基于C．D.Walter发明的心动阵列结构，提出了新的线性高基心动阵列模乘结构，较好地实现了PMMM。对于基r（r=2^w）的n位模乘运算，Walter使用（n＋1）（n＋2）个PF来实现Montgomery模乘，我们用n＋2个PE实现Montgomery模乘，最大并行性为Walter的2倍。将此结构应用于模幂运算，仅需一次预计算便可使得非平方模乘的输入输出延迟为walter中的1/2，且平方模乘延迟与其相当，从而提高了模幂的运算速度。当然，考虑到对速度和硬件资源的不同需求，我们也给出了使用n/2＋1个PE来计算模乘、模幂的实现算法，并做出了相应的数据分析。     

Unified Parallel Systolic Multiplier Over GF（2^m）

In general, there are three popular basis representations, standard （canonical, polynomial） basis, normal basis, and dual basis, for representing elements in GF（2^m）. Various basis representations have their distinct advantages and have their different associated multiplication architectures. In this paper, we will present a unified systolic multiplication architecture, by employing Hankel matrix-vector multiplication, for various basis representations. For various element representation in GF（2^m）, we will show that various basis multiplications can be performed by Hankel matrix-vector multiplications. A comparison with existing and similar structures has shown that time complexities. the proposed architectures perform well both in space and     

Design of Montgomery Multiplication Architecture Based on Programmable Cellular Automata

This study presents a Montgomery multiplication architecture that uses an irreducible all one polynomial (AOP) in GF(2 ^m ) based on a programmable cellular automata (PCA). The proposed architecture has the advantage of high regularity and a reduced latency based on combining the characteristics of the irreducible AOP and PCA. The proposed architecture can be used to implement modular exponentiation, division, and inversion architectures.     

Low-Complexity Bit-Parallel Multiplier over GF(2$^m$) Using Dual Basis Representation

Recently, cryptographic applications based on finite fields have attracted much attention. The most demanding finite field arithmetic operation is multiplication. This investigation proposes a new multiplication algorithm over GF（2^m） using the dual basis representation. Based on the proposed algorithm, a parallel-in parallel-out systolic multiplier is presented, The architecture is optimized in order to minimize the silicon covered area （transistor count）. The experimental results reveal that the proposed bit-parallel multiplier saves about 65% space complexity and 33% time complexity as compared to the traditional multipliers for a general polynomial and dual basis of GF（2^m）.     

Montgomery exponent architecture based on programmable cellular automata

This study presents an efficient exponent architecture for public-key cryptosystems using Montgomery multiplication based on programmable cellular automata (PCA). Multiplication is the key operation in implementing circuits for cryptosystem, as the process of encrypting and decrypting a message requires modular exponentiation which can be decomposed into multiplications. Efficient multiplication algorithm and simple architecture are the key for implementing exponentiation. Thus we employ Montgomery multiplication algorithm and construct simple architecture based on irreducible all one polynomial (AOP) in GF(2^m). The proposed architecture has the advantage of high regularity and a reduced hardware complexity based on combining the characteristics of the irreducible AOP and PCA. The proposed architecture can be efficiently used for public-key cryptosystem.     

可重构双基双域模乘器设计与实现

选择素数域和二进制域上基于字的Montgomery模乘算法,分析传统双域模乘器在二进制域上运算效率不高的问题,首先选择能够使两个域上模乘器延迟时间相当的字长,并对模乘器进行双域的可重构设计,使之能够同时支持素数域和二进制域上的运算。相较以往设计,采用双域双基设计的模乘器使时钟周期数平均缩短了48%。