A high-speed logic LSI using diffusion self-aligned enhancement depletion MOS IC

This paper reports the design, fabrication, and characterization of a diffusion self-aligned enhancement depletion (DSA-ED) MOS IC. It is shown that using DSA structure, a short channel MOST with effective submicron channel length can be realized even by standard photolithographic techniques. High-speed characteristics of a DSA MOST, high gain factors, and small drain junction capacitance are described. The advantage of an ED configuration is discussed. To evaluate the basic performance of the gate, 19-stage ring oscillators with various device sizes have been developed. In the ring oscillator design, the high gain factors of the DSA MOST are fully utilized to minimize the device size and upgrade the performance and packing density. A propagation delay time of 0.65 ns, a power dissipation of 0.15 mW, a power delay product of 0.10 pJ at the supply voltage 2 V, and a packing density of 510 gate/mm/SUP 2/ have been obtained by the single-level metal interconnections of 7 /spl mu/m details. A 4-bit arithmetic logic unit (ALU) has been developed with the same design principle and device size to obtain the 2.9 ns/gate, 0.71 mW/gate performance at the supply voltage of 5 V and 141 gates/mm/SUP 2/ packing density.     

GaAs OPFET characteristics considering the effect of gate depletionwith modulation due to incident radiation

A realistic analytical model of an ion-implanted GaAs OPFET has been presented. Both the photogeneration and photovoltaic effect and the voltage dependence of the depletion layer widths in the active region have been considered. The threshold voltage decreases in the enhancement device and increases in the depletion device at a particular dose, flux density, and trap center density when both the photovoltaic effect and photogeneration are taken into account compared to the case where the photovoltaic effect is ignored. At higher flux density and trap density, the threshold voltage shows a nonlinear effect at a lower value of the implanted dose, which is mainly due to the recombination term. The drain-source current significantly increases due to the photovoltaic effect because of the widening of the channel region. The device is pinched off at a higher drain-source voltage compared to the photogeneration case only     

Use of focused-ion-beam and modeling to optimize submicron MOSFETcharacteristics

An asymmetrical MOSFET structure is formed by using a focused-ion-beam implantor to create a p⁺ channel doping next to the source. This work builds on previous efforts by providing a uniquely tailored doping profile through the use of localized beams. An investigation shows that the output resistance improves, detrimental hot-electron effects diminish, and threshold voltage stabilizes as channel length is reduced. The improved output resistance is especially beneficial to analog applications where enhanced current source characteristics often lead to significantly better circuit operation. Improvements in device performance are attributed to the reduction of the pinchoff region, which is clarified with the help of detailed hydrodynamic device simulations. A two-transistor equivalent circuit model has been developed which reflects the device structure     

An InAlAs/InAs MODFET

An InAs modulation-doped field-effect transistor (MODFET) using an epitaxial heterostructure based entirely on arsenides is reported. The heterostructure was grown by MBE on InP and contains a 30-Å InAs channel. A 2-μm-gate-length device displays well-behaved characteristics, showing sharp pinch-off (V_th=0.8 V) and small output conductance (5 mS/mm) at 300 K. The maximum transconductance is 170 mS mm with a maximum drain current of 312 mA/mm. Strong channel quantization results in a breakdown voltage of -9.6 V, a severalfold improvement over previous InAs MODFETs based on antimonides. Low-temperature magnetic field measurements show strong Shubnikov-de Haas oscillations which, over a certain range of gate voltage, strongly indicate that the electron channel resides in the InAs layer     

An accurate two-dimensional numerical analysis of the MOS transistor

A two dimensional numerical analysis has been made for MOS transistors with both small and large values of channel lenghts and various bias conditions. Results are compared with a simplified analysis of the MOST and with experimental data obtained on devices. Detailed pictures of the free carriers density distribution and of the voltage distribution are presented for various channel lengths and two dimensional effects are clearly seen near the source and the drain that are very hardly accounted for in a simplified one dimensional analysis. Such a program seems to be a very powerful tool for device optimisation and physical understanding of the behaviour of very small devices used in complex circuits.     

A 64-kbit dynamic MOS RAM

A 64-kbit dynamic MOS RAM is developed by using 2 /spl mu/m rule VLSI fabrication technology and low power circuit technology. The 2 /spl mu/m rule VLSI fabrication technology is achieved by improving various aspects of the ultraviolet photolithographic, thin-gate oxidation, arsenic ion implantation, and multilevel interconnection processes. Microminiaturization of the device structure has made the voltage requirements for its MOST threshold voltage and DC supply voltages low. A highly sensitive and low power dissipating sense circuit has been developed for the VLSI RAM. A new level-detecting circuit with a logic threshold which is independent of MOST threshold voltage is proposed. A dynamic address-buffer circuit is also shown. The fabricated 64K RAM has 200 ns of access time, 370 ns of minimum cycle time, and 150 mW of power dissipation under typical supply voltage conditions of V/SUB DD/=7 V and V/SUB BB/=-2 V.     

Electrical characteristics of a DSA MOS transistor with a fine structure

Fabrication technologies and electrical characteristics of a diffusion self-aligned MOS transistor (DSA MOST) or a double-diffused MOS transistor (DMOST) are discussed in comparison with a conventional short-channel MOS transistor as a fundamental device for a VLSI. The symmetrical DSA MOS LSI with enhancement depletion configurations requires six photolithographic steps and the number of the steps is the same as that of an NMOS LSI with small physical dimensions. The only difference is the step orders of the enhancement channel doping in these devices. The lowering effects of the threshold voltage and the source drain breakdown voltage are smaller in the DSA MOST than in the conventional MOS transistor. The drain current IDof the symmetrical DSA MOS transistor is, respectively, 1.13 (in the nonsaturation region) and 1.33 (in the saturation region) times larger than that of the conventional short-channel NMOS transistor at the effective gate voltage of 3.0 V. The improvement of the short-channel effect, the current voltage characteristics, and the power-delay product are obtained by the scaling of the DSA MOS transistor.     

High-current resolution broad-band SQUID amplifier suitable for TEScalorimeter

A superconducting quantum interference device (SQUID) amplifier has been developed as a current detector with both high-current resolution and broad bandwidth for a transition edge sensor calorimeter. The amplifier is a two stage SQUID (TSS) that consists of an input-SQUID with a 38-turn input coil and a 100-serial SQUID array (100-SSA) output, and has been integrated on a 3 × 3 mm Si chip using Nb thin film fabrication technology. It is designed to increase the amplifier gain and maintain matching with the parameters of the calorimeter. To avoid flux trapping in the SSA, the washer coil of the dc-SQUIDs in the SSA was made with a narrow line width of 17.5 μm. We experimentally confirmed that the designed output voltage was achieved using a one-layer p-metal magnetic shield tube in the earth's magnetic field. The performance of the shielded TSS amplifier was evaluated in liquid helium. The TSS amplifier had a gain of 10 kV/A and an impedance of 0.07 Ω at 100 kHz. When a flux locked loop circuit was used to drive the amplifier, a current resolution of 1 pA/√Hz and a rise time of 1 μs were achieved     

Influence of barrier thickness on the high-power performance ofAlGaN/GaN HEMTs

The dependence of current slump in AlGaN/GaN HEMTs on the thickness of the AlGaN barrier was observed. Power measurements on a 2×125×0.3 μm AlGaN/GaN HEMT made on Silicon Carbide (SiC) substrates with an AlGaN thickness of 10 nm gave a saturated output power of 1.23 W/mm at 8 GHz whereas a device with the same dimensions fabricated on samples with an AlGaN barrier of 20 nm gave a saturated output power of 2.65 W/mm at the same frequency. RF load line measurements clearly show the reduction of RF full channel current as compared to dc full channel current and the increase in the RF knee voltage compared to the dc knee voltage, with the effect being more pronounced in thin barrier samples. Passivation improved the large signal performance of these devices. A 1×150×0.3 μm transistor made on AlGaN(20 nm)/GaN structure gave a saturated output power of 10.7 W/mm (40% power added efficiency) at 10 GHz after passivation. This represents the state of the art microwave power density for AlGaN/GaN HEMTs. Heating of the transistors during high-power operation of these devices becomes the important factor in limiting their performance after passivation     

基于栅控二极管研究碲镉汞器件表面效应

采用不同工艺生长了CdTe/ZnS复合钝化层,制备了相应的长波HgCdTe栅控二极管器件并进行了不同条件下I-V测试分析.结果表明,标准工艺制备的器件界面存在较高面密度极性为正的固定电荷,在较高的反偏下形成较大的表面沟道漏电流,对器件性能具有重要的影响.通过钝化膜生长工艺的改进有效减小了器件界面固定电荷面密度,使HgCdTe表面从弱反型状态逐渐向平带状态转变,表面效应得到有效抑制,器件反向特性获得显著改善.此外,基于最优的工艺条件制备的器件界面态陷阱数量得到大幅降低,器件稳定性增强;同时器件R_0A随栅压未发生明显地变化.     

A UMOS power field effect transistor

A power MOST switch fabricated using a U-shaped groove anisotropically etched in silicon is described. The structure provides a short channel while maintaining a reasonable breakdown voltage. Devices with a channel length of 2–3 μm and an active area of 0.23 mm² exhibit breakdown voltages ranging from 35 to 45V with a current handling capability of 1A and a switching time of less than 5 nsec.     

Numerical analysis of MOS magnetic field sensors

A new method of numerical analysis of MOS magnetic field sensors is described, which is based on a lumped discrete approach and the application of a general-purpose circuit-analysis program. The channel region of the device is represented by a network of identical L-type circuit cells. A cell consists exclusively of conventional MOS devices, independent voltage sources and controlled current sources, while the magnetic field appears as a parameter in some of these devices. The method allows for an accurate two-dimensional numerical analysis of MOS sensors, including effects which have been neglected hitherto, such as transverse current flow and nonuniform charge density across the channel. Numerical results are given for conventional MOS plates, split-drain MOS devices and distributed current source biased MOS Hall plates.     

Self Field Effect Compensation in an HTS Tube

It is well known that the critical current density ${J}_{c}$ of a superconducting material depends on the magnetic flux density $B$ . There exists an electric method to measure the ${J}_{c}({B})$ deduced from the $U(I)$ measurements. The problem with this method is the self field effect because the magnetic flux density is always the sum of the applied magnetic flux density and the self magnetic flux density. This paper presents a special experimental arrangement, compensating fully or partially the self magnetic flux density in an HTS tube. It allows characterizing the true zero magnetic flux density behaviour of the superconducting material. The experimental results of the compensation are discussed. A theoretical analysis based on Bean's model is presented and gives results close to the experimental ones. The proposed compensation is not perfect but the experiments and the theoretical analysis allow validation of the compensation principle.      

A monolithic quad line driver for industrial applications

The device described in this paper is a new quad line driver to be used in the hostile and noisy industrial environment and developed in mixed technology (BCD: Bipolar, CMOS, DMOS). It consists of four independent line drivers, each of which has a rail-to-rail push-pull output stage realized with power DMOS transistors connected in half bridge configuration. Even though the device is designed to be used primarily in the output cards of programmable controllers, it is a general purpose device, since it can drive any kind of load (resistive, capacitive, or inductive) with an output current of 100 mA. The novel structure of the top driver allows full protection of the output stage against any kind of short circuits and/or overloads, providing a linear current limitation. Furthermore, when a channel is tristated, for every applied voltage ranging from ground to the supply voltage, virtually zero current is absorbed from the output. An innovative high efficiency central charge pump circuit has also been designed and implemented, making both a very wide supply voltage operation (6-50 V) and high switching frequency (up to 500 KHz) possible, The device can also be used as a receiver since the input voltage can swing from -10-50 V     

A 0.15-μm 60-GHz high-power composite channel GaInAs/InP HEMTwith low gate current

This letter presents recent improvements and experimental results provided by GaInAs/InP composite channel high electron mobility transistors (HEMT). The devices exhibit good dc and rf performance. The 0.15-μm gate length devices have saturation current density of 750 mA/mm at V_GS=+0 V. The Schottky characteristic is a typical reverse gate-to-drain breakdown voltage of -8 V. Gate current issued from impact ionization has been studied in these devices, in the first instance, versus drain extension. At 60 GHz, an output power of 385 mW/mm has been obtained in such a device with a 5.3 dB linear gain and 41% drain efficiency which constitutes the state-of-the-art. These results studied are the first reported for a composite channel Al_0.65In_0.35As/Ga_0.47In_0.53 As/InP HEMT on an InP substrate     

1200V大容量SiC MOSFET器件研制

采用平面栅MOSFET器件结构,结合优化终端场限环设计、栅极bus-bar设计、JFET注入设计以及栅氧工艺技术,基于自主碳化硅工艺加工平台,研制了1200V大容量SiC MOSFET器件.测试结果表明,器件栅极击穿电压大于55V,并且实现了较低的栅氧界面态密度.室温下,器件阈值电压为2.7V,单芯片电流输出能力达到50A,器件最大击穿电压达到1600V.在175℃下,器件阈值电压漂移量小于0.8V;栅极偏置20V下,泄漏电流小于45nA.研制器件显示出优良的电学特性,具备高温大电流SiC芯片领域的应用潜力.     

Improved double-recessed P-buffer 4H-SiC MESFETs with partial heavy doped channel

An improved double-recessed P-buffer 4H-SiC MESFETs with partial heavy doped channel (HD-MESFET) is proposed in this paper. Compared with the double-recessed p-buffer layer (DRB-MESFET), because of the concentration gradient from the heavy doped area to the channel under the low gate, which prevents the lateral expansion of the depletion layer toward source under the gate, and increases its longitudinal width, thus the DC and frequency characteristics of the device are improved. The simulations indicate that the drain saturation current of the proposed structure increased by 18.4%. Despite a slight decrease in the breakdown voltage, the maximum output power density was still increased by 16.5%. In addition, the DC transconductance increased by 32%. Moreover, the proposed structure has an effective promotion in threshold voltage, which improves the effectiveness of the device performance.     

1 W/mm RF power density at 3.2 GHz for a dual-layer RESURF LDMOStransistor

In this letter, we present state-of-the-art performance, in terms of output power density, for an RF-power LDMOS transistor. The novel device structure has a dual-layer RESURF of the drift region, which allows for a sub-μm channel length and a high breakdown voltage of 110 V. The output power density is more than 2 W/mm at 1 GHz and a V_DS=70 V, with a stable gain of 23 dB at V_DS=50 V. At 3.2 GHz the power density is over 1 W/mm at V_DS=50 V and 0.6 W/mm at V_DS=28 V. These results are to our knowledge the best ever for silicon power MOSFETs     

Theory of the MOS transistor in weak inversion-new method to determine the number of surface states

The drain current IDversus gate voltage VGof an MOST operating in weak inversion, and the influence of surface potential fluctuations on this characteristic have been studied before [1], [2]. The purpose of this paper is to derive an expression of the drain current IDversus the drain voltage VDfor devices with a channel length not smaller than 20 µm. It is demonstrated that the surface potential fluctuations do not affect the slope of the ID-VDcurve, whereas the density Nssof surface states strongly influences the slope for small drain voltages. This yields a simple and useful technique to determine Nsson MOS transistors.     

Recessed-gate structure approach toward normally off high-Voltage AlGaN/GaN HEMT for power electronics applications

A recessed-gate structure has been studied with a view to realizing normally off operation of high-voltage AlGaN/GaN high-electron mobility transistors (HEMTs) for power electronics applications. The recessed-gate structure is very attractive for realizing normally off high-voltage AlGaN/GaN HEMTs because the gate threshold voltage can be controlled by the etching depth of the recess without significant increase in on-resistance characteristics. With this structure the threshold voltage can be increased with the reduction of two-dimensional electron gas (2DEG) density only under the gate electrode without reduction of 2DEG density in the other channel regions such as the channel between drain and gate. The threshold-voltage increase was experimentally demonstrated. The threshold voltage of fabricated recessed-gate device increased to -0.14 V while the threshold voltage without the recessed-gate structure was about -4 V. The specific on-resistance of the device was maintained as low as 4 m/spl Omega//spl middot/cm/sup 2/ and the breakdown voltage was 435 V. The on-resistance and the breakdown voltage tradeoff characteristics were the same as those of normally on devices. From the viewpoint of device design, the on-resistance for the normally off device was modeled using the relationship between the AlGaN layer thickness under the gate electrode and the 2DEG density. It is found that the MIS gate structure and the recess etching without the offset region between recess edge and gate electrode will further improve the on-resistance. The simulation results show the possibility of the on-resistance below 1 m/spl Omega//spl middot/cm/sup 2/ for normally off AlGaN/GaN HEMTs operating at several hundred volts with threshold voltage up to +1 V.