应用于10 Gbit/s光通信及背板传输的自适应均衡器设计

描述了一种既可用于背板传输也可用于光纤通信的高速串行收发器前端均衡器的设计。为适应光信号在传播中的色散效应,使用前馈均衡器(FFE)加判决反馈均衡器(DFE)的组合,取代了背板通信中常用的连续时间线性均衡器(CTLE)和DFE的组合。设计使用3 pre-tap、3 post-tap和1个main tap的抽头组合方式,兼顾pre-cursor和post-cursor的信号失真,有效补偿范围为15 dB。补偿系数采用完全自适应算法调整,对FFE采用模拟MSE算法调整,DFE引擎采用1/16速率数字sign-sign最小均方差(LMS)算法实现。芯片使用UMC 28 nm工艺流片,输入信号频率为10 Gbit/s。     

DFE architectures for high-speed backplane applications

Embedded and look-ahead decision feedback equalisation (DFE) architectures are proposed to overcome the speed bottleneck of DFE design for high-speed backplane applications. DFE design examples simulated in 0.18 /spl mu/m CMOS technology demonstrate the feasibility of 10Gbit/s operation over a 34-inch FR4 backplane.     

A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS

Along with CMOS technology scaling, ADC-based serial link receivers have drawn growing interest in backplane communications but power dissipation of the ADC and complex digital equalizer in such digital receivers can be a limiting factor in high-speed applications. Implementing analog embedded equalization within the front-end ADC structure can potentially relax the ADC resolution requirement and reduces the complexity of the DSP which results in a more energy-efficient receiver. In this paper, the equivalence between the speculative comparisons of a loop-unrolling DFE and an ADC with non-uniform quantization levels is utilized to propose a novel ADC-based DFE receiver structure. The equivalency partially compensates for the power overhead imposed by loop-unrolling DFE. The 5-bit prototype receiver with two-tap embedded DFE is designed, laid out and simulated in a 130-nm CMOS process with 1.8 Gbps data rate. With embedded DFE disabled, the receiver achieves 4.57-bits ENOB and 1.77 pJ/conv.-step FOM. With 1.8-Gbps signaling across a 48-in FR4 channel, the two-tap DFE enabled receiver opens the completely closed eye and allows for a 0.26 UI timing margin at a BER of 10⁻⁹. The total active area is 0.21 mm² and the ADC consumes 76 mW from a 1.2-V supply.     

0.18 /spl mu/m CMOS backplane receiver with decision-feedback equalisation embedded

Decision-feedback equalisation (DFE) is explored to reduce intersymbol interference and crosstalks in high-speed backplane applications. In the design of the clock and data recovery circuit, embedding DFE within a phase and frequency detector enhances the recovery of data inherently from distorted input signals and facilitates providing DFE with the recovered clock.     

一个用于背板通信的24Gb/s高速自适应组合均衡器

本文介绍了应用于背板通信系统中均衡器的设计与实现.该均衡器采用连续时间线性均衡器（Continuous Time Linear Equalizer,CTLE）和2抽头判决反馈均衡器（Decision Feedback Equalizer,DFE）的组合结构来消除信道码间干扰中的前标分量和后标分量.在设计中,CTLE采用双路均衡器结构补偿信道不同频率的损耗,减小了电路的面积和功耗;DFE采用半速率预处理结构来缓解传统DFE结构中关键反馈路径的时序限制,并采用模拟最小均方（Least Mean Square,LMS）算法电路控制DFE系数的自适应.电路采用IBM 0.13μm BiCMOS工艺设计并实现,测试结果表明对于经过18英寸背板后眼图完全闭合的24Gb/s的信号,均衡后的眼图水平张开度达到了0.81UI.整个均衡器芯片包括焊盘在内的芯片面积为0.78×0.8mm²,在3.3V的电源电压下,功耗为624mW.     

一种用于背板互连的10 Gbit/s接口电路

基于SMIC 40 nm CMOS工艺,提出了一种用于背板互连的10 Gbit/s I/O接口电路。该接口电路由前馈均衡器(FFE)、接收机前端放大器和判决反馈均衡器(DFE)组成。FFE对发射端信号进行预加重,DFE消除较大的残余码间干扰。重点分析了FFE和DFE在消除码间干扰时存在的问题。使用改进的FFE减少对发射端信号的衰减,保证信号到达接收端时具有较大幅度,实现接收机对信号的正确判决,降低系统的误码率。测试结果表明,系统数据率为10 Gbit/s,传输信道在Nyquist频率(即5 GHz)处的衰减为22.4 dB。在1.1 V电源电压下,判决器Slicer输入端信号眼图的眼高为198 mV,眼宽为83 ps。FFE的功耗为31 mW,接收机前端放大器的功耗为1.8 mW,DFE的功耗为5.4 mW。     

Parallel adaptive decision feedback equalizers

Several algorithms for parallel implementation of adaptive decision feedback equalizers (DFEs) are proposed. The first is a double-row DFE algorithm that outperforms previous approaches. Under the no-error-propagation assumption, the algorithm will perform exactly like a serially adapting DFE. The multiplication complexity of the double-row DFE algorithm is of the same order as that of the parallel DFE algorithm and the extended least-mean-square (LMS) method. The previous algorithms and the double-row DFE algorithm may become impractical to implement due to their large computational complexity, so three additional parallel implementations of the DFE, which lead to considerable hardware savings and avoid the coding loss of the former approaches, are presented. The different algorithms are compared on the basis of convergence analysis and simulation results     

Adaptive combined DFE/MLSE techniques for ISI channels

By embedding a decision-feedback equalizer (DFE) into the structure of a maximum-likelihood sequence estimator (MLSE), an adaptive combined DFE/MLSE scheme is proposed. In this combined DFE/MLSE, the embedded DFE has three functions: (i) prefiltering the received signals and truncating the equivalent channel response into the desired one, (ii) compensating for channel distortions, and (iii) providing the MLSE detector with predicted values of input signals. Since the embedded MLSE detector operates on the predicted signals the detected symbols at the output of the DFE/MLSE do not suffer any delay and can be directly fed back into the embedded DFE so that the error propagation, which usually takes place in a conventional DFE, can be greatly reduced. Analytical and simulation results indicate that the performance is significantly improved by the DFE/MLSE compared to the conventional DFE while its computation complexity is much less than that of the conventional MLSE receiver. The combined DFE/MLSE can use different adaptive structures (block-updating, sliding window updating or symbol-by-symbol updating) to meet different performance objectives. Moreover, the proposed DFE/MLSE provides a trade-off between performance and complexity with a parameter m representing the MLSE detection depth as well as the number of predicting steps of the embedded DFE. For some particular values of m, this scheme is capable of emulating the conventional DFE, MLSE-VA, adaptive LE-MLSE equalizer, adaptive DDFSE, and adaptive BDFE without detection delay     

BAD: bidirectional arbitrated decision-feedback equalization

The bidirectional arbitrated decision-feedback equalizer (BAD), which has bit-error rate performance between a decision-feedback equalizer (DFE) and maximum a posteriori (MAP) detection, is presented. The computational complexity of the BAD algorithm is linear in the channel length, which is the same as that of the DFE, and significantly lower than the exponential complexity of the MAP detector. While the relative performance of BAD to those of the DFE and the MAP detector depends on the specific channel model, for an error probability of 10/sup -2/, the performance of BAD is typically 1-2 dB better than that of the DFE, and within 1 dB of the performance of MAP detection.     

一种高速大容量背板的设计与实现

背板是通信设备的要求.采用传统的板卡平行连接结构的背板,要继续增加带宽已经非常困难,从而成为制约系统容量的一个瓶颈.本文给出了一种采用前后交叉连接结构的高速大容量背板的具体设计实现,在保证信号完整性前提下大大降低了设计难度,其总带宽达到1Tb/s.     

Combined trellis coding and DFE through Tomlinson precoding

The authors propose and evaluate a receiver architecture which combines the power of a decision feedback equalizer (DFE) with trellis coding, while allowing for minimal decoding delay in such a way that the total gain of the system is additive. The system is based on a structure that transposes the feedback filter of the DFE into the transmitter and, for high-order constellations, provides negligible increase in transmitter power. The first known hardware realization of a high bit rate digital subscriber line (HDSL) system that achieves the coding gain provided by a trellis code in addition to the equalization gain provided by the DFE is presented. A system whose complexity of implementation is comparable to that of a typical DFE and an independent Viterbi decoder is proposed     

运用误差反馈的判决反馈均衡器的性能分析

判决反馈均衡器（Decision Feedback Equalizer，DFE）能补偿具有严重符号间干扰（Inter Symbol Interference，ISI）的信道，且不存在线性均衡器增强噪声的影响。而在其基础上改进的运用误差反馈的DFE，可利用误差反馈滤波器来减少传统DFE中存在的误差信号的相关性，同时其硬件实现的复杂度没有明显提高。理论分析和仿真表明，这种方法比传统的DFE更有效，特别是针对信道有严重符号间干扰的情况。     

A Maximum-Likelihood Sequence Estimator with Decision-Feedback Equalization

A decision-feedback equalizer (DFE) is proposed as a prefilter which limits the complexity of a maximum-likelihood sequence estimator (MLSE) implemented by the Viterbi algorithm (VA) for channels having a long impulse response. By imbedding a DFE into the structure of the MLSE, the overall impulse response of the system is truncated to a short duration. With this practical receiver, a compromise may be made between performance and complexity by properly choosing the duration of a desired impulse response. A technique is also developed to estimate the performance of the receiver numerically, taking into account the effect of incorrect decision feedback on the VA. Analysis and computer simulation over a single-pole channel show that the proposed scheme can reduce the complexity of the MLSE while retaining much of its performance advantages.     

Performance improvement in decision feedback equalisers by using`soft decision'

One method to combat intersymbol interference (ISI) in digital transmission is to use a decision feedback equaliser (DFE). It is well known that a major part of the errors made by a DFE is due to the fact that the equaliser makes instantaneous decisions without taking into account data received later. It is therefore obvious that the performance of a DFE could be improved by allowing some type of `soft decision'. A method to introduce `soft decisions' in a decision feedback equaliser is presented. The method gives a performance improvement in SNR of about 1.5 dB with almost no increase in complexity compared to an ordinary DFE     

Cyclostationary crosstalk suppression by decision feedbackequalization on digital subscriber loops

Interference from digital signals in multipair cables has been shown to be cyclostationary under some conditions. This work evaluates the performance of a decision feedback equalizer (DFE) in the presence of cyclostationary interference (CI), intersymbol interference (ISI), and additive white noise (AWN). A comparison between a DFE with CI and one with stationary interference (SI) shows the ability of the DFE to substantially suppress CI. Fractionally spaced and symbol-rate DFE equalizers are also compared and the former is found to yield better performance, especially in the presence of CI. The use of a symbol-rate DFE using an adaptive timing technique that finds the receiver's best sampling phase is proposed for when the fractionally spaced DFE cannot be used because of its complexity. The results also demonstrate the potential benefits of synchronizing central office transmitter clocks, if a fractionally spaced DFE is used at the receiver     

Adaptive Bayesian decision feedback equalizer for dispersive mobileradio channels

The paper investigates adaptive equalization of time-dispersive mobile radio fading channels and develops a robust high performance Bayesian decision feedback equalizer (DFE). The characteristics and implementation aspects of this Bayesian DFE are analyzed, and its performance is compared with those of the conventional symbol or fractional spaced DFE and the maximum likelihood sequence estimator (MLSE). In terms of computational complexity, the adaptive Bayesian DFE is slightly more complex than the conventional DFE but is much simpler than the adaptive MLSE. In terms of error rate in symbol detection, the adaptive Bayesian DFE outperforms the conventional DFE dramatically. Moreover, for severely fading multipath channels, the adaptive MLSE exhibits significant degradation from the theoretical optimal performance and becomes inferior to the adaptive Bayesian DFE     

Importance sampling simulation for evaluating lower-bound symbolerror rate of the Bayesian DFE with multilevel signaling schemes

For the class of equalizers that employs a symbol-decision finite-memory structure with decision feedback, the optimal solution is known to be the Bayesian decision feedback equalizer (DFE). The complexity of the Bayesian DFE, however, increases exponentially with the length of the channel impulse response (CIR) and the size of the symbol constellation. Conventional Monte Carlo simulation for evaluating the symbol error rate (SER) of the Bayesian DFE becomes impossible for high channel signal-to-noise ratio (SNR) conditions. It has been noted that the optimal Bayesian decision boundary separating any two neighboring signal classes is asymptotically piecewise linear and consists of several hyperplanes when the SNR tends to infinity. This asymptotic property can be exploited for efficient simulation of the Bayesian DFE. An importance sampling (IS) simulation technique is presented based on this asymptotic property for evaluating the lower bound SER of the Bayesian DFE with a multilevel pulse amplitude modulation (M-PAM) scheme under the assumption of correct decisions being fed back. A design procedure is developed, which chooses appropriate bias vectors for the simulation density to ensure asymptotic efficiency (AE) of the IS simulation     

Fast adaptive equalization/diversity combining for time-varyingdispersive channels

We examine adaptive equalization and diversity combining methods for fast Rayleigh-fading frequency selective channels. We assume a block adaptive receiver in which the receiver coefficients are obtained from feedforward channel estimation. For the feedforward channel estimation, we propose a novel reduced dimension channel estimation procedure, where the number of unknown parameters are reduced using a priori information of the transmit shaping filter's impulse response. Fewer unknown parameters require a shorter training sequence. We obtain least-squares, maximum-likelihood, and maximum a posteriori (MAP) estimators for the reduced dimension channel estimation problem. For symbol detection, we propose the use of a matched filtered diversity combining decision feedback equalizer (DFE) instead of a straightforward diversity combining DFE. The matched filter form has lower computational complexity and provides a well-conditioned matrix inversion. To cope with fast time-varying channels, we introduce a new DFE coefficient computation algorithm which is obtained by incorporating the channel variation during the decision delay into the minimum mean square error (MMSE) criterion. We refer to this as the non-Toeplitz DFE (NT-DFE). We also show the feasibility of a suboptimal receiver which has a lower complexity than a recursive least squares adaptation, with performance close to the optimal NT-DFE     

Near‐Optimum Blind Decision Feedback Equalization for ATSC Digital Television Receivers

This paper presents a near‐optimum blind decision feedback equalizer (DFE) for the receivers of Advanced Television Systems Committee (ATSC) digital television. By adopting a modified trellis decoder (MTD) with a trace‐ back depth of 1 for the decision device in the DFE, we obtain a hardware‐efficient, blind DFE approaching the performance of an optimum DFE which has no error propagation. In the MTD, the absolute distance is used rather than the squared Euclidean distance for the computation of the branch metrics. This results in a reduction of the computational complexity over the original trellis decoding scheme. Compared to the conventional slicer, the MTD shows an outstanding performance improvement in decision error probability and is comparable to the original trellis decoder using the Euclidean distance. Reducing error propagation by use of the MTD in the DFE leads to the improvement of convergence performance in terms of convergence speed and residual error. Simulation results show that the proposed blind DFE performs much better than the blind DFE with the slicer, and the difference is prominent at the trellis decoder following the blind DFE.     

A study of analog decision feedback equalization for ADC-Based serial link receivers

High-speed serial link receivers based on analog-to-digital converters (ADCs) provide better programmability with different channel characteristics and the possibility of employing powerful signal equalization techniques in the digital domain. However, complexity and power consumption are still major issues in adopting such receivers in high-speed applications when compared to traditional binary or mixed-signal approaches. Embedded decision feedback equalization (DFE) before ADC quantization can relax the design requirements of both the ADC and post-ADC digital processing. This paper studies the impact of embedded analog DFE on voltage margin improvement of an ADC-based receiver through worst-case analysis. An analytical expression for the link bit-error-rate (BER) with analog DFE is derived and validated through simulations. An empirical study is conducted that evaluates the achievable BER of embedded analog DFE as a function of the channel inter-symbol interference (ISI) and ADC resolution. A channel-dependent parameter is introduced and employed to quantify the BER improvement achieved by embedding analog DFE in a receiver. A prototype receiver with embedded DFE is designed and laid out in a 130 nm CMOS process and achieves 4.64-bits peak ENOB and 4.08 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. The BER performance of the receiver over high-loss FR4 channels at 1.6 Gb/s is evaluated and used to validate the simulation results.