使用MOSFET管不同参数影响研究

总结MOSFET管分类及特点及MOSFET管的温度对开启电压,导通电阻,漏源极电压,漏电流,雪崩能量等参数的影响。     

基于异质结倍增层的InAlAsSb SACM雪崩光电二极管的优化

使用低工作电压的雪崩光电二极管(APD)有利于提高集成电路的稳定性和降低功耗.文章建立了一个分离吸收、电荷、倍增(SACM)型的雪崩光电二极管的模型,为了在低偏压下获得高增益同时不降低工作电压范围,这个模型采用了具有高低禁带宽度的异质结倍增层.同时,文章研究了异质结倍增层的厚度和掺杂浓度对暗电流和增益的影响.通过对掺杂浓度的优化,击穿电压和穿通电压可以同时下降.     

工艺参数对低压TVS器件耐压的影响

目前低压瞬间电压抑制(TVS)二极管工艺参数的研究还不够深入.从深p型(DP)基区杂质浓度、杂质注入能量及基区尺寸控制三个方面探究了工艺条件对低击穿电压的影响.当DP注入剂量小于6.0×1014cm-2时,pn结以雪崩击穿为主,耐压大于6V.DP注入能量在50 keY以下与高浓度n+区复合形成的pn结雪崩击穿耐压大于6V;当控制基区尺寸使n+集电区与DP基区的间距大于1.2 μm时击穿电压保持为7V,但是随着n+与DP基区的间距增加,电流导通路径受到挤压变窄,在相同的反向测试电流下,器件耐压略有提升.通过对单向TVS工艺仿真优化,选择了关键工艺参数,并进行了工程实验,制备了兼具低电容和高抗ESD能力的TVS器件,保证了对主器件实施可靠的保护.     

双极RF功率管的深阱结终端

给出了双极RF功率管新的深阱结终端结构.模拟分析表明,具有优化宽度、优化深度且填充绝缘介质的深阱结终端结构能使雪崩击穿电压提高到理想值的95%以上.实验结果表明,深阱结终端结构器件DCT260的BVCBO为理想值的94%,比传统终端结构器件高14%;与传统结构相比,在不减小散热面积的情况下,该结构还减小集电结面积和漏电流,器件的截止频率提高33%,功率增益提高1dB.     

用分子束外延法制作的双异质结GaAs/Al_xGa_(1-x)As双极晶体管

制作并试验了用分子束外延法生长的双异质结AlGaAs/GaAs双结晶体管(DHBJT)。掺入缓变基极-集电极结改进了DHBJT的dc特性,它优于用突变基极-集电极结所获得的特性。采用缓变集电极和发射极结以及基区宽度为0.05、0.2和0.1μm分别获得最大电流增益为500、900和1650,从0.1μm基区宽度到0.05μm基区宽度的电流增益下降是由于采用高基区掺杂浓度使电子寿命降低引起的。1650值可以与用液相外延法生长的HBJT所获得的电流增益相媲美,它是用MBE生长的HBJT获得的最佳值。业已发现共发射极晶体管的导通电压与集电极和发射极结导通电压之差相对应。用700℃(作为最佳温度)高集电极生长温度改进了dc特性,具有超晶格界面的DHBJT的初步结果表明,在集电极电流电平的较宽范围内电流增益几乎是不变的。     

双极RF功率管的深阱结终端

给出了双极 RF功率管新的深阱结终端结构 .模拟分析表明 ,具有优化宽度、优化深度且填充绝缘介质的深阱结终端结构能使雪崩击穿电压提高到理想值的 95 %以上 .实验结果表明 ,深阱结终端结构器件 DCT2 6 0的BVCBO为理想值的 94 % ,比传统终端结构器件高 14 % ;与传统结构相比 ,在不减小散热面积的情况下 ,该结构还减小集电结面积和漏电流 ,器件的截止频率提高 33% ,功率增益提高 1d B     

用少量元件实现噪声减半的自动调零放大器

Analog DevicesAD8553自动调零仪表放大器有一个独特的结构，它的两只增益设定电阻没有公共节点（参考文献1）。该IC的前级是一个精密电压／电流转换器，其中增益电阻R1设定了互导的大小。IC的后级是一个精密电流／电压转换器，与反馈电阻R2的值共同确定了总体电压增益，即G=2（R2/R1）。会发现，两只增益设定电阻是相互独立的，输入级是一个压控电流源，     

跨导放大器的设计考虑

2008年4月采用电压反馈放大器(VFA)来设计一个优质的电流到电压(跨导放大器)转换器是一项重大的挑战。理论上,一个光电二极管当曝露在光线中时可产生一个电流或电压输出,而跨导放大器(TIA)便是将这个很弱的电流转换成一个可用的电压信号,通常跨导放大器均需经过补偿才能正常工作。     

低噪声APD偏置电路

１ＡＰＤ的特性雪崩光电检测器 (ＡＰＤ)和ＰＩＮ二极管通常被作为接收器用于光通信中。其中ＡＰＤ适合于高灵敏度和高带宽的光接收电路。但这种器件在工作时需要施加一个反向结压 ,这样 ,当接收到射线时产生的电子空穴对会被外加电场收集并转换为电流 ,其电流强度正比于射线强度。另外 ,工作时施加在器件上的反向偏置电压会引发雪崩效应 ,其雪崩增益可通过改变偏压来进行调节。这就有可能对光纤接收器的增益进行优化。然而 ,要得到满意的雪崩增益 ,就必须给ＡＰＤ提供一个比较高的反向偏压。很多ＡＰＤ需要４０Ｖ～６０Ｖ的偏压 ,有些器件…     

二极管击穿电压的数值计算

本文以与实验结果符合得最好的R.V.Overstraeten等人的碰撞电离率为依据,按照雪崩击穿条件,采用数值方法计算了非穿通型单边突变结的雪崩击穿电压与衬底掺杂浓度的关系.在此基础上得到了非穿通型二极管击穿电压与电阻率的经验关系式,此组公式在给定的电压范围内与数值结果符合得相当好.对于穿通型二极管,把这些经验公式与解析式相结合所得结果与数值计算结果符合的程度更加令人满意.     

一种新N型射极势垒绝缘栅双极晶体管

本文提出了一种新N型射极势垒绝缘栅双极晶体管。该器件用N型轻掺杂区代替传统的P+区形成空穴势垒,以阻止寄生PNP晶体管空穴分流,从而增强电导调制效应。仿真验证结果显示,该器件对比传统沟槽IGBT,其电流密度和关断损耗分别增加和降低了49%和25%,同时具有相似的击穿电压、关断时间和雪崩能量。此外,该器件具有无限大的跨导,有利于开通和关断。因此,该器件可应用于高压大功率电力电子系统。     

Triggering phenomena in avalanche diodes

The operation of a small area p-n junction diode above the breakdown voltage is analyzed. A new formulation in terms of ionization probability is used to derive the rate of turn-on of current in such structures. Two differential equations are given which may be used to compute the probability that a carrier swept into or generated within the space-charge region triggers avalanche breakdown. For a 27-V n⁺-p diode biased 1 V above breakdown, this probability is close to 0.5 for an electron entering from the p side, or 0.1 for a hole entering from n side. Experimental measurements are in good agreement with the theoretical predictions.     

Practical aspects of the depletion etch method in high-voltage devices

In an earlier paper a new junction-termination geometry was described which was able to give near-ideal avalanche breakdown voltage in both plane and planar p-n junctions. The difficulty of the DEM (depletion etch method) was to achieve a precise etch depth which failure to achieve led to reduced effectiveness. In this paper the range of avalanche breakdown voltage is related to the accuracy of the depletion etch in a quanitative and rather general way so thatDelta V, the decrease in breakdown voltage below the ideal is related toDelta Y, the deviation in etch depth from the ideal, for any p-n junction.     

Arrayed silicon avalanche cathodes

Silicon avalanche cathodes (SACs) consisting of a heavily doped shallow (less than 300 A) p-n junctions were fabricated, characterized, and used as electron sources in Si-based microvacuum diodes. The emission current was investigated as a function of diode reverse-biased voltage and external field. The field was provided by an anode placed approximately 1 mm above the cathode to simulate the field which would be obtained with a built-on-chip anode. Eighteen different shapes and sizes of SACs were tested. An emission current of 0.24 μA and an emission efficiency (emission current/total diode current) of 2.1×10^-5 were observed from the single bare Si p-n junction cold cathode     

A fast method of calculating avalanche breakdown voltage of semiconductor p-n junction

A fast method of calculating the avalanche breakdown voltage of semiconductor p-n junction is described. A simple technique of calculating the integral from the stored values of the integrand is illustrated for Silicon step junctions. This results in considerable saving of computational time.     

MOS型硅功率器件的耐压与终端处理

本文介绍了MOS型硅功率器件常见的平面结击穿电压的基本理论和提高击穿电压的基本方法以及终端处理技术发展中所面临的课题。     

A double-gate-type static-induction thyristor

A double-gate-type static-induction thyristor (DG-SIThy) with a high blocking voltage and a high current rating has been fabricated. In this paper, a basic operational mechanism, a fabrication procedure, and the electrical characteristics of the DG-SIThy are described. In the DG-SIThy, both electron injection and hole injection are controlled by signals applied to two gale regions so that the DG-SIThy is capable of higher frequency operations than a single-gate SIThy. In the DG-SIThy, described here, both a cathode and a gate (first gate) regions have been fabricated on one side of a semiconductor wafer and both an anode and gate.(second gate) regions on another side. For realizing the DG-SIThy with a high blocking voltage and a high current rating, we have tried attentively to form a p-n junction on one side of the wafer without influencing the p-n junction on the other side, and have developed a new counter-doping technique for epitaxial growth and an improved package structure for a compression-mounted device. The DG-SIThy fabricated with these techniques has shown a for-Ward blocking voltage of 1000 V, an average current rating of 100 A, and a forward voltage drop of 1.44 V at the rated anode current. A turn-on time of 0.95 its and a turn-off time of 0.48 µs have been observed at the rated anode current and at anode voltages of 650 and 550 V, respectively. As already speculated, the DG-SIThy shows a higher switching speed and a lower forward drop than the single-gate SIThy.     

Avalanche breakdown characteristics of a diffused P-N junction

A one-dimensional analysis is presented on the avalanche breakdown characteristics of a diffused p-n junction diode. By numerically integrating the carrier ionization rate in a junction space-charge layer, avalanche breakdown voltage is calculated for diffused diodes of silicon and germanium; this voltage is graphically illustrated throughout a range of parameters applicable to most practical situations. In addition, for calculating the maximum cutoff frequency of varactor diodes, junction capacity is similarly illustrated assuming the device is biased to avalanche breakdown. From these illustrations, and from an accompanying nomograph which relates the physical constants of a junction to its impurity atom gradient, the above parameters can be readily established without additional calculations. Further, examples are also presented to demonstrate the reduction of breakdown voltage resulting from a rapid increase of conductivity within the space-charge layer of a diffused p-n junction; this situation approximates many epitaxial and double diffused structures.     

一种最小电压应力的软开关无桥PFC技术研究

针对传统桥式整流升压功率因数校正(PFC)电路效率较低的缺点,提出了一种最小电压应力的软开关无桥PFC电路拓扑.在理论分析和仿真验证的基础上,研制了一台300 W的实验样机.结果表明,改进的无桥PFC电路拓扑具有通态损耗低、电流采样简单,能实现开关管零电压关断和零电流开通,同时实现整流二极管零电压导通和接近零电流软关断...     

1000-V, 30-A 4H-SiC BJTs with high current gain

This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.