Fast organic thin-film transistor circuits

We have fabricated organic thin-film transistors and integrated circuits using pentacene as the active material. Devices were fabricated on glass substrates using low-temperature ion-beam sputtered silicon dioxide as the gate dielectric and a double-layer photoresist process to isolate devices. These transistors have carrier mobility near 0.5 cm²/V-s and on/off current ratio larger than 10⁷. Using a level-shifting design that allows circuits to operate over a wide range of threshold voltages, we have fabricated ring oscillators with propagation delay below 75 μs per stage, limited by the level-shifting circuitry. When driven directly, inverters without level shifting show submicrosecond rise and fall time constants     

Scaling limits of organic digital circuits

The effect of device scaling on organic circuits’ performance was studied. Particularly, the influence of contact resistance on the static and the dynamic behavior of the circuits was investigated. For that purpose, an analytical model describing the voltage transfer characteristics (VTCs) and the propagation delay was developed. Using the model, it was shown that for OTFTs with channel lengths of less than 10 μm the contact resistance has negative influence on both, the static noise margin (SNM) and the propagation delay. Moreover, the model is in a good agreement with experimentally measured data. Scaling the lateral dimensions of the transistors down to few μm limits the circuit performance due to contact effects, and the 1–10 MHz frequency range operation required by some applications can only be achieved by reducing the specific contact resistance, ρ_c, 10–100 times. This need for ρ_c reduction highlights the importance of improving charge injection in organic transistors that can usually be achieved by contact doping like in inorganic electronics.     

Adaption of directly measurable transistor noise parameters to computer-aided noise analysis

A transistor is conveniently characterised by four real noise parameters available from outer-terminal measurements. This representation is easily implemented into a computer program for noise analysis. The Rothe-Dahlke noise circuit is used in connection with the adjoint-network concept, and no additional auxiliary nodes are required.     

Measurement of digital noise in mixed-signal integrated circuits

This paper proposes a method of measuring the influence of digital noise on analog circuits using wide-band voltage comparators as noise detectors. Noise amplitude and r.m.s voltage are successfully measured by this method. A test chip is fabricated to measure the digital noise influence. From the experimental results, it is shown that the digital noise influence can be considerably reduced by using a differential configuration in analog circuits for mixed-signal IC's. The digital noise influence can be further reduced by lowering the digital supply voltage. These results show that the voltage-comparator-based measuring method is effective in measuring the influence of digital noise on analog circuits     

Crosstalk noise reduction in synthesized digital logic circuits

As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: First, it can destroy logical information carried by a circuit net. Second, it causes delay uncertainty: Non critical paths might become critical because of noise. As a result, circuit speed becomes limited by noise, primarily because of capacitive coupling between wires. Most design approaches address the crosstalk noise problem at the layout generation stage, or via postlayout corrections. With continued scaling, too many circuit nets require corrections for noise, causing a design convergence problem. This work suggests to consider noise at the gate-level netlist generation stage. The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. A design flow is proposed for automatically synthesizing CMOS circuits that have improved robustness to noise effects, using standard tools, by limiting the range of gate strengths available in the cell library. The synthesized circuits incur a penalty in area/power, which can be partially recovered in a single postlayout corrective iteration. Results of design experiments indicate that delay uncertainty is the most important noise-related concern in synthesized static CMOS logic. Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. By using the proposed design flow, timing uncertainty was reduced to below 3%, with area and power penalties below 20%.     

Large scale,flexible organic transistor arrays and circuits based on polyimide materials

Polyimide (PI) materials are lightweight, flexible, resistant strongly to heat and chemicals, and have been widely used in electronics industry such as working as electronic packaging materials in large-scale integrated circuits. In this letter, PI materials, for the first time, are introduced into organic field-effect transistors (OFETs) and circuits as insulator layers in order to be compatible with the photolithography process. Moreover, a novel method is developed to make the PI films strong enough to endure the critical processes of photolithography (e.g., the influence of developer on polyimide layer). Based on the intact PI insulator and the modified photolithographic technique, large scale, flexible transistor arrays and circuits were fabricated with high resolution and high performance (mobility up to 0.55 cm² V⁻¹ s⁻¹ for bottom-contact bottom-gate OFETs). It provides a new way for the fabrication of large-area organic devices and circuits beyond solution printed techniques, especially for the application of organic semiconductors with poor solubility, e.g., pentacene.     

Compound noise separation in digital circuits using blind source separation

Analysis of individual noise sources in pre-nanometer circuits cannot take into account the evolving reality of multiple noise sources interacting with each other. Noise measurement made at an evaluation node will reflect the cumulative effect of all the active noise sources, while individual and relative severity of various noise sources will determine what types of remedial steps can be taken, pressing the need for development of algorithms that can analyze the contributions of different noise sources when a noise measurement is available. This paper addresses the cocktail-party problem inside integrated circuits with multiple noise sources. It presents a method to extract the time characteristics of individual noise source from the measured compound voltage in order to study the contribution and properties of each source. This extraction is facilitated by application of blind source separation technique, which is based on the assumption of statistical independence of various noise sources over time. The estimated noise sources can aid in performing timing and spectral analysis, and yield better circuit design techniques.     

Low-frequency noise figure and its application to the measurement of certain transistor parameters

Low-frequency noise measurements are shown to provide a convenient and reasonably accurate (±10 per cent) means of measuring r'_{b}. Their application to the measurement of the factornin the junction lawp_{e} = p_{n} (e_^{qV/nkT} - 1)is also described, though the values ofnobtained from noise measurements do not check accurately with the values ofndetermined by other methods. Experimental determinations of the variation of low-frequency noise figure with emitter-bias current are also presented for several transistor types. The observed behavior suggests that the principal source of1/fnoise in low-noise transistors may be in the emitter-base transition region instead of on the base surfaces where it is placed in presently accepted noise models.     

A digital library for a flexible low-voltage organic thin-film transistor technology

This paper presents the design, fabrication and characterization of digital logic gates, flip-flops and shift registers based on low-voltage organic thin-film transistors (TFTs) on flexible plastic substrates. The organic transistors are based on the p-channel organic semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) and have channel lengths as short as 5 μm and gate-to-contact overlaps of 20 μm. The organic TFT is modeled which allows us to simulate different logic gate architectures prior to the fabrication process. In this study, the zero-VGS, biased-load and pseudo-CMOS logic families are investigated, where their static and dynamic operations are modeled and measured. The inverter and NAND gates use channel length of 5 μm and operate with a supply voltage of 3 V. Static and dynamic master-slave flip-flops based on biased-load and pseudo-CMOS logic are designed, fabricated and characterized. A new design for biased-load dynamic flip-flops is proposed, where transmission gate switches are implemented using only p-channel transistors. 1-stage shift registers based on the new design and fabricated using TFTs with a channel length of 20 μm operate with a maximum frequency of about 3 kHz.     

Influence of impact-ionization-induced base current reversal onbipolar transistor parameters

In this paper we describe a set of measurements representing a complete characterization of impact-ionization effects in bipolar transistors. We demonstrate that impact-ionization significantly influences the dependence of base resistance on current and voltages applied to the device. A dc method for the simultaneous extraction of all parasitic resistances in bipolar transistors is presented. The method can separate the influence of current-crowding on the base resistance from that of base width and conductivity modulation; the collector parasitic resistance is measured in the active region. Starting from the parameters extracted by means of these techniques, a complete and accurate circuit-model of impact-ionization effects can be defined     

Analog and digital circuits using organic thin-film transistors onpolyester substrates

We have fabricated and characterized analog and digital circuits using organic thin-film transistors on polyester film substrates. These are the first reported dynamic results for organic circuits fabricated on polyester substrates. The high-performance pentacene transistors yield circuits with the highest reported clock frequencies for organic circuits     

Influence of raypath parameters on digital radio outage

The received power frequency correlation coefficient taking account of amplitudes, phase path delays and angles of arrival of rays is derived theoretically to evaluate the frequency selectivity of multipath fading. An estimation of frequency selectivity reduction due to aperture antennas is presented by using ray tracing data.     

Equivalent circuits of a transistor mixer

Both resistive and reactive effective parameters of a transistor mixer are expressed in terms of oscillator amplitude and the small-signal quiescent parameters. The frequencies of the three signals in a mixer, being different, give rise to three effective equivalent circuits: one in respect of the intermediate-frequency output, one as presented to the radio-frequency source and one as presented to the oscillator source. The proposed circuits offer a convenient means of mixer-circuit design up to the frequencies at which the small-signal equivalent circuit is applicable.     

Influence of carrier mobility and design parameters on field effect transistor characteristics

The operation of a field effect transistor (FET) having a plane circular geometry is analyzed. By taking limits, the solution for a plane rectangular geometry is obtained. The carrier mobility is assumed to vary asE(-1/n), whereEis the drift field andnan experimentally determined number depending on the drift field. Assuming the gradual approximation to hold, the device characteristics are established analytically and graphically. Operation in the hypercritical range decreases the device sensitivity to geometric factors and certain material constants. It concentrates the channel resistance toward the drain. The dynamic conductance is shown to be a strong function of the drift-field range and of the drain voltage, particularly in the high field ranges and for low drain voltages. The optimum drift-field range giving the highest slope and frequency limit depends on the geometry. The slope, maximum for zero bias for all ranges, is a strong function of the bias. The operational frequency limit is shown to be proportional toP(n-1/3n-1), wherePis the power handling capacity per unit length. For practical devices, this limit is 10 to 15 times less than the highest limit obtainable based on circuit considerations alone. The present work has confirmed the findings of previous investigations and has extended the results to cover new geometrical configurations and wider operating ranges. It provides data for device optimization and may, therefore, be of use to designers.     

Changes of the four noise parameters due to general changes of linear two-port circuits

Transformation formulas for the four noise parameters are given as a function of the four scattering parameters. For example, the influence of the lead inductances of a microwave bipolar transistor is examined, showing new significant results. The described procedure is applicable to other semiconductor devices. Most of the general formulas in Section II are believed to be new.     

High-frequency noise of the junction field-effect transistor

Based on Geurst's treatment of the high-frequency value of the admittances of the junction field-effect transistor, the high-frequency noise of the device has been computed, assuming that the noise source is of thermal origin. By applying an appropriate series expansion of the current it is possible to express the noise of the drain and gate current in terms of known quantities, as steady-state transconductance, gate capacitance, and frequency. At low frequencies the noise spectrum of the drain current is independent of the frequency and is much larger than the noise of the gate current; however, at high frequencies the noise spectra of the gate and drain current both vary by ω²and are of the same order of magnitude.     

Influence of oxygen on the parameters of a thin film copper phthalocyanine field effect transistor

The influence of oxygen on the electrical parameters of a copper phthalocyanine thin film field effect transistor was investigated by means of temperature‐modulated field effect spectroscopy. It was found that both the dark electrical conductivity and threshold voltage of the source–drain current versus gate voltage dependence were changed after oxygen exposure. Both effects can be effectively utilised for gas sensing. Copyright © 1999 John Wiley & Sons, Ltd.     

Haar wavelet method for the analysis of transistor circuits

This paper presents Haar wavelet based method of analysis for observer design in the generalized state space or singular system of transistor circuits. The technique can be interpreted from the incremental and multiresolution view point. Accurate solutions can be obtained by changing the time scale (m), at the same time the main features of the solution are preserved. It can be easily implemented with a digital computer and it is found to be fast, flexible, convenient and computationally attractive.     

Deriving stability criteria for nonlinear circuits with application to worst-case noise margin of I2L

A simplified method of deriving stability criteria for nonlinear circuits is introduced. Unlike the conventional approach which requires construction of a small-signal equivalent circuit and identification of loops, only the basic nonlinear circuit equations are needed. The method is applied to the calculation of the worst-case static noise margin of I2L, which is shown to be much smaller than a recently published result.     

Sub-threshold current in organic thin film transistors: Influence of the transistor layout

This paper highlights an intrinsic difference between organic thin film transistor architectures, namely planar and staggered structures, using a numerical drain current model. From simulation results it is demonstrated that the transistor structure in itself impacts the sub-threshold slope, the onset voltage and the threshold voltage. This is due to the location of the source contact with respect to the accumulation layer. The potential profile induced in the device by the gate–source voltage differs in planar or staggered architectures, and the gate control is shown to be much more efficient in the planar configuration. This paper describes in detail the electrical behavior of both OTFT configurations, based on numerical simulations.