金丝楔形键合强度的影响规律分析

金丝楔形键合是一种通过超声振动和键合力协同作用来实现芯片与电路引出互连的技术。现今,此引线键合技术是微电子封装领域最重要、应用最广泛的技术之一。引线键合互连的质量是影响红外探测器组件可靠性和可信性的重要因素。基于红外探测器组件,对金丝楔形键合强度的多维影响因素进行探究。从键合焊盘质量和金丝楔焊焊点形貌对键合强度的影响入手,开展了超声功率、键合压力及键合时间对金丝楔形键合强度的影响研究。根据金丝楔焊原理及工艺过程,选取红外探测器组件进行强度影响规律试验及分析,指导实际金丝楔焊工艺,并对最佳工艺参数下的金丝键合拉力均匀性进行探究,验证了金丝楔形键合强度工艺一致性。     

小尺寸、细间距焊盘键合的工艺研究

随着技术的进步，对混合电路的集成度要求越来越高，芯片的功能不断增加，尺寸却越来越小，从而导致焊盘在整个芯片中所占的面积比率明显上升，因此造成焊盘，以及焊盘间的间距减小，这就给正常的键合带来了困难。然而引线键合是厚膜工艺申的关键技术，它直接影响集成电路的可靠性和成品率。因此通过此项研究制定相应的工艺规范，使小尺寸、细间距焊盘的芯片可以顺利完成键合组装。     

引线键合工艺介绍及质量检验

介绍了引线键合工艺流程、键合材料及键合工具,讨论分析了影响引线键合可靠性的主要工艺参数,说明了引线键合质量的评价方法,并提出了增强引线键合可靠性的措施。     

一种提升电路板键合可靠性的前处理方法

为解决微波组件生产过程中多次使用钎焊与胶粘工艺,带来的助焊剂氧化残留、导电胶油剂沾污镀金焊盘和电路板加工生产过程引入的油墨沾污镀金焊盘等问题。对键合焊盘的前处理方法进行研究,提出一种激光微刻蚀键合焊盘的前处理方法,对电路板键合界面进行100%激光微刻蚀处理,使得键合界面“归一化”,提升键合焊点质量。彻底消除由于键合界面清理不彻底,导致虚焊、脱焊、键合强度偏低的现象,确保引线键合的可靠性,以期为微波组件生产工艺人员解决键合界面沾污问题提供参考。     

高温存储下铜线键合焊点分析

采用铜引线键合工艺生产的电子元器件在服役中会产生热,引起引线与金属化焊盘界面出现IMC(intermetallic compound,金属间化合物)。IMC的生长和分布将影响键合点的可靠性,严重时会出现"脱键",导致元器件失效。研究了焊点在服役过程中的演化,选取铜线键合产品SOT-23为试验样品,分析了在高温存储试验环境下焊点键合界面IMC的生长及微观结构变化情况。     

芯片铝焊盘上不同金属丝键合质量研究

金属键合丝是半导体封装中非常关键的材料,它直接影响到键合的工艺表现和互连的可靠性。以不同金属丝(金丝、钯铜丝、金钯铜丝、银丝)和芯片铝焊盘第一焊点的键合为研究对象,分析对比各金属丝作为键合丝材料本身的基本性质、与铝焊盘键合第一焊点的工艺性能、与铝焊盘键合第一焊点的可靠性,发现其工艺性能和可靠性都满足半导体封装的键合要求。可靠性试验显示,各金属丝与铝焊盘之间的金属间化合物生长速度不同,但与可靠性失效无直接关系;可靠性失效都是由于金属丝焊球与铝焊盘脱落造成的;选择不同金属丝键合可满足不同的可靠性要求。     

微波组件细间距金丝键合工艺的可靠性分析

细间距小尺寸的焊盘键合工艺是微波组件自动键合工艺面临的关键技术瓶颈.针对具体产品,分析了细间距小尺寸焊盘的球焊键合的工艺控制要点,提出了改进劈刀结构、改进焊线模式、优化工艺参数等方面的工艺优化手段,采用该优化方法后,焊接的可靠性和稳定性得到了很大的提高,达到了提升自动球焊键合质量和提高金丝键合工艺精度的目的.     

CMOS芯片键合失效分析与研究

通过对CMOS芯片引线键合过程中发生铝焊盘剥落和出现"弹坑"两种现象进行分析,明确了该类故障现象的发生是由于键合焊盘受到了不同程度的机械作用而产生的不同程度的损伤.对可能造成该类故障现象的因素进行分析,主要因素有:芯片自身存在结构薄弱或原始缺陷,键合材料、键合参数等匹配不佳,操作中引入的不当因素等.对引线键合的方式和原...     

引线键合技术进展

引线键合以工艺简单、成本低廉、适合多种封装形式而在连接方式中占主导地位.对引线键合工艺、材料、设备和超声引线键合机理的研究进展进行了论述与分析,列出了主要的键合工艺参数和优化方法,球键合和楔键合是引线键合的两种基本形式,热压超声波键合工艺因其加热温度低、键合强度高、有利于器件可靠性等优势而取代热压键合和超声波键合成为键合法的主流,提出了该技术的发展趋势,劈刀设计、键合材料和键合设备的有效集成是获得引线键合完整解决方案的关键.     

微波电路引线键合质量的影响因素分析

在一级封装的三种实现电气连接的互连方法中,内引线键合是一种传统的最成熟的技术.其工艺主要分为球焊与楔焊,其中后者由于焊点较小,适用于微波混合电路的组装.从工艺的角度出发,明确了除引线键合参数(超声频率和功率、温度、压力、时间)的设置以外,键合表面与界面的问题对引线键合的质量影响极大,并分别从键合材料的选用、键合表面的状态、键合工具的选型等三方面进行论述.同时结合实际工作,对常见的键合问题与原因分析以及引线键合质量评估的方法进行了说明.     

Flip chip interconnect systems using copper wire stud bump and leadfree solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly     

Single chip bumping and reliability for flip chip processes

Processes of bump deposition based on mechanical procedures together with their reliability data are summarized in this paper. The stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge–wedge bonding machine. This wedge bumping doesn’t require a wire flame-off process step. Because of this, no active atmosphere is necessary. The minimum pad diameter which can be bumped using the solder wedge bumping is 50 μm, up to now. This bumping process is highly reproducible and therefore well-suited for different flip chip soldering applications. Palladium stud bumps provide a solderable under bump metallization. Results from aging of lead/tin solder bumps on palladium are shown. The growth of intermetallics and its impact on the mechanical reliability are investigated.     

A Preliminary Electron Backscatter Diffraction Study of Microstructures and Microtextures Evolution during Au Stud and Flip Chip Thermosonic Bonding

Microstructures and microtextures of the gold wire, free air ball, Au stud bumps and flip chip bonding bumps were analyzed using Electron Backscatter Diffraction (EBSD). It is demonstrated that process parameters, such as bonding power, force and temperature have significant influences on the microstructure and microtexture of gold bumps. The non-uniform deformation, the associated microstructure defects and the local textures of the Au bumps under the vertical force and the horizontal ultrasonic wave applied are presented and discussed.     

Evaluation of reliability and metallurgical integrity of wire bonds and lead free solder joints on flexible printed circuit board sample modules

This paper presents a study of the optimization of the gold plating thickness for the use of both wire bonding and soldered interconnects on a flexible printed circuit board sample module. Wire bondability is typically better, when the gold plating thickness is greater than 30 μin.; however, the risk of problems with solder joint embrittlement becomes a concern with thick gold plating. In order to better understand the effect of the gold plating thickness on wire bondability and solder joint embrittlement, an evaluation was performed on samples with three ranges of gold plating thicknesses (10–20 μin., 20–30 μin., and 30–45 μin.), on flexible printed circuit board (PCB), substrates. Mechanical shear testing and metallurgical analyses were conducted on chip component solder joints in this three thickness gold study. Thermal shock and drop testing were conducted to evaluate the reliability of the sample modules. Drop testing is especially critical for determining the reliability of the sample modules, which are used in portable consumer electronics products. Reliability testing and metallurgical analyses have been performed to characterize the effect of gold embrittlement on the mechanical integrity of the solder joints with a gold content ranging from 1 to 4 wt.%.     

基于DOE和BP神经网络对Al线键合工艺优化

Al丝超声引线键合工艺被广泛地应用在大功率器件封装中,以实现大功率芯片与引 线框架之间的电互连.Al丝引线键合的质量严重影响功率器件的整体封装水平,对其工艺参数的优化具有重要工业应用意义.利用正交实验设计方法,对Al丝引线键合工艺中的三个最重要影响因数(超声功率P/DAC、键合时间t/ms、键合压力F/g)进行了正交实验设计,实验表明拉力优化后的工艺参数为:键合时间为40 ms,超声功率为25 DAC,键合压力为120g;剪切推力优化的工艺参数为:键合时间为50 ms,超声功率为40 DAC,键合压力为120 g.基于BP神经网络系统,建立了铝丝超声引线键合工艺的预测模型,揭示了Al丝超声键合工艺参数与键合质量之间的内在联系.网络训练结果表明训练预测值与实验值之间符合很好,检验样本的结果也符合较好,其误差基本控制在10%以内.     

Effect of Gold Stud Bump Topology on Reliability of Flip Chip on Flex Interconnects

The flip chip technique using conductive adhesives have emerged as a good alternative to solder flip chip methods. Different approaches of the interconnection mechanism using conductive adhesives have been developed. In this paper, test chips with gold stud bumps are flip-chipped with conductive adhesives onto a flexible substrate. An experimental study to characterize the bonding process parameters is reported. Initial results from the environmental studies show that thermal shock test causes negligible failure. On the other hand, high humidity test causes considerable failure in flip chip on flex assemblies. Improvements in the reliability of the assembly are achieved by modifying the shape of the gold stud bumps.     

InSb红外探测器芯片粘接工艺研究

基于InSb红外探测器的封装特点,采用正交试验法研究了芯片粘接过程中基板平整度、粘接剂抽真空时间、配胶时间、固化条件等工艺参数对芯片性能及可靠性的影响。通过计算极差和方差分析了各因素对芯片可靠性的影响大小。结果表明,固化条件对粘接后芯片的性能影响最大,其次是配胶时间,而抽真空时间和基板平整度影响相对较小。针对极差分析得出的较优参数组合和较差参数组合,利用X射线衍射(XRD)研究了不同参数组合对晶片粘接的应力大小,所得结果与正交试验一致。     

T/R组件基板电极区的互连可靠性

采用化学镀Ni/Pd/Au新工艺制作了T/R组件基板电极区,对比研究了在化学镀Ni/Au基板和Ni/Pd/Au基板上引线键合和钎焊的性能。结果显示:化学镀Ni/Pd/Au基板经过200℃烘烤处理6 h后,φ25μm金丝的引线键合强度大于0.08 N(8 gf),0402元件的焊点剪切强度大于4.9 N(500 gf),引线键合和钎焊性能均优于化学镀Ni/Au基板,有效地提高了T/R组件互连可靠性。     

Cost analysis: solder bumped flip chip versus wire bonding

The cost of wire bonding chips and solder bumped flip chips on boards or on organic substrates is studied. The effects of IC chip yields, gold and solder materials, and major equipment of these technologies on costs are examined. Useful equations and charts for determining the cost of and comparing the cost between these technologies are provided