High‐Mobility ZnO Thin Film Transistors Based on Solution‐processed Hafnium Oxide Gate Dielectrics

The properties of metal oxides with high dielectric constant (k) are being extensively studied for use as gate dielectric alternatives to silicon dioxide (SiO₂). Despite their attractive properties, these high‐k dielectrics are usually manufactured using costly vacuum‐based techniques. In that respect, recent research has been focused on the development of alternative deposition methods based on solution‐processable metal oxides. Here, the application of the spray pyrolysis (SP) technique for processing high‐quality hafnium oxide (HfO₂) gate dielectrics and their implementation in thin film transistors employing spray‐coated zinc oxide (ZnO) semiconducting channels are reported. The films are studied by means of admittance spectroscopy, atomic force microscopy, X‐ray diffraction, UV–Visible absorption spectroscopy, FTIR, spectroscopic ellipsometry, and field‐effect measurements. Analyses reveal polycrystalline HfO₂ layers of monoclinic structure that exhibit wide band gap (≈5.7 eV), low roughness (≈0.8 nm), high dielectric constant (k ≈ 18.8), and high breakdown voltage (≈2.7 MV/cm). Thin film transistors based on HfO₂/ZnO stacks exhibit excellent electron transport characteristics with low operating voltages (≈6 V), high on/off current modulation ratio (～10⁷) and electron mobility in excess of 40 cm² V^?1 s^?1.     

Pure‐Silica‐Zeolite MFI and MEL Low‐Dielectric‐Constant Films with Fluoro‐Organic Functionalization

The synthesis of organic‐functionalized pure‐silica‐zeolites (PSZs) with MFI‐ and MEL‐type structures for low‐k applications prepared through a direct‐synthesis method by adding a fluorinated silane to the synthesis solution is reported. The added fluorine functionality increases the hydrophobicity of the zeolites, which are characterized by scanning electron microscopy, X‐ray diffraction, ²⁹Si and ¹⁹F solid‐state NMR spectroscopy, nitrogen adsorption, and thermogravimetric analysis. The functionalized zeolite powders have low water content and calcined spin‐on films prepared from the functionalized nanoparticle suspensions exhibit higher water contact angles and lower k values (2.1 and 1.8 for the functionalized MFI‐ and MEL‐type zeolites, respectively) than PSZ films. The use of a direct‐synthesis method to decrease the moisture adsorption in the films eliminates the extra post‐spin‐on silylation steps that are traditionally used to render the zeolite films hydrophobic.     

Effects of Crystallinity in Spin‐On Pure‐Silica‐Zeolite MFI Low‐Dielectric‐Constant Films

Low‐dielectric‐constant (low‐κ) materials are a critical requirement for future generations of computer microprocessors. As a unique class of porous silicas, pure silica zeolites (PSZs) have been shown to be a promising low‐κ material with excellent mechanical strength (e.g., elastic modulus of 16–18 GPa) due to their crystalline nature. In the present study, we show for the first time that higher crystallinity of spin‐on PSZ MFI films leads to lower κ values and less moisture sensitivity—two critical properties of a porous low‐κ material. We have also advanced the two‐stage synthesis method to produce zeolite nanoparticles with high yield (77 %) and a small diameter (< 80 nm). A κ value of 1.6 is obtained from the silylated highly crystalline PSZ MFI film and the κ value only increases by 12.5 % after exposure to ambient conditions for a period of 24 h.     

MEL‐type Pure‐Silica Zeolite Nanocrystals Prepared by an Evaporation‐Assisted Two‐Stage Synthesis Method as Ultra‐Low‐k Materials

A MEL‐type pure‐silica zeolite (PSZ), prepared by spin‐on of nanoparticle suspensions, has been shown to be a promising ultra‐low‐dielectric‐constant (k) material because of its high mechanical strength, hydrophobicity, and chemical stability. In our previous works, a two‐stage synthesis method was used to synthesize a MEL‐zeolite nanoparticle suspension, in which both nanocrystal yield and particle size of the zeolite suspension increased with increasing synthesis time. For instance, at a crystal yield of 63%, the particle size is 80 nm, which has proved to be too large because it introduces a number of problems for the spin‐on films, including large surface roughness, surface striations, and large mesopores. In the current study, the two‐stage synthesis method is modified into an evaporation‐assisted two‐stage method by adding a solvent‐evaporation process between the two thermal‐treatment steps. The modified method can yield much smaller particle sizes (e.g., 14 vs. 80 nm) while maintaining the same nanocrystal yields as the two‐stage synthesis. Furthermore, the nanoparticle suspensions from the evaporation‐assisted two‐stage synthesis show a bimodal particle size distribution. The primary nanoparticles are around 14 nm in size and are stable in the final suspension with 60% solvent evaporation. The factors that affect nanocrystal synthesis are discussed, including the concentration, pH value, and viscosity. Spin‐on films prepared by using suspensions synthesized this way have no striations and improved elastic modulus (9.67 ± 1.48 GPa vs. 7.82 ± 1.30 GPa), as well as a similar k value (1.91 ± 0.09 vs. 1.89 ± 0.08) to the previous two‐stage synthesized films.     

Water‐Induced Scandium Oxide Dielectric for Low‐Operating Voltage n‐ and p‐Type Metal‐Oxide Thin‐Film Transistors

Solution‐processed metal‐oxide thin films based on high dielectric constant (k) materials have been extensively studied for use in low‐cost and high‐performance thin‐film transistors (TFTs). Here, scandium oxide (ScO_x) is fabricated as a TFT dielectric with excellent electrical properties using a novel water‐inducement method. The thin films are annealed at various temperatures and characterized by using X‐ray diffraction, atomic‐force microscopy, X‐ray photoelectron spectroscopy, optical spectroscopy, and a series of electrical measurements. The optimized ScO_x thin film exhibits a low‐leakage current density of 0.2 nA cm^?2 at 2 MV cm^?1, a large areal capacitance of 460 nF cm^?2 at 20 Hz and a permittivity of 12.1. To verify the possible applications of ScO_x thin films as the gate dielectric in complementary metal oxide semiconductor (CMOS) electronics, they were integrated in both n‐type InZnO (IZO) and p‐type CuO TFTs for testing. The water‐induced full oxide IZO/ScO_x TFTs exhibit an excellent performance, including a high electron mobility of 27.7 cm² V^?1 s^?1, a large current ratio (I_on/I_off) of 2.7 × 10⁷ and high stability. Moreover, as far as we know it is the first time that solution‐processed p‐type oxide TFTs based on a high‐k dielectric are achieved. The as‐fabricated p‐type CuO/ScO_x TFTs exhibit a large I_on/I_off of around 10⁵ and a hole mobility of 0.8 cm² V^?1 at an operating voltage of 3 V. To the best of our knowledge, these electrical parameters are among the highest performances for solution‐processed p‐type TFTs, which represents a great step towards the achievement of low‐cost, all‐oxide, and low‐power consumption CMOS logics.     

Layer‐Controlled and Wafer‐Scale Synthesis of Uniform and High‐Quality Graphene Films on a Polycrystalline Nickel Catalyst

Chemical vapor deposition (CVD) provides a synthesis route for large‐area and high‐quality graphene films. However, layer‐controlled synthesis remains a great challenge on polycrystalline metallic films. Here, a facile and viable synthesis of layer‐controlled and high‐quality graphene films on wafer‐scale Ni surface by the sequentially separated steps of gas carburization, hydrogen exposure, and segregation is developed. The layer numbers of graphene films with large domain sizes are controlled precisely at ambient pressure by modulating the simplified CVD process conditions and hydrogen exposure. The hydrogen exposure assisted with a Ni catalyst plays a critical role in promoting the preferential segregation through removing the carbon layers on the Ni surface and reducing carbon content in the Ni. Excellent electrical and transparent conductive performance, with a room‐temperature mobility of ≈3000 cm² V^?1 s^?1 and a sheet resistance as low as ≈100 Ω per square at ≈90% transmittance, of the twisted few‐layer grapheme films grown on the Ni catalyst is demonstrated.     

Amphiphilic Poly(p‐phenylene)s for Self‐Organized Porous Blue‐Light‐Emitting Thin Films

Micro‐ and nanostructuring of conjugated polymers are of critical importance in the fabrication of molecular electronic devices as well as photonic and bandgap materials. The present report delineates the single‐step self‐organization of highly ordered structures of functionalized poly(p‐phenylene)s without the aid of either a controlled environment or expensive fabrication methodologies. Microporous films of these polymers, with a honeycomb pattern, were prepared by direct spreading of the dilute polymer solution on various substrates, such as glass, quartz, silicon wafer, indium tin oxide, gold‐coated mica, and water, under ambient conditions. The polymeric film obtained from C₁₂PPPOH comprises highly periodic, defect‐free structures with blue‐light‐emitting properties. It is expected that such microstructured, conjugated polymeric films will have interesting applications in photonic and optoelectronic devices. The ability of the polymer to template the facile micropatterning of nanomaterials gives rise to hybrid films with very good spatial dispersion of the carbon nanotubes.     

High Performance Multi‐Level Non‐Volatile Polymer Memory with Solution‐Blended Ferroelectric Polymer/High‐k Insulators for Low Voltage Operation

Polymer ferroelectric‐gate field effect transistors (Fe‐FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next‐generation non‐volatile memory. Furthermore, polymer Fe‐FETs have been recently of interest owing to their capability of storing data in more than 2 states in a single device, that is, they have multi‐level cell (MLC) operation potential for high density data storage. However, among a variety of technological issues of MLC polymer Fe‐FETs, the requirement of high voltage for cell operation is one of the most urgent problems. Here, a low voltage operating MLC polymer Fe‐FET memory with a high dielectric constant (k) ferroelectric polymer insulator is presented. Effective enhancement of capacitance of the ferroelectric gate insulator layer is achieved by a simple binary solution‐blend of a ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (PVDF‐TrFE) (k ≈ 8) with a relaxer high‐k poly(vinylidene‐fluoride–trifluoroethylene–chlorotrifluoroethylene) (PVDF‐TrFE‐CTFE) (k ≈ 18). At optimized conditions, a ferroelectric insulator with a PVDF‐TrFE/PVDF‐TrFE‐CTFE (10/5) blend composition enables the discrete six‐level multi‐state operation of a MLC Fe‐FET at a gate voltage sweep of ±18 V with excellent data retention and endurance of each state of more than 10⁴ s and 120 cycles, respectively.     

Photocurrent enhancement in thin‐film silicon solar cells by combination of anti‐reflective sub‐wavelength structures and light‐trapping textures

Dielectric films with anti‐reflective sub‐wavelength structures are applied to thin‐film silicon solar cells to improve the light incoupling at the front surface. It is verified that modification of the refractive index of the incident medium using dielectric films with sub‐wavelength structures is beneficial to reduce the average reflectivity of Si solar cells with an anti‐reflective coating based on optical interference. It is also shown that the sub‐wavelength structure must be combined with a proper light‐trapping texture to enhance the absorption within thin‐film silicon solar cells. The effectiveness of dielectric films with sub‐wavelength structures is demonstrated by an increase of the short‐circuit current density of a microcrystalline silicon cell from 29.1 to 30.4 mA/cm² in a designated area of 1 cm². The optical interplay between the dielectric films and the light‐trapping textures is also discussed. Copyright © 2015 John Wiley & Sons, Ltd.     

Hexagonal Boron Nitride–Enhanced Optically Transparent Polymer Dielectric Inks for Printable Electronics

Solution‐processable thin‐film dielectrics represent an important material family for large‐area, fully‐printed electronics. Yet, in recent years, it has seen only limited development, and has mostly remained confined to pure polymers. Although it is possible to achieve excellent printability, these polymers have low (≈2–5) dielectric constants (ε_r). There have been recent attempts to use solution‐processed 2D hexagonal boron nitride (h‐BN) as an alternative. However, the deposited h‐BN flakes create porous thin‐films, compromising their mechanical integrity, substrate adhesion, and susceptibility to moisture. These challenges are addressed by developing a “one‐pot” formulation of polyurethane (PU)‐based inks with h‐BN nano‐fillers. The approach enables coating of pinhole‐free, flexible PU+h‐BN dielectric thin‐films. The h‐BN dispersion concentration is optimized with respect to exfoliation yield, optical transparency, and thin‐film uniformity. A maximum ε_r ≈ 7.57 is achieved, a two‐fold increase over pure PU, with only 0.7 vol% h‐BN in the dielectric thin‐film. A high optical transparency of ≈78.0% (≈0.65% variation) is measured across a 25 cm² area for a 10 μm thick dielectric. The dielectric property of the composite is also consistent, with a measured areal capacitance variation of <8% across 64 printed capacitors. The formulation represents an optically transparent, flexible thin‐film, with enhanced dielectric constant for printed electronics.     

A Polymer/Carbon‐Nanotube Ink as a Boron‐Dopant/Inorganic‐Passivation Free Carrier Selective Contact for Silicon Solar Cells with over 21% Efficiency

Traditional silicon solar cells extract holes and achieve interface passivation with the use of a boron dopant and dielectric thin films such as silicon oxide or hydrogenated amorphous silicon. Without these two key components, few technologies have realized power conversion efficiencies above 20%. Here, a carbon nanotube ink is spin coated directly onto a silicon wafer to serve simultaneously as a hole extraction layer, but also to passivate interfacial defects. This enables a low‐cost fabrication process that is absent of vacuum equipment and high‐temperatures. Power conversion efficiencies of 21.4% on an device area of 4.8 cm² and 20% on an industrial size (245.71 cm²) wafer are obtained. Additionally, the high quality of this passivated carrier selective contact affords a fill factor of 82%, which is a record for silicon solar cells with dopant‐free contacts. The combination of low‐dimensional materials with an organic passivation is a new strategy to high performance photovoltaics.     

Comparison of TiO2 and other dielectric coatings for buried‐contact solar cells: a review

This paper compares the optical, electronic, physical and chemical properties of dielectric thin films that are commonly used to enhance the performance of bulk silicon photovoltaic devices. The standard buried‐contact (BC) solar cell presents a particularly challenging set of criteria, requiring the dielectric film to act as: (i) an anti‐reflection (AR) coating; (ii) a film compatible with surface passivation; (iii) a mask for an electroless metal plating step; (iv) a diffusion barrier for achieving a selective emitter; (v) a film with excellent chemical resistance; (vi) a stable layer during high‐temperature processing. The dielectric coatings reviewed here include thermally grown silicon dioxide (SiO₂), silicon nitride deposited by plasma‐enhanced chemical vapour deposition (a‐ SiN_x :H) and low‐pressure chemical vapour deposition (Si₃N₄), silicon oxynitride (SiON), cerium dioxide (CeO₂), zinc sulphide (ZnS), and titanium dioxide (TiO₂). While TiO₂ dielectric coatings exhibit the best optical performance and a simple post‐deposition surface passivation sequence has been developed, they require an additional sacrificial diffusion barrier to survive the heavy groove diffusion step. A‐ SiN_x :H affords passivation through its high fixed positive charge density and large hydrogen concentration; however, it is difficult to retain these electronic benefits during lengthy high‐temperature processing. Therefore, for the BC solar cell, Si₃N₄ films would appear to be the best choice of dielectric films common in industrial use. Copyright © 2004 John Wiley & Sons, Ltd.     

Novel Method of Preparation of Gold‐Nanoparticle‐Doped TiO2 and SiO2 Plasmonic Thin Films: Optical Characterization and Comparison with Maxwell–Garnett Modeling

SiO₂ and TiO₂ thin films with gold nanoparticles (NPs) are of particular interest as photovoltaic materials. A novel method for the preparation of spin‐coated SiO₂–Au and TiO₂–Au nanocomposites is presented. This fast and inexpensive method, which includes three separate stages, is based on the in situ synthesis of both the metal‐oxide matrix and the Au NPs during a baking process at relatively low temperature. It allows the formation of nanocomposite thin films with a higher concentration of Au NPs than other methods. High‐resolution transmission electron microscopy studies revealed a homogeneous distribution of NPs over the film volume along with their narrow size distribution. The optical manifestation of localized surface plasmon resonance was studied in more detail for TiO₂‐based Au‐doped nanocomposite films deposited on glass (in absorption and transmittance) and silicon (in specular reflectance). Maxwell–Garnett effective‐medium theory applied to such metal‐doped nanocomposite films describes the peculiarities of the experimental spectra, including modification of the antireflective properties of bare TiO₂ films deposited on silicon by varying the concentration of metal NPs. The antireflective capabilities of the film are increased after a wet etching process.     

Two‐Dimensionally Ordered Copper Grid Patterns Prepared via Electroless Deposition Using a Colloidal‐Crystal Film as the Template

Two‐dimensionally ordered copper grid patterns with different pore sizes and thickness have been fabricated via electroless copper deposition using a colloidal‐crystal film as the template. The pore size of the grid can be adjusted by altering the deposition time. The copper films, with thicknesses of ≈ 100–130 nm and pore sizes of ≈ 100 nm, are flexible and can be peeled off a silicon wafer and rolled up into a reel. Three‐dimensionally ordered porous copper materials have also been prepared using a similar method.     

Liquid‐Tin‐Assisted Molten Salt Electrodeposition of Photoresponsive n‐Type Silicon Films

Production of silicon film directly by electrodeposition from molten salt would have utility in the manufacturing of photovoltaic and optoelectronic devices owing to the simplicity of the process and the attendant low capital and operating costs. Here, dense and uniform polycrystalline silicon films (thickness up to 60 µm) are electrodeposited on graphite sheet substrates at 650 °C from molten KCl–KF‐1 mol% K₂SiF₆ salt containing 0.020–0.035 wt% tin. The growth of such high‐quality tin‐doped silicon films is attributable to the mediation effect of tin in the molten salt electrolyte. A four‐step mechanism is proposed for the generation of the films: nucleation, island formation, island aggregation, and film formation. The electrodeposited tin‐doped silicon film exhibits n‐type semiconductor behavior. In liquid junction photoelectrochemical measurement, this material generates a photocurrent about 38–44% that of a commercial n‐type Si wafer.     

Heat‐Assisted Photoacidic Oxidation Method for Tailoring the Surface Chemistry of Polymer Dielectrics for Low‐Power Organic Soft Electronics

The use in low‐power soft electronics of the appropriate insulating polymer materials with a high dielectric constant (k) is considered a practical alternative to that of inorganic dielectric materials, which are brittle and have high processing temperatures. However, the polar surfaces of typical high‐k polymer insulators are problematic. Further, it is a huge challenge to control their surface properties without damage because of their soft and chemically fragile nature. Here, a heat‐assisted photoacidic oxidation method that can be used to effectively oxidize the outermost surfaces of high‐k rubbery polymer films without degradation is presented. The oxidized surfaces prepared with the developed method contain large numbers of hydroxyl groups that enable the subsequent growth of dense and ordered self‐assembled monolayers (SAMs) consisting of organosilanes. The whole process modifies the surface characteristics of polymer dielectrics effectively. The mechanisms of the oxidation of polymer surfaces and the subsequent SAM growth process are investigated. The resulting surface‐tailored rubbery dielectrics exhibit superior electrical characteristics when used in organic transistors. These results demonstrate that this method can be used to realize practical soft organic electronics based on high‐k polymer dielectrics.     

High K Capacitors and OFET Gate Dielectrics from Self‐Assembled BaTiO3 and (Ba,Sr)TiO3 Nanocrystals in the Superparaelectric Limit

Nanodielectrics is an emerging field with applications in capacitors, gate dielectrics, energy storage, alternatives to Li‐ion batteries, and frequency modulation in communications devices. Self‐assembly of high k dielectric nanoparticles is a highly attractive means to produce nanostructured films with improved performance—namely dielectric tunability, low leakage, and low loss—as a function of size, composition, and structure. One of the major challenges is conversion of the nanoparticle building block into a reliable thin film device at conditions consistent with integrated device manufacturing or plastic electronics. Here, the development of BaTiO₃ and (Ba,Sr)TiO₃ superparaelectric uniform nanocrystal (8–12 nm) films prepared at room temperature by evaporative driven assembly with no annealing step is reported. Thin film inorganic and polymer composite capacitors show dielectric constants in the tunable range of 10–30, dependent on composition, and are confirmed to be superparaelectric. Organic thin film transistor (TFT) devices on flexible substrates demonstrate the readiness of nanoparticle‐assembled films as gate dielectrics in device fabrication.     

>16% thin‐film epitaxial silicon solar cells on 70‐cm2 area with 30‐µm active layer,porous silicon back reflector,and Cu‐based top‐contact metallization

We demonstrate the use of a copper‐based metallization scheme for the specific application of thin‐film epitaxial silicon wafer equivalent (EpiWE) solar cells with rear chemical vapor deposition emitter and conventional POCl₃ emitter. Thin‐film epitaxial silicon wafer equivalent cells are consisting of high‐quality epitaxial active layer of only 30 µm, beneath which a highly reflective porous silicon multilayer stack is embedded. By combining Cu‐plating metallization and narrow finger lines with an epitaxial cell architecture including the porous silicon reflector, a J_sc exceeding 32 mA/cm² was achieved. We report on reproducible cell efficiencies of >16% on >70‐cm² cells with rear epitaxial chemical vapor deposition emitters and Cu contacts. Copyright © 2011 John Wiley & Sons, Ltd.     

Phthalocyanine‐Based 2D Conjugated Metal‐Organic Framework Nanosheets for High‐Performance Micro‐Supercapacitors

2D conjugated metal‐organic frameworks (2D c‐MOFs) are emerging as a novel class of conductive redox‐active materials for electrochemical energy storage. However, developing 2D c‐MOFs as flexible thin‐film electrodes have been largely limited, due to the lack of capability of solution‐processing and integration into nanodevices arising from the rigid powder samples by solvothermal synthesis. Here, the synthesis of phthalocyanine‐based 2D c‐MOF (Ni₂[CuPc(NH)₈]) nanosheets through ball milling mechanical exfoliation method are reported. The nanosheets feature with average lateral size of ≈160 nm and mean thickness of ≈7 nm (≈10 layers), and exhibit high crystallinity and chemical stability as well as a p‐type semiconducting behavior with mobility of ≈1.5 cm² V^?1 s^?1 at room temperature. Benefiting from the ultrathin feature, the nanosheets allow high utilization of active sites and facile solution‐processability. Thus, micro‐supercapacitor (MSC) devices are fabricated mixing Ni₂[CuPc(NH)₈] nanosheets with exfoliated graphene, which display outstanding cycling stability and a high areal capacitance up to 18.9 mF cm^?2; the performance surpasses most of the reported conducting polymers‐based and 2D materials‐based MSCs.     

Low‐Temperature,Nontoxic Water‐Induced Metal‐Oxide Thin Films and Their Application in Thin‐Film Transistors

Here, a simple, nontoxic, and inexpensive “water‐inducement” technique for the fabrication of oxide thin films at low annealing temperatures is reported. For water‐induced (WI) precursor solution, the solvent is composed of water without additional organic additives and catalysts. The thermogravimetric analysis indicates that the annealing temperature can be lowered by prolonging the annealing time. A systematic study is carried out to reveal the annealing condition dependence on the performance of the thin‐film transistors (TFTs). The WI indium‐zinc oxide (IZO) TFT integrated on SiO₂ dielectric, annealed at 300 °C for 2 h, exhibits a saturation mobility of 3.35 cm² V^?1 s^?1 and an on‐to‐off current ratio of ≈10⁸. Interestingly, through prolonging the annealing time to 4 h, the electrical parameters of IZO TFTs annealed at 230 °C are comparable with the TFTs annealed at 300 °C. Finally, fully WI IZO TFT based on YO_x dielectric is integrated and investigated. This TFT device can be regarded as “green electronics” in a true sense, because no organic‐related additives are used during the whole device fabrication process. The as‐fabricated IZO/YO_x TFT exhibits excellent electron transport characteristics with low operating voltage (≈1.5 V), small subthreshold swing voltage of 65 mV dec^?1 and the mobility in excess of 25 cm² V^?1 s^?1.