FPGA-based hardware accelerator for high-performance data-stream processing

An approach to solving high-performance data-stream processing is proposed based on hardware solutions that use a field-programmable gate array. The described HDG hardware solution was successfully applied to video data streams. The computation capacity of the employed crystal of the Xilinx Virtex5 family is sufficient for the real-time implementation of image analysis algorithms based on the mean-square deviation with a frequency of up to 100 frames per second.     

Detection of vowel-like speech: an efficient hardware architecture and it's FPGA prototype

Microsystem Technologies - In this paper, a robust vowel-like speech (VLS) detection method using modified non-local means normalization factor (MNLM-NF) and it’s FPGA prototype is proposed....     

Layered tile architecture for efficient hardware spiking neural networks

Spiking Neural Network (SNN) is the most recent computational model that can emulate the behaviour of biological neuron system. However, its main drawback is that it is computationally intensive, which limits the system scalability. This paper highlights and discusses the importance and significance of emulating SNNs in hardware devices. A layer-level tile architecture (LTA) is proposed for hardware-based SNNs. The LTA employs a two-level sharing mechanism of computing components at the synapse and neuron levels, and achieves a trade-off between computational complexity and hardware resource costs. The LTA is implemented on a Xilinx FPGA device. Experimental results demonstrate that this approach is capable of scaling to large hardware-based SNNs.     

A new software/hardware architecture for real time image processing of wide area airborne camera images

This paper describes a new software/hardware architecture for processing wide area airborne camera images in real time. The images under consideration are acquired from the 3K-camera system developed at DLR (German Aerospace Center). It consists of three off-the-shelf cameras, each of it delivers 16 Mpixel three times a second. One camera is installed in nadir, whereas the other two cameras are looking in side direction. Main applications of our system are supposed to be automotive traffic monitoring, determining the workload of public road networks during mass events, or obtaining a survey of damages in disaster areas in real time. Altogether, this demands a fast image processing system on the aircraft, because the amount of original high resolution images can not be sent to ground by up-to-date transfer mode systems. The on-board image processing system is distributed over a local network. On each PC several modules are running concurrently. In order to synchronize several processes and to assure access to commonly used data, a new distributed middleware for real time image processing is introduced. Two sophisticated modules one for orthorectification of images and one for traffic monitoring are explained in more detail. The orthorectification and mosaicking is executed on the fast graphics processing unit on one PC, whereas the traffic monitoring module runs on another PC in the on-board network. The resulting image data and evaluated traffic parameters are sent to a ground station in near real time and are distributed to the involved users. Thus, with the here suggested software/hardware system it becomes possible to support rescue forces and security forces in disaster areas or during mass events in near real time.

A hardware architecture for real-time image compression using a searchless fractal image coding method

In this paper we present a novel hardware architecture for real-time image compression implementing a fast, searchless iterated function system (SIFS) fractal coding method. In the proposed method and corresponding hardware architecture, domain blocks are fixed to a spatially neighboring area of range blocks in a manner similar to that given by Furao and Hasegawa. A quadtree structure, covering from 32 × 32 blocks down to 2 × 2 blocks, and even to single pixels, is used for partitioning. Coding of 2 × 2 blocks and single pixels is unique among current fractal coders. The hardware architecture contains units for domain construction, zig-zag transforms, range and domain mean computation, and a parallel domain-range match capable of concurrently generating a fractal code for all quadtree levels. With this efficient, parallel hardware architecture, the fractal encoding speed is improved dramatically. Additionally, attained compression performance remains comparable to traditional search-based and other searchless methods. Experimental results, with the proposed hardware architecture implemented on an Altera APEX20K FPGA, show that the fractal encoder can encode a 512 × 512 × 8 image in approximately 8.36 ms operating at 32.05 MHz. Therefore, this architecture is seen as a feasible solution to real-time fractal image compression.

Dynamically reconfigurable dataflow architecture for high-performance digital signal processing

In this paper a dataflow architecture is introduced that maps efficiently onto multi-FPGA platforms and is composed of communication channels which can be dynamically adapted to the dataflow of the algorithm. The reconfiguration of the topology can be accomplished within a single clock cycle while DSP operations are in progress. Finally, the programmability and scalability of the proposed architecture is demonstrated by a high-performance parallel FFT implementation.     

硬件加速CNN实时图像处理方法

针对CNN算法计算量大、运算耗时长、对PC资源依赖程度高的缺点,提出一种基于Vivado高层次综合硬件加速CNN实时图像处理的方法。将训练好的CNN模型中各参数提取并导入Vivado HLS中,利用C++语言按照Vivado HLS处理规范编写CNN识别算法,实现由FPGA的逻辑资源生成CNN算法对应的RTL级硬件电路,通过Vivado HLS仿真窗口进行CNN识别算法的测试,评估硬件加速CNN算法实时图像处理的效果。实验结果表明,该方法识别MNIST库中10 000例手写体样本仅需8.69s,PC端识别相同样本的时间为30s,该方法有利于实时图像处理算法向硬件化高性能处理平台ZynqSOC移植。     

Dynamic hardware plugins: exploiting reconfigurable hardware for high-performance programmable routers

This paper presents the dynamic hardware plugins (DHP) architecture for implementing multiple networking applications in hardware at programmable routers. By enabling multiple applications to be dynamically loaded into a single hardware device, the DHP architecture provides a scalable mechanism for implementing high-performance programmable routers. The DHP architecture is presented within the context of a programmable router architecture which processes flows in both software and hardware. Implementation options are described as well as the prototype testbed at Washington University in Saint Louis which utilizes the partial reconfiguration capability of modern field programmable gate arrays.     

Efficient hardware architecture of 2D-scan-based wavelet watermarking for image and video

This paper describes an efficient hardware architecture of 2D-Scan-based-Wavelet watermarking for image and video. The potential application for this architecture includes broadcast monitoring of video sequences for High Definition Television (HDTV) and DVD protection and access control. The proposed 2D design allows even distribution of the processing load onto a set of filters, with each set performing the calculation for one dimension according to the scan-based process. The video protection is achieved by the insertion of watermarks bank within the middle frequency of wavelet coefficients related to video frames by their selective quantization. The 2-D DWT is applied for both video stream and watermark in order to make the watermarking scheme robust and perceptually invisible. The proposed architecture has a very simple control part, since the data are operated in a row-column-slice fashion. This organization reduces the requirement of on-chip memory. In addition, the control unit selects which coefficient to pass to the low-pass and high-pass filters. The on-chip memory will be small as compared to the input size since it depends solely on the filter sizes. Due to the pipelining, all filters are utilized for 100% of the time except during the start-up and wind-down times. The major contribution of this research is towards the selection of appropriate real time watermarking scheme and performing a trade-off between the algorithmic aspects of our proposed watermarking scheme and the hardware implementation technique. The hardware architecture is designed, as a watermarking based IP core with the Avalon interface related to NIOS embedded processor, and tested in order to evaluate the performance of our proposed watermarking algorithm. This architecture has been implemented on the Altera Stratix-II Field Programmable Gate Array (FPGA) prototyping board. Experimental results are presented to demonstrate the capability of the proposed watermarking system for real time applications and its robustness against malicious attacks.     

Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing

Technology evolution makes possible the integration of heterogeneous components as programmable elements (processors), hardware dedicated blocks, hierarchical memories and buses. Furthermore, an optimized reconfigurable logic core embedded within a System-on-Chip will associate the performances of dedicated architecture and the flexibility of programmable ones. In order to increase performances, some of the applications are carried out in hardware, using dynamically reconfigurable logic, rather than software, using programmable elements. This approach offers a suitable hardware support to design malleable systems able to adapt themselves to a specific application. This article makes a synthesis of the Ardoise project. The first objective of Ardoise project was to design and to produce a dynamically reconfigurable platform based on commercial FPGAs. The concept of dynamically reconfigurable architecture depends partially on new design methodologies elaboration as well as on the programming environment. The platform architecture was designed to be suitable for real-time image processing. The article outlines mainly the Ardoise tools aspect: development environment and real-time management of the hardware tasks. The proposed methodology is based on a dynamic management of tasks according to an application scenario written using C++ language.

VLSI architecture for real-time image and video processing systems

This paper discusses the challenges of the design of real-time image and video processing systems and reviews some practical design approaches for these systems.     

A software architecture for user transparent parallel image processing

This paper describes a software architecture that allows image processing researchers to develop parallel applications in a transparent manner. The architecture's main component is an extensive library of data parallel low level image operations capable of running on homogeneous distributed memory MIMD-style multicomputers. Since the library has an application programming interface identical to that of an existing sequential library, all parallelism is completely hidden from the user.The first part of the paper discusses implementation aspects of the parallel library, and shows how sequential as well as parallel operations are implemented on the basis of so-called parallelizable patterns. A library built in this manner is easily maintainable, as extensive code redundancy is avoided. The second part of the paper describes the application of performance models to ensure efficiency of execution on all target platforms. Experiments show that for a realistic application performance predictions are highly accurate. These results indicate that the core of the architecture forms a powerful basis for automatic parallelization and optimization of a wide range of imaging software.     

A low complexity hardware architecture of K-means algorithm for real-time satellite image segmentation

Multimedia Tools and Applications - The Real time monitoring of forest area, coastal regions, sea, river basins, nation borders etc. helps in quick determination of devastations caused by natural...     

A new approach for design of an efficient FPGA-based reconfigurable convolver for image processing

The Journal of Supercomputing - Two-dimensional convolution plays a fundamental role in different image processing applications. Image convolving with different kernel sizes enriches the overall...     

A dedicated hardware architecture for real-time auto-focusing using an FPGA

The auto-focus is a fundamental function of a camera system which is required to photograph a clear image of an object. To obtain the optimal focus of a specific region within an image, the sharpness of the region must be measured. Since the sharpness represents the difference between a pixel and its neighbors, multiple pixel references occur while evaluating each pixel. To compensate for the processing bottleneck caused by this repetitive memory reference, this paper presents a dedicated hardware architecture for real-time auto-focusing. The proposed system processes the incoming pixel simultaneously with its neighboring pixels based on its parallelized window processing architecture. In addition, the proposed system performs an adaptive thresholding-based sharpness function with multiple windows to achieve accuracy and robustness. The proposed system is compared to several conventional pixel-based auto-focusing systems under various environmental conditions.     

Hybrid storage architecture and efficient MapReduce processing for unstructured data

As we are now entering the era of data deluge, how to efficiently manage these massive data is becoming a great challenge, especially for the exponentially growing unstructured data, which is far more than structured and semi-structured data. However, unstructured data is more complex for its variety. That is to say, different types of unstructured data have different file size, type and usage, which need different storage and processing for high efficiency. In this paper, we propose a hybrid storage architecture to store the pervasive unstructured data. This hybrid architecture integrates various kinds of data stores within a unified framework, where each type of unstructured data can find its suitable placement policy and it is transparent to users. In addition, we present several partitioning strategies based on the unified framework, which are beneficial to the MapReduce-based batch processing for these unstructured data. The experiments demonstrate that it is possible to build an efficient and smart system through the hybrid architecture and the partitioning strategies.     

ImAge: an extensible agent-based architecture for image retrieval

We present an open and extensible architecture, ImAge, for content-based image retrieval in a distributed environment. The architecture proposes the use of system components with standard public interfaces for implementing retrieval functionality. The standardization of the components and their encapsulation in autonomous software agents result in functional stratification and easy extensibility. Collaboration of the independent retrieval resources in ImAge results in enhanced system capability. Reuse of existing retrieval resources is achieved by encapsulating them in agents with standard interfaces. The addition of independent agents with domain knowledege adds the capability of processing conceptual queries, while reusing the existing system components for feature-based retrieval. A communication protocol allows the declaration of the capabilities of the system components and negotiations for optimal resource selection for solving a retrieval problem. The use of mobile agents alleviates network bottlenecks. This paper describes a prototype implementation that validates the architecture.     

Video image processing with the Sonic architecture

Current industrial video-processing systems use a mixture of high-performance workstations and application-specific integrated circuits. However, video image processing in the professional broadcast environment requires more computational power and data throughput than most of today's general-purpose computers can provide. In addition, using ASICs for video image processing is both inflexible and expensive. Configurable computing offers an appropriate alternative for broadcast video image editing and manipulation by combining the flexibility, programmability, and economy of general-purpose processors with the performance of dedicated ASICs. Sonic is a configurable computing system that performs real-time video image processing. The authors describe how it implements algorithms for two-dimensional linear transforms, fractal image generation, filters, and other video effects. Sonic's flexible and scalable architecture contains configurable processing elements that accelerate software applications and support the use of plug-in software     

VGL: a high-performance graph processing framework for the NEC SX-Aurora TSUBASA vector architecture

The Journal of Supercomputing - Developing efficient graph algorithms implementations is an extremely important problem of modern computer science, since graphs are frequently used in various...