FC-CBGA封装中高速差分信号过孔的设计与优化

对FC-CBGA封装中高速差分信号过孔的设计与优化问题进行研究,分析了采用堆叠孔、增加地回流孔和增大过孔反焊盘尺寸这三种优化方法对减小电容和电感不连续性,以提高过孔电性能的具体影响.时频域仿真验证了所述优化方法能够有效降低高速差分信号插入损耗及回波损耗,提高信号过孔阻抗,改善高速差分信号传输性能.     

高速差分过孔的仿真分析

高速差分信号传输中也存在着信号完整性问题。差分过孔在频率很高的时候会明显地影响差分信号的完整性,现介绍差分过孔的等效RLC模型,在HFSS中建立了差分过孔仿真模型并分析了过孔尤其过孔长度对信号完整性的影响。     

高速PCB单端过孔研究

在高速数字电路设计中,过孔的寄生电容、电感的影响不能忽略,过孔在传输路径上表现为阻抗不连续的断点,会产生信号的反射、延时、衰减等信号完整性问题。文章采用矢量网络分析仪研究了过孔长度、过孔孔径、焊盘/反焊盘直径对过孔阻抗的影响。通过在信号孔旁增加接地孔,为过孔电流提供回路方法,提高过孔阻抗的连续性,并有效降低过孔损耗。此外,文章还探讨了过孔多余短柱对过孔阻抗及损耗的影响。本研究可为高速数字电路过孔设计和优化提供依据。     

高速信号过孔对信号影响因素研究

影响信号完整性的因素有很多,其中过孔结构对信号影响越来越明显,如何进行有效的过孔设计从而使过孔阻抗与激励源阻抗配从而达到信号完整性已经成为当今PCB设计业界中的一个热门课题。文章通过Ansys公司的HFSS仿真软件,利用仿真方法分析不同信号过孔结构对高速信号的影响,并对过孔残桩长度（stub）,反焊盘,焊盘的不同大小对信号差损影响程度做了进一步研究。     

高速PCB中的过孔设计研究

传输线的不连续问题已成为当今高速数字设计研究的重点,尤其是高速多层板中的过孔结构。随着频率的增长和信号上升沿的变陡,过孔带来的阻抗不连续会引起信号的反射,严重影响系统的性能和信号完整性。文章运用全波电磁仿真软件HFSS,对多种过孔结构进行了全面的研究。通过建立三维物理模型,分析了过孔直径、过孔长度和多余的过孔短柱几种关键设计参数对高速电路的信号完整性的影响。     

PCB布线中的过孔和电容效应分析和结构优化

在多层PCB布线中,过孔和电容是常见的不连续结构。信号线在不同平面间转换传输路径时,过孔与回流层之间的寄生电容与寄生电感将引起信号完整性的相关问题;而常用的传输线上的AC耦合电容等,引入了阻抗突变的结构,由此带来了反射等相关问题。通过对多层PCB上的过孔进行建模仿真,研究不同变量对过孔性能的影响趋势,以协助信号完整性问题的分析;通过对电容阻抗突变处进行不同形式的补偿,仿真和测试结果相验证,得到提高信号传输质量的解决方案。     

SerDes链路中的过孔设计

随着SerDes链路信号传输速率的提升,PCB复杂度增加,信号越高走线和过孔设计对其正确传输的影响就越大,因此走线和过孔设计的研究就越发重要。文章通过搭建SerDes链路四级过孔走线模型,通过仿真得出,过孔的引入导致SerDes链路阻抗突变,码间串扰严重,设计中应尽量避免过孔的使用,如无法避免可以采用背钻和消盘处理,在一定范围内提高SerDes链路阻抗一致性,提升信号质量。     

高速BGA封装与PCB差分互连结构的设计与优化

随着电子系统通信速率的不断提升,BGA封装与PCB互连区域的信号完整性问题越来越突出。针对高速BGA封装与PCB差分互连结构进行设计与优化,着重分析封装与PCB互连区域差分布线方式,信号布局方式,信号孔/地孔比,布线层与过孔残桩这四个方面对高速差分信号传输性能和串扰的具体影响。利用全波电磁场仿真软件CST建立3D仿真模型,最后时频域仿真验证了所述的优化方法能够有效改善高速差分信号传输性能,减小信号间串扰,实现更好的信号隔离。     

多层PCB介质基板中嵌入高K材料对信号完整性的影响

采用数值仿真分析了多层PCB的电源/地平面中嵌入高K材料对过孔转换信号完整性的影响。研究了电源/地平面间的介质层整体采用高介电常数(高K)材料时信号过孔的S参数,并提出了两种局部添加高K材料的方法,一是在过孔周围布置一个包围过孔的介质柱,二是在过孔周围均匀布置若干个小介质柱。计算结果表明,介质层整体采用高K材料会引起较多的谐振,信号完整性变差;当嵌入介质材料的介电常数足够大时,在过孔周围局部嵌入高K材料的方法可明显增强信号完整性,其中,包围过孔的单个介质柱在高频时的性能良好,而在过孔周围嵌入多个小介质柱在低频时的效果较好。     

Cadence与Ansoft协同仿真信号完整性问题研究

本文首先介绍了印制板中过孔的一些相关理论以及由它引起的信号完整性问题,接着在Cadence软件中针对过孔布了两段徽带线并在时域进行仿真,最后把电路板模型导入的designer和HFSS中,同时对该电路板的表面电流、场强和散射参数矩阵进行了分析,从中可以看出过孔对信号的影响.     

差分过孔的结构分析与优化

针对差分过孔引起的阻抗不连续以及过孔残桩引起的信号反射问题，通过过孔反焊盘补偿设计及端接过孔残桩减小了差分过孔及残桩引起的反射，改善了接收信号的质量。通过对比差分过孔优化设计前后的频域传输参数和时域信号眼图，说明了本方法的有效性及实用性。     

Modeling and optimization of via formation in dielectrics by laser ablation using neural networks and genetic algorithms

Laser ablation is an effective process for forming vias in dielectric layers during the fabrication of multilayer substrates in microsystems packaging. In this paper, vias with diameters of 10-50 /spl mu/m are ablated in DuPont Kapton E polyimide using an Anvik HexScan 2150 SXE excimer laser operating at 308 nm. A statistical experiment employing a 2/sup 5-1/ fractional factorial design is conducted to determine the significance of laser fluence, shot frequency, number of pulses, and the vertical and horizontal positions of the debris removal system on the ablated thickness of the dielectric, top via diameter, via wall angle, and via resistance. Resistance measurements on metal deposited in ablated vias are performed to characterize via quality. Neural networks (NNs) are trained using the error back-propagation algorithm to model the ablation process using the measurement data collected from the experiment. Genetic algorithms are then utilized in conjunction with the NN models to derive optimized process recipes for achieving target responses. The recipes identified are subsequently verified by experiment. These optimized recipes are found to improve ablation results by as much as 40% for the ablated film thickness, 30% for via diameter, 9% for via wall angle, and more than 100% for via resistance.     

Optimization of via distribution and stacked via in multi-layered P/G networks

The usage of via stack was not carefully studied in previous multi-layered P/G (Power/Ground) network designs. However, with feature size scaling down, the resistance of via is increasing quickly and their influence on voltage drop of P/G networks has become obvious. In this paper, two optimization techniques for via placement are proposed, which are proved to be helpful in reducing on die voltage drop. Firstly, an efficient heuristic algorithm based on sensitivity analysis is presented to optimize via distribution in early design stage. Compared with even distribution design strategies, averagely the heuristic algorithm can reduce the worst voltage drop by 8.43% without adding more vias. Secondly, experiments demonstrated that using stacked vias in nonadjacent layers is powerful in eliminating “hot” areas which suffer from large voltage drop. Based on this observation, a heuristic algorithm is developed to further reduce the worst voltage drop. Experiments show that voltage drop distribution can be well optimized by combining these two strategies together.     

Analysis of a large number of vias and differential signaling in multilayered structures

A method is presented for full-wave modeling of vertical vias in multilayered circuits. The analysis of the interior problem is based upon the cylindrical wave expansion of the magnetic field Green's function. The multiple interaction among vertical vias is modeled by the Foldy-Lax scattering formula. Multilayered effects are included by using cascaded network of the single-layer components. The exterior problem of the via and the transmission line is analyzed using the method of moments approach. The exterior and interior problems are combined into a system of equations to facilitate the solution of a large number of vias. Using this approach, the scattering matrix of problems of several thousand vias can be calculated with moderate CPU and memory requirement. Numerical results have been obtained for different via configurations and for a large range of frequency. Also illustrated are results for common and differential mode in differential signaling with surrounding idle and shorting vias.     

Reliability evaluation of tungsten donut-via as an element of the highly robust metallization

The typical via layout in CMOS technology with AlCu-metallizations and tungsten via is cylindrical. Common vias have a size as small as possible in the related process. More challenging application, temperature and mission profiles require higher robustness of a metallization [1,2]. Via arrays of small common vias are in use to the transfer of higher currents [3]. But the typical via array layout is not the best layout for applications which are faced to high mechanical stress because via arrays metal layer connections make these parts in the stack inflexible.The developed so called highly robust metallization is optimized for applications with extended operating conditions regarding higher currents and temperatures as well as mechanical stress [4]. Donut-Vias are elements of the highly robust metallization for the interconnection of highly robust metal lines. The paper shows the layout of a Donut-Via and explains the benefits and limits of the new layout by simulation and test results.     

过孔阻抗控制及其对信号完整性的影响

传输线的连续性问题是高速数字电路设计的重点,尤其是高速多层PCB中的过孔结构。随频率的增加和上升时间的缩短,过孔阻抗不连续、寄生电容和电感会引起信号反射和衰减,并导致信号完整性问题。本研究采用矢量网络分析仪研究了单端微带线上过孔孔径、焊盘、反焊盘大小对阻抗连续性的影响,并通过为过孔信号提供返回路径,提高了过孔阻抗连续性与信号完整性。     

多芯片组件布线算法研究

该文以多芯片组件布线中的四通孔(V4R)算法为基础,针对其布线结果不均匀、产生多余噪声的缺陷,通过引入PST(Priority Search Tree)和LEA(Left Edge Algorithm)方法,移除过孔或拐角,减小布线层数,减少噪声,以达到总体布线结果优化。计算机模拟结果表明,优化后的算法有效利用了布线空间,在电特性方面使延时和噪声均得到减小。     

Electromigration reliability of tungsten and aluminum vias andimprovements under AC current stress

The reliability with respect to electromigration failure of tungsten and aluminum vias under DC, pulse-DC, and AC stressing has been studied using Kelvin test structures. The results indicate that although W-plug vias can eliminate the step coverage problem, this metallization system is not ideal because the intermetallic contact represents an undesirable flux divergence location for electromigration. Al vias are more reliable than W-plug vias with respect to electromigration failure. The unidirectional 50% duty factor pulse-DC lifetime is found to be twice the DC lifetime in the low-frequency region (<200 Hz) and four times the DC lifetime in the normal frequency region (> 10 kHz). The via lifetimes under bidirectional stressing current are found to be orders of magnitude longer than DC lifetimes under the same stressing current density for both W and Al vias. All the observations are in agreement with a vacancy relaxation model     

Electromigration performance of Al–Si–Cu filled vias with titanium glue layer

Electromigration performance of vias filled with high temperature (480°C) sputtered Al alloys on Ti glue layers was investigated in comparison with W-stud vias. Electromigration lifetime and failure mode are quite different according to via structures and kinds of Al alloys used. Electromigration lifetime of W-stud via chain and Al–Cu filled via chain depends on the via to via distances, while that of Al–Si–Cu filled via chain does not depend on the via to via distances. Failure mode observations revealed that voids were formed only at a few locations in the test structure in Al–Si–Cu filled via chain while voids were formed at every via in W-stud via chains and Al–Cu filled via chains. It is supposed that Al moves through the Al–Si–Cu filled vias during electromigration test in spite of the existence of the Ti glue layer at the via bottom. The Al transportation, however, was prohibited at W-stud vias and Al–Cu filled vias. Glue Ti deposited at via bottom was converted to Al–Ti–Si alloy in Al–Si–Cu filled vias, while Al₃Ti alloy was formed at Al–Cu filled via bottom. It is speculated that Al transportation occurs through via bottom Al–Ti–Si alloy layer during electromigration test in the case of Al–Si–Cu filled vias.