红外焦平面探测器杜瓦组件的热致破坏及其环境试验

红外探测器的环境耐受能力取决于设计和制造中完整有效的环境耐受措施,环境试验与评价验证了其在极端环境作用下能正常工作的能力。研制、生产和使用各阶段的试验目的不同,试验施加应力的大小不同,必须进行环境自然条件和诱发条件测量、温度响应特性调查和试验环境分析,选择正确、合理和必要的设计与试验环境条件,以尽可能产生最适合的试验数据,保证顾客所需的质量水平和有价格竞争力的可用性。运用288×4红外焦平面杜瓦组件温度响应试验实测数据和时间常数方法,计算分析它的温度稳定时间,指出空气介质温度循环筛选或温度冲击试验,不能在红外探测器的功能部件上施加大于10 ℃/min的温度急剧变化应力,高温工作状态的温度变化速率大于50 ℃/min对冷头部分的缺陷筛选效果更好。试验结果表明,真空完好性恒定高温试验应力量值大于+90 ℃、2160 h。能够通过高温+71 ℃、低温?54 ℃无故障环境试验考核的产品具有全世界贮存、运输和使用的潜力。     

Magnetic field measurements of the LHC-IR MQXA magnets at room temperature

KEK has completed 13 of the 18 MQXA quadrupole magnets supplied for the LHC interaction region. The field measurements at room temperature were performed before and after the cold test. The multipole components by the warm measurements showed a good correlation with those by the cold measurements. It is concluded that field quality of the magnets can be evaluated by the warm measurements.     

温、湿、振三综合环境试验技术的应用

主要描述了温度、湿度、振动这3种主要的环境应力单独施加在产品上所引发失效的主要类型并分析了原因，同时还分析了这3种应力综合施加在产品上所产生的失效加速效果，探讨了温、湿、振三综合试验技术在工程试验上，尤其是在产品可靠性试验上的应用。     

Experimental Determination of a More Powerful Burn-In

This paper describes an experiment in which it was determined that burn-in could be made more powerful (i.e., capable of precipitating more failures in a given burn-in period) by reducing the time spent at the high temperature extreme. The number of failures precipitated in burn-in using a cycle consisting of a 2-hour non-operating cold soak and a 2-hour operating heat soak were compared to those precipitated using a 2-hour non-operating cold soak and a 4-hour operating heat soak. The shorter cycles precipitated as many failures as the longer, for an equal number of cycles. The fact that the shorter cycle required two-thirds the chamber time of the longer cycle equates to more cycles, and hence more failures removed, in a given burn-in period.     

室内温度检测与调控系统设计

介绍了以DS18B20基础设计室内温度检测与调控系统的基本过程,该系统以AT89C52单片机为主控器,采用单线多点检测技术,在一条总线上挂接5个DS18B20温度检测点,并循环检测读取各检测点温度数值,可根据实际情况设定阈值,当其中任意3个检测点的温度均超过阈值时,实施超温告警及自动温度调节功能,实验测试结果达到了预期的设计目标。该系统改进了一般温度检测装置单点测试及只测温而不能调节温度的缺陷,可应用于对环境温度要求严格的病房、居室、办公室、小型仓库等场所。     

The experimental study for the solder joint reliability of high I/O FCBGAs with thermal loaded bend test

In this study, the reliability of flip-chip ball-grid array package (FCBGA) is explored by a cyclic four-point bend test executed at different controlled temperature. The test vehicle is put in a heated chamber and the resulting daisy chain resistance and strains variations are monitored to check its failure. The strain gauges are mounted near the component corners to get the strains of the test boards when under bending. A data logger records the daisy chain resistance simultaneously during the test. The component failure is detected with a self-written program by judging when the failure resistance of the daisy chain is larger than 20% of its initial resistance. The test results at various temperatures showed that the component life cycle is reduced with the increase of the temperature during the cyclic bend test when under a fixed maximum deflection setting. If tested at room temperature by varying the maximum deflections, the component life cycle is also reduced with the increase of the maximum deflection in the cyclic bend test. Through the fitted curve of all these test data, it is then possible to get relating equations among the variables of temperature, deflection, and life cycle. An extra test is conducted to verify these deduced equations with an error of only 6% approximately. Furthermore, the optic microscope is utilized to observe the failure mode of the FCBGA component after the test. It is found that all the failures are the delamination at the interface of solder balls and substrate. Also, from the results of tested curves, it can be used to predict the component life cycle at elevated temperatures based on the results tested at room temperature.     

Effects of different test profiles of temperature cycling tests on the reliability of RFID tags

Passive UHF radio-frequency identification (RFID) tags are used for object identification in various environmental conditions, which may affect the reliability of these tags. The effects of different environmental stresses can be studied with accelerated life tests (ALT). Choosing the most suitable test may be challenging: The results are needed as fast as possible, but the failure mechanisms must replicate those occurring in the real operating environment. Here the effects of different temperature cycling profiles were studied by altering temperature ranges, extreme temperatures, soak times to extreme temperatures and transition times between extreme temperatures. Failure times clearly differed between the tests. The test with the fastest transition time and the shortest soak time seemed to have the most acceleration. It was also observed that the different temperature cycling profiles affected the failure mechanisms detected. Cracking of the antenna was observed with lower temperature extremes or shorter soak and transition times. However, with longer soak and transition times, cracks were seen in the RFID interconnections. Both cases led to changes in the impedance matching and consequently to failures. The totally different failure mechanisms clearly demonstrate the importance of carefully determining the test parameters in order to achieve the correct failure mechanism.     

Dislocations in Si generated by fatigue at room temperature

Dislocations in silicon can be generated in many ways, and they often induce a leakage current at the p–n junction and give rise to data retention failures of the semiconductor devices. In this study, it was found that dislocations could be generated in silicon even at room temperature by fatigue. The dislocations generated in a semiconductor device were investigated by transmission electron microscopy. They formed a cluster 3 μm in diameter, which emerged from the interface between the silicon substrate and a tungsten stud. Most of the dislocations were lying on the (1 1 1) planes. It was discovered that cyclic deformation of the device by ultrasonic vibration during the cleaning process generated these dislocations.     

基于CPLD的低功耗爆炸场温度测试系统

为了测量爆炸场等恶劣环境下温度的动态变化,分析炸药或相关弹药的爆炸参数,设计了基于CPLD的低功耗温度存储式测试系统;运用钨铼热电偶温度传感器匹配先进的电源管理模块,并结合动态存储测试技术,能够应用于环境条件比较差的恶劣环境中,在可靠可信、微功耗的基础上能得到较好的实验数据。     

Reduction of test effort. Looking for more acceleration for reliable components for automotive applications

Experience shows that chip package interaction is a dominant cause for failures of electronic components. Optimising the technology by applying the standard temperature cycling test to detect these failures is very time consuming and not any more compatible with today’s development cycles.Early failure indicators (preferable electrically measurable) could be the key element to reduce the test effort and to guarantee the performance in an application.From the package point of view there are three main drivers to be taken into consideration: The temperature, i.e. all degradation processes with an activation energy, temperature swings, which cause thermo-mechanical stress due to different CTE (coefficient of thermal expansion) of the variety of different materials used for the assembly, and temperature gradients, especially when active cycles are applied (switching of the device) can lead to metal reconstruction and plastic deformation, reducing lifetime of the component drastically. Knowledge of the weak areas allows choosing the best test in order to make the addressed failure mode observable in the shortest time.This paper provides a decision basis to speed up technology qualification by using TS (thermal shock) instead of TC (thermal cycling). Results will be shown for different die attach materials.     

Accelerated temperature testing of transistors does not cause excess flicker noise

Electrical noise measurement analysis has been applied in reliability screening of semiconductor devices. Normally it is expected that during accelerated testing reactions increase in composition of device materials causes early failures through the process of defect production. An increase in defects is further expected to result in an increase in the noise of semiconductor devices. Accelerated temperature testing of sample of indegenous NPN transistors was done and noise was measured after certain durations of test time. No appreciable change was observed in the noise level (mainly flicker or 1/noise) even though the devices reached the stage of complete failure. This indicates that defects produced by accelerated temperature testing are not noise generators. X-ray radiography and SEM analysis study has been done for completely failed devices.     

High temperature reliability of electrically conductive adhesive attached temperature sensors on flexible polyimide substrates

The attachment and packaging of temperature sensors may be challenging due to their structure and materials. Sensing requires a structure which is open to the environment and the materials often differ from those used in silicon-based electronics. Thus, traditional attachment techniques and materials such as soldering may be inappropriate. Polymer-based electrically conductive adhesives (ECA) are an alternative. The operating environment of a sensor may, however, be very demanding. Very little research data is available on the use of ECAs in challenging conditions, thus restricting their use in many applications. This study tested the behaviour of temperature sensors attached with ECAs onto flexible polyimide (PI) substrates in thermal storage at 200 °C. More than 1000 h of testing without failures were conducted on the ECA sensor structures. Good high temperature reliability therefore seems to be possible with ECAs. However, the PI substrate was observed to be critical to reliability. An adhesive layer used in the PI substrate reacted at the test temperature and severe oxidation of the copper pads and reaction between the materials consequently destroyed the interconnection and caused failures.     

基于nRF24L01的无线温湿度测试系统

针对传统温湿度测量中的缺点,设计了以低功耗MSP430单片机为控制核心,利用温湿度一体传感器SHT11进行温湿度信号的采集,结合无线传输模块nRF24L01对数据进行无线传输的温湿度测试系统,并在可靠可信、微功耗的基础上能很好地满足实际应用要求。     

Temperature accelerated life test on commercial concentrator III–V triple‐junction solar cells and reliability analysis as a function of the operating temperature

A temperature accelerated life test on commercial concentrator lattice‐matched GaInP/GaInAs/Ge triple‐junction solar cells has been carried out. The acceleration of the aging has been accomplished by subjecting the solar cells at temperatures markedly higher than the nominal working temperature inside a concentrator, and the nominal photo‐current condition (820 X) has been emulated by injecting current in darkness. Three tests at different temperatures have been carried out. The failure distributions across the three test temperatures have been fitted to an Arrhenius–Weibull model. An Arrhenius activation energy of 1.59 eV was determined from the fit. The reliability functions and parameters of these solar cells at two nominal working conditions (80 and 100 °C) have been obtained. In both cases, the instantaneous failure rate function monotonically increases, that is, the failures are of the wear‐out kind. We have also observed that the reliability data are very sensitive to the nominal temperature condition. In fact, at a nominal working condition of 820 X and 80 °C, assuming that the concentration module works 5 h per day, the warranty time obtained for a failure population of 5% has been 113 years. However, for a nominal working condition of 820 X and 100 °C, the warranty time obtained for a failure population of 5% has been 7 years. Therefore, in order to offer a long‐term warranty, the working temperature could be a key factor in the design of the concentration photovoltaic systems. Copyright © 2014 John Wiley & Sons, Ltd.     

Soft-defect detection (SDD) technique for a high-reliability CMOSSRAM

A complete data retention test of a CMOS SRAM array accomplished at room temperature using the soft-defect detection (SDD) technique is reported. The SDD technique uses a connectivity analysis and cell-array current test to detect physical open faults that can cause data retention failures. An extensive circuit analysis was made to establish the operation theory and special circuit design features required for SDD. Complete SDD circuits have been developed and implemented into a 16 K CMOS SRAM module for a 32-b microcontroller. Full operation and effectiveness of the SDD technique were verified from a special experimental 16 K CMOS RAM module with built-in defective cells. the SDD technique can accomplish not only the retention test at room temperature, but also the detection of other defects that were heretofore impractical to detect using the conventional retention test technique of high-temperature bakes and functional tests     

Importance of multi-temp testing in automotive qualification and zero defects program

For automotive qualification of Integrated circuits (ICs), multi-temp testing is required by AEC-Q100. In this paper, we demonstrate the importance and necessity of this multi-temp testing in automotive qualification and zero defects program.During the qualification of one of our new products, we found that all samples could pass electrical testing at room temperature after high temperature operating life test, but a few of them failed at hot temperature. One transistor in the circuit was found to have large leakage current. Only at hot temperature, this leakage current was increased (>50 μA) and the fail was detected during hot electrical testing. Root cause was identified and design error is corrected before the release of the product. No failures are observed anymore.     

Built-in self test of S2I switched current circuits

This article presents a new concept for built-in self test of switched current circuits based on S²I memory cells. From the spectrum of possible transistor defects reported in CMOS processes [1] [2], five different fault-situations were modelled and the ability to detect the various failures was studied. This was accomplished by simulating a simple switched-current integrator in which all the different failures were introduced sequentially in all transistors. The fault coverage was derived and the result shows that a powerful system for detection of transistor faults in an analogue sampled-data system can be readily realised with a minimum of additional overhead circuitry.     

Base profile design for high-performance operation of bipolartransistors at liquid-nitrogen temperature

Measurements of thin epitaxial-base polysilicon-emitter n-p-n transistors with increasing base doping show the effects of bandgap narrowing, mobility changes, and carrier freezeout. At room temperature the collector current at low injection is proportional to the integrated base charge, independent of the impurity distribution. At temperatures below 150 K, however, minority injection is dominated by the peak base doping because of the greater effectiveness of bandgap narrowing. When the peak doping in the base approaches 10¹⁹ cm^-3, the bandgap difference between emitter and base is sufficiently small that the current gain no longer monotonically decreases with lower temperature but instead shows a maximum as low as 180 K. The device design window appears limited at the low-current end by increased base-emitter leakage due to tunneling and by resistance control at the high-current end. Using the measured DC characteristics, circuit delay calculations are made to estimate the performance of an emitter-coupled logic ring oscillator at room and liquid-nitrogen temperatures. It is shown that if the base doping can be raised to 10¹⁹ cm^-3 while keeping the base thickness constant, the minimum delay at liquid-nitrogen temperature can approach the delay of optimized devices at room temperature     

Calibration of resistance type die level temperature sensors usinga single temperature technique

Thermal test chips are widely used to develop electronic packaging thermal solutions and to evaluate electronic package assembly processes. Temperature sensors are an integral component on thermal test chips. Unfortunately, each temperature sensor must be calibrated in order for them to be effective. Each calibration can take up to one hour to complete. In a time when increasing sample sizes and shorter development cycles are taxing current equipment and manpower resources, new calibration techniques must be established to keep development costs down. This paper discusses simplified calibration procedures, which can significantly reduce the time needed for temperature sensor calibration. The simplified calibration procedures utilize single-resistance measurements either at room temperature or at the anticipated test temperature. For four different test chip designs included in the current study, calibration error variations less than ±0.6°C at a ±2σ confidence level are possible. The simplified calibration procedures can be applied to any resistor type temperature sensor that has a linear correlation between its electric resistive properties and temperature     

Charge accumulation of quantum dots at room temperature

The accumulation of charge in InGaAs quantum dots has been measured at room temperature by the photoelectrochemical capacitance-voltage (CV) technique for the first time. A carrier per quantum dot ratio greater than four has been observed. The use of atomic force microscopy and low temperature and room temperature photoluminescence (PL) confirm the existence of quantum dots. Also, a possible excited state is indicated by room temperature PL in a sample with small quantum dots.