Josephson latching driver with a low bit-error rate

A new Josephson latching driver with a current-injection device at an input port has been developed and tested. It has high input sensitivity and a wide bias margin. Under an optimal bias condition, the bit-error rate (BER) of this driver is below 10/sup -12/ at data rates of 5 and 10 Gb/s. The driver can be switched by superconducting single-flux quantum (SFQ) pulse input and can be used as an amplifier to test the BER of SFQ circuits. In such a test, the BER of an SFQ converter operating at 5 Gb/s was less than 10/sup -12/ with bias margin of /spl plusmn/20%.     

Logic operation at 5 Gb/s of an output interface for single-flux-quantum systems

High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NEC's 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.     

Output interface with latching driver for LTS-SFQ circuits

We propose an output interface with a latching driver for single-flux-quantum (SFQ) circuits operating at 4.2 K. An optimum critical current density J/sub c/ of the latching driver was discussed, and a multichip module (MCM) structure with SFQ circuits and latching drivers was proposed for 40-Gb/s operation. To optimize J/sub c/ of the latching driver, we calculated the punchthrough probability of Nb-Al-AlO/sub x/-Nb junctions and high-temperature superconductor (HTS) junctions. The Nb junction with a J/sub c/ of 45 kA/cm/sup 2/, which has a hysteresis of 44% for the latching operation, leads to a punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz. On the other hand, ramp-edge-type interface-modified junctions based on YBa/sub 2/Cu/sub 3/O/sub 7-x/ have an optimum J/sub c/ of 60 kA/cm/sup 2/ that gives the smallest punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz without any shunt capacitance. Because the optimum J/sub c/ of 45 kA/cm/sup 2/ for the latching driver is too large to fabricate large-scale integrated SFQ circuits with the Nb junction, the MCM structure consisting of SFQ circuits and latching drivers with the optimum J/sub c/ is important to prepare 40-Gb/s SFQ systems. The J/sub c/ of 60 kA/cm/sup 2/ is a practical value for the HTS junctions, and use of the low-temperature superconductor (LTS)-HTS MCM structure is also one way to realize the high-speed SFQ systems.     

10 K NbN ADC for IR sensor applications

The authors report the design, fabrication and test results of a 12-bit NbN SFQ counting A/D converter operating at 9 to 10 K and its insertion into a test IR focal plane array sensor system. The NbN IC is based on a linearized SQUID front-end which generates SFQ pulses at a frequency proportional to the signal. A gated SFQ counter integrates the signal over the sample time and the data is driven off chip through a serializing latching voltage state logic (MVTL) output shift register. The TRW A/D converter chip has been packaged and inserted into an IR focal plane array sensor test facility, or test bed, at the NASA Jet Propulsion Laboratory. The entire system has been successfully demonstrated producing IR images at 100 frames/s with the NbN A/D converter operating at 9 K, dissipating 0.3 mW. Performance of the A/D converter chip, the package including magnetic shielding and medium/high speed signal I/O, and the integrated test bed system are discussed.     

Pulse amplitude-modulated time-based interface for off-chip interconnect

An increased number of bits pulse amplitude-modulated differential-time signalling interface for off-chip interconnect is introduced in this article by combining the differential time signalling (DTS) technique with the pulse amplitude-modulation (PAM) approach. Applying the PAM to the DTS-transmitted signal increases the total number of the transmitted bits per symbol while maintaining the transmitted signal bandwidth. 4-bit 6 Gb/s DTS serial link has been designed and simulated using 65 nm CMOS mixed signal technology. 5-bit 7.5 Gb/s and 6-bit 9 Gb/s amplitude-modulated DTS serial links have been designed, simulated and compared to the 6 Gb/s DTS serial link. The three serial links use 1.5 Gb/s as input clock signal. In the amplitude-modulated DTS-transmitted signal, the rising and falling edges of the input clock signal are modulated in time as well as the transmitted signal amplitude is modulated. A reference clock pulse is generated from the input clock signal and embedded on the transmitted signal to be used as reference timing at the receiver circuit. The design details of the designed links are presented in the article. The 9 Gb/s link uses a 60 cm 4003C Rogers substrate as a transmission channel. The transmitted signal spectrum is presented and compared for the three designed links. The total power consumption of the 9 Gb/s amplitude-modulated DTS interface is less than 25 mW.     

A CMOS 10-gb/s power-efficient 4-PAM transmitter

A novel power-efficient architecture for a multilevel pulse amplitude modulation (PAM) transmitter is proposed. A data-look-ahead technique is used to pre-switch the current sources so that drive current is reduced when transmitting small voltage levels. This technique also eliminates the need for a pre-driver block, which also saves transmitter power. Based on this architecture, a 4-PAM transmitter is designed in 0.18-/spl mu/m standard digital CMOS technology. The transmitter achieves 3.5 GS/s (7 Gb/s) with a 1.7-V supply and 5 GS/s (10 Gb/s) with a 2-V supply and it occupies an area of 0.16 mm/sup 2/. The output driver and the entire transmitter consume only 11.25 and 66 mW at 7 Gb/s (20 and 121 mW at 10 Gb/s), respectively, which are the lowest reported powers at this speed.     

Pseudomorphic 2DEG FET IC's for 10 Gb/s optical communicationsystems with external optical modulation

An optical modulator driver IC and a preamplifier IC for 10 Gb/s optical communication systems are developed using AlGaAs/InGaAs/GaAs pseudomorphic two-dimensional electron gas (2DEG) FETs with a gate length of 0.35 μm. The optical modulator driver IC operates at a data rate up to 10 Gb/s with an output voltage swing of more than 4 V_p-p . The bandwidth for the amplifier IC is 13.0 GHZ with ab 47 dB-Ω transimpedance gain. In addition, optical transmission experiments with external optical modulation using these ICs have successfully been carried out at 10 Gb/s     

SiGe driver circuit with high output amplitude operating up to 23Gb/s

A high-speed driver circuit is presented with special regard to layout aspects. The IC, which was fabricated in an advanced SiGe bipolar technology, was developed for driving external modulators in a 20 Gb/s fiber-optic time division multiplex transmission system but can also be used as an output stage of multipurpose pulse generators. Measurements on mounted chips show clear eye diagrams up to 23 Gb/s data rate and high single-ended and differential output swings of 3.5 and 7 V_p-p , respectively, at 50 Ω external load. To the best of the authors' knowledge, this is the highest voltage swing reported so far for a silicon-based driver circuit at comparable operating speed     

一个低功耗高摆幅电压模式发送端

本文设计完成了一个28纳米工艺下的低功耗电压模式发送端. 相比于电流模式发送端。电压模式发送端输出更大摆幅的信号的同时功耗更低。发送端通过电压转换器被分为两个电压域用于减小功耗。另外,本文提出的电压结构能够实现相互独立的阻抗匹配和均衡控制。 芯片实测发送端可输出差分摆幅880毫伏的信号,并且每个通道的功耗仅为23毫瓦。     

一种低功耗高精确度SERDES发送机

介绍了一款高速串行接口发送机芯片。均衡器采用多抽头前馈均衡结构,且各阶均衡系数均可调,增大了均衡调谐范围,提高了均衡精确度;驱动器采用H树型电流模结构,提高了电流利用率,降低了功耗。设计采用TSMC 55 nm CMOS工艺,电源电压为1 V,输出数据率范围为550 Mb/s~6.25 Gb/s。在最高工作速率6.25 Gb/s下,发送机整体功耗约20 mW,结果表明发送机均衡精确度较高,功耗较低。     

New hybrid integrated laser diode-drivers using microsolder bumpbonding: SPICE simulation of high-speed modulation characteristics

This paper proposes two types of new hybrid integrated laser diode (LD)-drivers that use microsolder bump bonding instead of conventional wire bonding. In one, an LD and a driver are flip-chip bonded to each other; in the other, an LD and a driver are flip-chip bonded onto a substrate. Their performances are compared to those of a monolithic LD-driver and a conventional hybrid one using wire bonding by a simulation program with integrated circuit emphasis (SPICE) with particular emphasis on high-speed LD modulation. The nonreturn-to-zero (NRZ) eye patterns modulated at signal speeds up to 30 Gb/s by the new hybrid integrated LD-drivers were hardly inferior to those by the monolithic LD-driver, whereas those by conventional hybrid ones were greatly degraded over 10 Gb/s. The new hybrid integrated LD-drivers are a feasible alternative to monolithic ones for high-speed optical transmitters     

High-Speed TDM–WDM Techniques for Long-Haul Submarine Optical Amplifier Systems

Optical amplifier techniques have led to the installation of large-capacity submarine systems and further capacity increases seem likely. This paper reviews the FSA submarine system, which flexibly operates at both 2.5 and 10 Gb/s and offers maximum transmission capacity of 60 Gb/s for commercial use. The system configuration as well as its characteristics and upgradability will be introduced, including measurement results on time-division-multiplexing/wavelength-division-multiplexing (TDM–WDM) transmission at bit rates of 10 and 20 Gb/s using non-return-to-zero or soliton pulses. To further increase transmission capacity, TDM–WDM techniques that permit more than 10 Gb/s signal transmission in each data channel should be developed. Thus, pulse formats, which include non-return-to-zero, return-to-zero, or soliton pulses, and dispersion allocation in transmission fibers are significant issues. We introduce and discuss our recent results from high-speed (10 to 40 Gb/s) TDM–WDM signal transmission experiments with regard to the above aspects.     

Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses

This paper demonstrates that driver preemphasis technique can be used for on-chip global buses to increase signal channel bandwidth. Compared to conventional repeater insertion techniques, driver preemphasis saves repeater layout complexity and reduces power consumption by 12%-39% for data activity factors above 0.1. A driver circuit architecture using voltage-mode preemphasis technique was tested in 0.18-mum CMOS technology for 10-mm long interconnects at 2 Gb/s     

Real-time measurements on a four stage RSFQ-counter with Nb–Al2O3–Nb Josephson junctions

RSFQ-toggle-flipflops with a SFQ-trigger circuit a Josephson transmission line at the input and a SFQ/dc-circuit at the output of each stage are implemented in the Nb–Al₂O₃–Nb Josephson junction technology on a single chip having coplanar wave guides at input and output. The counter is tested successfully at 4.2 K via coplanar/coaxial transitions using a bit pattern generator and a digital oscilloscope at room temperature up to f_I≈2 GHz pulse repetition frequency at the input. The highest test frequency f_I is limited by the available pattern generator.     

Multisim在超导器件研究中的应用

 为了对约瑟夫森结及其相关电路进行仿真研究,首次在Multisim中建立了约瑟夫森结的模型.利用Multisim对直流约瑟夫森效应,交流约瑟夫森效应进行了仿真验证.随后利用在Multisim中建立的模型对电阻电容电感并联约瑟夫森结(Resistively-Capacitively-Inductively Shunted Junction,RCLSJ)模型中的混沌行为,微波感应台阶,热噪声对台阶的影响以及RSFQ (Rapid Single Flux Quantum)电路进行了仿真研究.仿真结果证明了在Multisim中建立的模型对超导器件进行仿真研究是合理可行的,这对超导器件的分析和设计具有重要意义.     

10Gb/s光调制器InGaP/GaAs HBT驱动电路的研制

采用自行研发的4英寸InGaP/GaAs HBT技术,设计和制造了10Gb/s光调制器驱动电路.该驱动电路的输出电压摆幅达到3V_pp,上升时间为34.2ps(20~80%),下降时间为37.8ps(20~80%),输入端的阻抗匹配良好(S11=-12.3dB@10GHz),达到10Gb/s光通信系统(SONET OC-192,SDH STM-64)的要求.整个驱动电路采用-5.2V的单电源供电,总功耗为1.3W,芯片面积为2.01×1.38mm².     

Single-chip 4×500-MBd CMOS transceiver

A CMOS chip containing four 500-MBd serializer/deserializer pairs has been designed to relieve interconnect congestion in an ATM switch system. The 9.7×9.7 mm² chip fabricated in a 0.8-μm technology is packaged on a ceramic ball grid array and dissipates 3.5 W. It replaces a 72-wire parallel interface with an eight-line serial interface transparent to the user and supports transmission at 1.6 Gb/s per direction in full-duplex mode. Virtually error-free operation in a system environment over electrical serial links having up to 9 dB loss at 500 MHz has been realized using signal predistortion for the serial bit stream and PLL clock recovery for each of the four receivers. Interface timing and serial-link driver strength are programmable     

A versatile Si-bipolar driver circuit with high output voltageswing for external and direct laser modulation in 10 Gb/s optical-fiberlinks

A monolithic integrated driver circuit developed for laser modulation in a 10 Gb/s optical-fiber link is presented. The IC was fabricated in a self-aligned double-polysilicon Si-bipolar production technology with f_T≈25 GHz. The circuit can be operated up to 14 Gb/s with a maximum output voltage swing as high as 3.6 V at 50 Ω load (corresponding to an internal current swing of 108 mA), which allows the circuit to drive external modulators. In addition, the circuit can be used for direct laser modulation at 10 Gb/s, since the output current swing can easily be controlled over a wide range (e.g., from 15 mA to 60 mA). Problems in the design of such driver circuits as well as their solutions are discussed in detail     

A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11- μm CMOS

This paper presents a 20-Gb/s simultaneous bidirectional transceiver using a resistor-transconductor (R-gm) hybrid in standard 0.11-mum CMOS. The R-gm hybrid separates the inbound signal from the signal line voltage and current without using a replica driver. It eliminates the need for precise matching between the replica- and main-driver characteristics, enabling a data rate of 20 Gb/s per differential pair, which is the highest reported for bidirectional signaling. The transceiver occupies 1.0² mm and consumes 260 mW at 20 Gb/s with a bit error rate of less than 10^-12. The area and power overhead due to the hybrid are 0.002 mm² and 7 mW, and correspond to 0.2% and 3% of the total transceiver area and power consumption     

High-temperature operation of oxide SFQ-circuit-elements

Single flux quantum (SFQ) circuit components such as an SFQ-dc converter and a confluence buffer have been fabricated by using an YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// ramp-edge junction technology and their logic operations at temperatures up to near 60 K were investigated. The SFQ-dc converter was correctly operated in a wide temperature range from 4.2 K to 56 K and found to be useful for detecting output signals from other SFQ circuit components at any operating temperatures. The basic function that a signal from either of two input Josephson transmission lines (JTLs) was transmitted to an output JTL was confirmed for the confluence buffer and finite operating margins were obtained at temperatures from 42 K to 61 K. The narrowest margin of dc supply current obtained at temperatures from 55 K to 60 K was /spl plusmn/20% and was consistent with the simulation. Margin reduction due to thermal noise was also evaluated. According to the analytical calculation, the operating margin to keep the bit-error rate less than 10/sup -5/ was as large as /spl plusmn/20% even at 50 K when the value of junction critical-current I/sub c/ was kept near 0.4 mA.