Temperature-dependent dynamic triggering characteristics of SCR-type ESD protection circuits

Experimental analysis of the dynamic characteristics of various silicon-controlled rectifier (SCR)-type ESD protection circuits at various temperatures has been carried out. These circuits include MOSFET-trigger SCR (MTSCR), diode-chain-trigger SCR (DCTSCR), low-voltage zener diode trigger SCR (ZDSCR), low-voltage trigger SCR (LVTSCR) and gate-coupled low-voltage trigger SCR (GCSCR) circuits. The static trigger voltage increases with temperature if the SCR uses the breakdown trigger mechanism, otherwise it decreases with temperature. The peak pad voltages for the MTSCR and DCTSCR subjected to a pulse-like ESD stress decrease with increasing temperature, while those of GCSCR and LVTSCR are relatively insensitive to temperature.     

The novel SCR-based ESD protection with low triggering and high holding voltages

This paper introduces a novel silicon controlled rectifier (SCR)-based circuit. The proposed device using 70 nm DRAM process obtained the high holding and low triggering voltages by using variable IR drop. These characteristics enable to discharge electrostatic discharge (ESD) current and ensure latch-up immunity for normal operations. Also, the proposed scheme is easily implemented through the modification of the metal connection compare to the conventional SCR-based device. We investigated electrical characteristics by both measurements and TCAD simulations. Measurement results showed the proposed SCR had triggering voltage of 6.2 V, holding voltage of 3.3 V, and the second breakdown current of 58 mA/μm.     

基于SCR的ESD器件低触发电压设计

设计和验证了三种低电压触发的SCR结构ESD保护电路,采用上华0.5μmCMOS工艺流片,测试表明,所有的器件都具有低电压触发特性,在器件宽度只有50μm的条件下,能达到400V正向机器模式的ESD性能。实验中发现了意外失效情况,文章给出了分析。     

Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology

The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip electro-static-discharge (ESD) protection. The device has a small area in requirement robustness in comparison to gate-grounded NMOS (ggNMOS). The proposed ESD protection device is designed in 0.25 μm CMOS technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 3.8 V and a high trigger current of greater than 120 mA. The robustness has measured to HBM 8 kV (HBM: human body model) and MM 400 V (MM: machine model). The proposed device has a high-level It2 of 52 mA/μm approximately.     

Design of fabrication of ESD protection circuit with high holding voltage for power IC

In this paper, A newly Silicon Controlled Rectifier (SCR)-based Electric Static Discharge (ESD) protection circuit is proposed. The proposed circuit has the latch-up immunity in normal operating conditions with the high holding voltage by inserting the floating regions. To verify the electrical characteristics, a Technology Computer Aided Design (TCAD) simulation is performed by setting each of variables: D1, D2, D3, and D4. The results of the simulation show that the proposed protection circuit has the holding voltage 5 V higher than the conventional circuits and has the same level of robustness properties as the existing SCR. In addition, the proposed circuit is fabricated through a 0.18 μm Bipolar-CMOS-DMOS process. The electrical characteristics are confirmed by measuring Transmission Line Pulse, and the robustness properties are measured through Human Body Model (HBM) and Machine Model (MM). The holding voltage is about 20 V, which has the increases above 18 V or more compared to the conventional SCR. Therefore, the proposed circuit is proved to have the better ESD protection performance than HBM 8 kV and MM 800 V higher than HBM 2 kV and MM 200 V, the commercial standard.     

一种用于混合电压芯片的新型ESD防护触发电路

为了降低芯片成本,通过使用低压器件串联的方式构造静电防护触发电路,使芯片在没有使用高压I/O器件的情况下实现了高压电源域的ESD防护。由于该触发电路未使用电容器件,因此有效地降低了ESD触发电路所占用的芯片面积,并且该电路为静态电压触发,其开启时间可远长于一般电容电阻耦合的触发电路。通过在HSPICE中使用类ESD(ESD-like)的方波脉冲,可以看出该电路在发生ESD时能有效地触发ESD器件,而在芯片正常工作时不易因外界干扰而产生误触发。     

一种用于ESD保护的双向SCR特性研究

基于0.35 μm CMOS混合信号工艺,实现了一种用于ESD保护的MDDSCR器件。通过堆叠MDDSCR单元来调整维持电压,结合TLP测试结果,说明了关键尺寸和不同的衬底连接方式对器件特性的影响。堆叠DDSCR正向触发电压(Vt1)和维持电压(VH)随着堆叠器件数量的增加而线性增加,但因为存在额外寄生通路,负向Vt1和VH分别维持在20 V和6 V左右。该器件可实现6 kV以上HBM ESD保护能力,广泛应用于汽车电子、无线基站、工业控制等电源或者信号端的双向ESD保护。     

基于SCR的ESD保护电路防闩锁设计

SCR器件作为目前单位面积效率最高的ESD保护器件,被广泛研究并应用到实际电路中.SCR所具有的低保持电压特性可以带来很高的ESD性能,但同时也会导致闩锁.文章从提高保持电压和触发电流这两方面入手,研究在实际电路应用中如何防止ESD保护电路发生闩锁.     

Analysis of a Parasitic‐Diode‐Triggered Electrostatic Discharge Protection Circuit for 12 V Applications

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic‐diode‐triggered silicon controlled rectifier. The breakdown voltage and trigger voltage (V_t) of the proposed ESD protection circuit are improved by varying the length between the n‐well and the p‐well, and by adding n+/p+ floating regions. Moreover, the holding voltage (V_h) is improved by using segmented technology. The proposed circuit was fabricated using a 0.18‐μm bipolar‐CMOS‐DMOS process with a width of 100 μm. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the V_t of the proposed circuit increased from 14 V to 27.8 V, and V_h increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human‐body‐model surges at 7.4 kV and machine‐model surges at 450 V.     

Highly Robust AHHVSCR‐Based ESD Protection Circuit

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR‐based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch‐up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit — (i) an AHHVSCR‐based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR‐based ESD protection circuit, and (iii) a standard HHVSCR‐based ESD protection circuit. A circuit having the proposed new structure is fabricated using 0.18 μm Bipolar‐CMOS–DMOS technology. The fabricated circuit is also evaluated using Transmission‐Line Pulse measurements to confirm its electrical characteristics, and human‐body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.     

TFT_LCD驱动芯片GATE／SOURCE静电保护电路设计与实现

文章描述了TFT_LCD驱动芯片防静电（ESD）保护电路的布局,重点分析和设计了TFT_LCD驱动芯片GATE和SOURCE引脚的ESD保护电路。ESD保护电路布局上,采用髓排ESD电路错开呈”品字形“排列,使ESD电流均匀流通。在GATE保护电路中,采用二极管接法代替通用PMOS,防止电路产生Latch-up效应。SOURCE的保护电路中．NMOS的Drain设计了RPO（Resisl Protection Oxide）,使流经Drain的电流均匀分散,使二次击穿电压升高。     

Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology

To provide area-efficient output ESD protection for the scaled-down CMOS VLSI, a new output ESD protection is proposed. In the new output ESD protection circuit, there are two novel devices, the PTLSCR (PMOS-trigger lateral SCR) and the NTLSCR (NMOS-trigger lateral SCR). The PTLSCR is in parallel and merged with the output PMOS, and the NTLSCR is in parallel and merged with the output NMOS, to provide area-efficient ESD protection for CMOS output buffers. The trigger voltages of PTLSCR and NTLSCR are lowered below the breakdown voltages of the output PMOS and NMOS in the CMOS output buffer. The PTLSCR and NTLSCR are guaranteed to be turned on first before the output PMOS or NMOS are broken down by the ESD voltage. Experimental results have shown that the PTLSCR and NTLSCR can sustain over 4000 V (700 V) of the human-body-model (machine-model) ESD stresses within a very small layout area in a 0.6 μm CMOS technology with LDD and polycide processes. The noise margin of the proposed output ESD protection design is greater than 8 V (lower than −3.3 V) to avoid the undesired triggering on the NTLSCR (PTLSCR) due to the overshooting (undershooting) voltage pulse on the output pad when the IC is under normal operating conditions with 5 V VDD and 0 V VSS power supplies.     

亚微米CMOS集成电路的ESD保护新结构

本文主要介绍几种新型的ESD保护结构,包括互补SCR结构,双寄生SCR结构,低触发电压,高触发电流的横向SCR结构等,利用这些结构可以对CMOS集电路的输入／输出进行有效地ESD保护。     

LVTSCR structures for latch-up free ESD protection of BiCMOS RF circuits

The results of a numerical and experimental study aimed at increasing the holding on-state voltage of a low-voltage triggered silicon controlled rectifier are presented. Using TCAD numerical simulations two solutions are presented that are based on emitter injection control by the modification of the emitter–drain area ratio and by the addition of internal diodes in the emitter line. Experimental data generated in a 0.18 μm CMOS technology demonstrate the effectiveness of the new low-voltage triggered silicon controlled rectifier (LVTSCR) structures and validates the simulation results. It has been demonstrated that for the LVTSCR structures with high holding voltage the electrostatic discharge efficiency is 3–5 times higher than that of a conventional grounded gate snapback NMOS and simultaneously has 50% lower RF load capacitance.     

ESD issues in compound semiconductor high-frequency devices and circuits

The need of ESD protection for high frequency devices and circuits is underlined by reviewing the compound semiconductor material properties with emphasis on ESD stress and by collecting their ESD failure thresholds. Basic requirements for possible ESD protection structures in the microwave frequency regime are discussed and possible ESD protection devices and circuit concepts are proposed.     

GaAs MMIC抗静电能力研究

用人体静电放电模拟器对以ＧａＡｓ ＭＥＳＦＥＴ为主要有源器件的ＭＭＩＣ的静电敏感度进行研究,叙述了在ＭＭＩＣ设计、工艺制作等环节防静电和提高ＭＭＩＣ抗静电能力的措施,采用这些措施后,低噪声ＭＭＩＣ静电损伤阈值达到５００～８００ Ｖ。     

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices

As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The simulation results show that the using these techniques reduces the ESD triggering voltage by 63 and 44% for MOSFET-based and LVTSCR-based ESD structures, respectively, under 2 kV HBM ESD stress. The effectiveness of proposed gate and substrate triggering techniques is also confirmed by the HBM and TLP measurements.     

Design of novel DDSCR with embedded PNP structure for ESD protection* Xiuwen Bi (毕秀文), Hailian Liang (梁海莲), Xiaofeng Gu (顾晓峰)?, Long Huang (黄龙)

通过在常规双向可控硅器件(DDSCR)内部嵌入一个PNP结构,提出了一种新型的静电防护(ESD)器件DDSCR-PNP,以提高器件的维持电压(Vh),降低闩锁风险。首先,分析了DDSCR-PNP器件的工作机理,理论分析表明,内嵌PNP结构(PNP_2)使器件具有很好的电压箝位能力。然后,基于0.35 μm Bipolar-CMOS-DMOS工艺制造了实验器件,并利用Barth 4002传输线脉冲测试系统进行了分析。测试结果证明了DDSCR-PNP的Vh比传统DDSCR高得多,而且通过调节P阱宽度可进一步增加Vh。然而,当P阱宽度超过12 μm时,DDSCR-PNP的漏电流(IL)出现明显波动。最后,利用Sentaurus仿真分析了影响Vh和IL的原因。结果表明,横向PNP_2有助于提高Vh并降低IL,但其作用随着P阱宽度的增大而减弱,导致IL随之增大。这种新型的DDSCR-PNP器件为高压集成电路的ESD防护提供了一种有效的解决方案。     

Design of SCR‐Based ESD Protection Circuit for 3.3 V I/O and 20 V Power Clamp

In this paper, MOS‐triggered silicon‐controlled rectifier (SCR)–based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR‐based ESD protection circuits with floating diffusion regions for inverter and light‐emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded‐gate NMOS (ggNMOS) in the MOS‐triggered SCR‐based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P‐well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the floating diffusion region. The trigger voltage was improved by the partial insertion of a P‐body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low‐ and high‐voltage applications were designed using 0.18 µm Bipolar‐CMOS‐DMOS technology, with 100 µm width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS‐6008).     

应用于ESD防护电路的抗噪声LVTSCR组件研究

应用于ESD防护的低压触发SCR组件,当受到电路噪声干扰时,极易造成SCR组件的误导通,进而影响到电路的正常功能,严重时可以产生持续的闩锁效应,造成SCR组件烧毁。通过改进SCR的结构,提高该SCR组件的触发电流,或者提高该SCR组件的保持电压,使其抗噪声干扰能力大大增强。另外,文中对触发电流与温度的关系、保持电压与N+区宽度的关系也做了分析。