A low-power CMOS time-to-digital converter

A time-to-digital converter, TDC, with 780 ps lsb and 10-μs input range has been integrated in a 1.2-μm CMOS technology. The circuit is based on the interpolation time interval measurement principle and contains an amplitude regulated crystal oscillator, a counter, two pulse-shrinking delay lines, and a delay-locked loop for stabilization of the delay. The TDC is designed for a portable, low-power laser range-finding device. The supply voltage is 5±0.5 V, and the operating temperature range is -40 to +60°C. Single-shot accuracy is 3 ns and accuracy after averaging is ±120 ps with input time intervals 5-500 ns. In the total input range of 10 μs, the final accuracy after averaging is ±200 ps. Current consumption is 3 mA, and the chip size is 2.9 mm×2.5 mm     

An integrated time-to-digital converter with 30-ps single-shotprecision

A time-to-digital converter (TDC) with 32-ps resolution and 2.5-μs measurement range has been integrated in a 0.8-μm BiCMOS process. The TDC is based on a counter with a 100-MHz clock. Two separate time digitizers improve the time resolution by interpolating within the clock period. These interpolators are based on analog dual-slope conversion. According to test results, the single-shot precision of the TDC is better than 30 ps (σ-value) and the nonlinearity is less than ±5 ps when input time intervals range from 10 ns to 2.5 μs. The conversion time is ⩽6.3 μs. Temperature drift, excluding the temperature dependence of the oscillator, is below ±40 ps in the temperature range of -40 to 60°C. The size of this chip, including pads, is 3.5×3.4 mm² and its power consumption is 350 mW     

A high-resolution CMOS time-to-digital converter utilizing aVernier delay line

This paper describes a CMOS time-to-digital converter (TDC) integrated circuit utilizing tapped delay lines. A technique that allows the achievement of high resolution with low dead-time is presented, The technique is based on a Vernier delay line (VDL) used in conjunction with an asynchronous read-out circuitry. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. A test circuit fabricated in a standard 0.7-μm digital CMOS process is presented. The TDC contains 128 delay stages and achieves 30-ps resolution, stabilized by the DLL, with the accuracy exceeding ±1 LSB. Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable     

A CMOS time-to-digital converter with better than 10 ps single-shot precision

A high-precision CMOS time-to-digital converter IC has been designed. Time interval measurement is based on a counter and two-level interpolation realized with stabilized delay lines. Reference recycling in the delay line improves the integral nonlinearity of the interpolator and enables the use of a low frequency reference clock. Multi-level interpolation reduces the number of delay elements and registers and lowers the power consumption. The load capacitor scaled parallel structure in the delay line permits very high resolution. An INL look-up table reduces the effect of the remaining nonlinearity. The digitizer measures time intervals from 0 to 204 /spl mu/s with 8.1 ps rms single-shot precision. The resolution of 12.2 ps from a 5-MHz external reference clock is divided by means of only 20 delay elements.     

Temperature compensated and gated CMOS ring oscillator for time-to-digital converter application

This paper presents a CMOS voltage controlled ring oscillator with temperature compensation for low power time-to-digital converters (TDCs). In order to maintain the oscillation frequency stable, a novel compensation circuit is proposed through adaptively sensing temperature variations. This design has been implemented in TSMC 0.35 μm CMOS standard process with an active area of under 0.039 mm². Experimental results show that the clock frequency is around 159.0 MHz only with a power consumption of 550 μA. As respective to the room temperature the maximum frequency variation is between ?3.46 and +3.08 % under temperature range of ?40 to 85 °C. The bit error time induced by clock jitter is limited within 4.8 % in the whole clock period, and the differential nonlinearity of the TDC is less than 0.408 LSB.     

Three-gamma annihilation imaging in positron emission tomography

It is argued that positron annihilation into three photons, although quite rare, could still be used as a new imaging modality of positron emission tomography. The information gained when the three decay photons are detected is significantly higher than in the case of 511 keV two-gamma annihilation. The performance of three-gamma imaging in terms of the required detector properties, spatial resolution and counting rates is discussed. A simple proof-of-principle experiment confirms the feasibility of the new imaging method.     

Highly accurate cyclic CMOS time-to-digital converter withextremely low power consumption

The authors propose a new cyclic structure for a CMOS time-to-digital converter (TDC). The measured single-shot resolution is 286 ps, and the measured single-shot accuracy is <143 ps. The new circuit can be shut down between measurements which makes the circuit suitable for portable applications     

基于门控多路环形振荡器的时间数据转换器

A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm~2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.     

An 11-bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments

An 11-bit time-to-digital converter (TDC) with high time resolution implemented in CMOS VLSI is presented. The TDC operates with a wide and clock-adjustable resolution of LSB = 50 ps to 1 ns, and with good power supply, temperature, and environmental effects compensation. The dead time of the measurement is as low as 0.5 /spl mu/s and the event rate can be as high as 1 MEvents/s. The power dissipation is a function of event rate and clock frequency; the TDC dissipates <10 mW at an event rate of 100 kEvents/s and LSB=100 ps. The TDC was incorporated in a complete time-of-flight (TOF) system on a chip that in addition included front-end analog signal processing. The TOF chip is already flying onboard the HENA (High Energy Neutral Atoms) instrument of the IMAGE NASA mission, launched in 2000, and is part of many other instruments such as particles, X-ray, and the laser altimeter of the Messenger spacecraft.     

1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. It additionally serves as a CMOS process strength estimator for analog circuits in this large system-on-chip. Measured integral nonlinearity is 0.7 least significant bits. The TDC consumes 5.3 mA raw and 1.3 mA with power management from a 1.3-V supply.     

A low power time-to-digital converter for all-digital phase-locked loop

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL’s total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.     

A time-to-digital converter based AFC for wideband frequency synthesizer

The automatic frequency calibration (AFC) technique is routinely used in wideband frequency synthesizers that contain multiple voltage-controlled oscillator (VCO) tuning curves. In this paper, a counter-based AFC that uses a time-to-digital converter (TDC) in the counting process is developed. The TDC is able to capture the fractional VCO cycle information within the counting window. This significantly improves the frequency detection accuracy over the existing counter-based AFC techniques. In addition, a quantitative model is developed to determine the minimally required error-free AFC calibration time for a given VCO tuning curve characteristic. An AFC circuit using the proposed TDC-based counter is designed in a 0.13-μm CMOS technology. Simulation results show that the proposed AFC significantly improves the frequency detection accuracy and consequently for a given frequency detection resolution reduces the AFC calibration time. The simulated error-free AFC time is <2.5 μs with a frequency resolution of 0.04 %.     

CMOS imaging for automotive applications

This contribution is devoted to CMOS imaging for automotive applications. It is shown that unlike CCD-based imaging, imaging based on CMOS-sensing meets adequately requirements posed by automotive vision applications. In addition, besides classical vision, CMOS imaging enables new applications like, e.g., occupancy sensing, rangefinding, and 3-D vision.     

A multigrid expectation maximization reconstruction algorithm for positron emission tomography

The problem of reconstruction in positron emission tomography (PET) is basically estimating the number of photon pairs emitted from the source. Using the concept of the maximum-likelihood (ML) algorithm, the problem of reconstruction is reduced to determining an estimate of the emitter density that maximizes the probability of observing the actual detector count data over all possible emitter density distributions. A solution using this type of expectation maximization (EM) algorithm with a fixed grid size is severely handicapped by the slow convergence rate, the large computation time, and the nonuniform correction efficiency of each iteration, which makes the algorithm very sensitive to the image pattern. An efficient knowledge-based multigrid reconstruction algorithm based on the ML approach is presented to overcome these problems.     

Pulse shrinking time-to-digital converter for UWB application

A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device. The pulse shrinking is realized in a loop containing two Programmable Delay Lines(PDLs) or a two-channel PDL. One line(channel) delays the rising edge and the other line(channel) delays the falling edge of a circulating pulse. Delay resolution of PDL is converted into a digital output code under known conditions of pulse width. This delay resolution measurement mechanism is different from the conventional time interval measurement mechanism based on pulse shrinking of conversion of unknown pulse width into a digital output code. This mechanism automatically avoids the influence of unwanted pulse shrinking by any circuit element apart from the lines. The achieved relative errors for four PDLs are within 0.80%–1.60%.     

A high-resolution time-to-digital converter using a three-level resolution

In this article, a three-level resolution Vernier delay line time-to-digital converter (TDC) was proposed. The proposed TDC core was based on the pseudo-differential digital architecture that made it insensitive to nMOS and pMOS transistor mismatches. It also employed a Vernier delay line (VDL) in conjunction with an asynchronous read-out circuitry. The time interval resolution was equal to the difference of delay between buffers of upper and lower chains. Then, via the extra chain included in the lower delay line, resolution was controlled and power consumption was reduced. This method led to high resolution and low power consumption. The measurement results of TDC showed a resolution of 4.5 ps, 12-bit output dynamic range, and integral nonlinearity of 1.5 least significant bits. This TDC achieved the consumption of 68.43 µW from 1.1-V supply.     

Regularized image reconstruction algorithms for positron emission tomography

We develop algorithms for obtaining regularized estimates of emission means in positron emission tomography. The first algorithm iteratively minimizes a penalized maximum-likelihood (PML) objective function. It is based on standard de-coupled surrogate functions for the ML objective function and de-coupled surrogate functions for a certain class of penalty functions. As desired, the PML algorithm guarantees nonnegative estimates and monotonically decreases the PML objective function with increasing iterations. The second algorithm is based on an iteration dependent, de-coupled penalty function that introduces smoothing while preserving edges. For the purpose of making comparisons, the MLEM algorithm and a penalized weighted least-squares algorithm were implemented. In experiments using synthetic data and real phantom data, it was found that, for a fixed level of background noise, the contrast in the images produced by the proposed algorithms was the most accurate.     

Penalized weighted least-squares image reconstruction for positron emission tomography

Presents an image reconstruction method for positron-emission tomography (PET) based on a penalized, weighted least-squares (PWLS) objective. For PET measurements that are precorrected for accidental coincidences, the author argues statistically that a least-squares objective function is as appropriate, if not more so, than the popular Poisson likelihood objective. The author proposes a simple data-based method for determining the weights that accounts for attenuation and detector efficiency. A nonnegative successive over-relaxation (+SOR) algorithm converges rapidly to the global minimum of the PWLS objective. Quantitative simulation results demonstrate that the bias/variance tradeoff of the PWLS+SOR method is comparable to the maximum-likelihood expectation-maximization (ML-EM) method (but with fewer iterations), and is improved relative to the conventional filtered backprojection (FBP) method. Qualitative results suggest that the streak artifacts common to the FBP method are nearly eliminated by the PWLS+SOR method, and indicate that the proposed method for weighting the measurements is a significant factor in the improvement over FBP.     

A standard CMOS high-voltage transmitter for ultrasound medical imaging applications

A high-voltage (HV) transmitter for ultrasound medical imaging applications is designed using 0.18-µm CMOS (complementary metal oxide semiconductor) technology. The proposed HV transmitter achieves high integration by employing standard CMOS transistors in a stacked configuration with dynamic gate biasing circuit while successfully driving the capacitive output load with an HV pulse without device breakdown reliability issues. The HV transmitter, which includes the output driver and voltage level-shifters, generates up to 30-Vp-p pulses at 1.25 MHz frequency and occupies 0.035 mm² of layout area.     

Super-resolution in respiratory synchronized positron emission tomography

Respiratory motion is a major source of reduced quality in positron emission tomography (PET). In order to minimize its effects, the use of respiratory synchronized acquisitions, leading to gated frames, has been suggested. Such frames, however, are of low signal-to-noise ratio (SNR) as they contain reduced statistics. Super-resolution (SR) techniques make use of the motion in a sequence of images in order to improve their quality. They aim at enhancing a low-resolution image belonging to a sequence of images representing different views of the same scene. In this work, a maximum a posteriori (MAP) super-resolution algorithm has been implemented and applied to respiratory gated PET images for motion compensation. An edge preserving Huber regularization term was used to ensure convergence. Motion fields were recovered using a B-spline based elastic registration algorithm. The performance of the SR algorithm was evaluated through the use of both simulated and clinical datasets by assessing image SNR, as well as the contrast, position and extent of the different lesions. Results were compared to summing the registered synchronized frames on both simulated and clinical datasets. The super-resolution image had higher SNR (by a factor of over 4 on average) and lesion contrast (by a factor of 2) than the single respiratory synchronized frame using the same reconstruction matrix size. In comparison to the motion corrected or the motion free images a similar SNR was obtained, while improvements of up to 20% in the recovered lesion size and contrast were measured. Finally, the recovered lesion locations on the SR images were systematically closer to the true simulated lesion positions. These observations concerning the SNR, lesion contrast and size were confirmed on two clinical datasets included in the study. In conclusion, the use of SR techniques applied to respiratory motion synchronized images lead to motion compensation combined with improved image SNR and contrast, without any increase in the overall acquisition times.