双核多媒体处理器迎接要求苛刻的多媒体应用的挑战

为多媒体应用选择处理器是一项很复杂的工作,需要彻底分析处理器内核体系结构和外设,了解视频和音频数据流如何通过系统,并正确评估以可接受的功耗水平能够取得的处理能力.以往的解决办法还是将处理功能分成由微控制器（MCU）芯片处理的“控制部分”和由数字信号处理器（DSP）处理的“计算部分”.但是,现在出现了能将DSP和MCU功能集成到一个统一结构中的嵌入式媒体处理器（EMP）,例如ADI公司的Blackfin处理器系列产品.     

BWDSP100数字信号处理器的指令缓存器设计

本文介绍了一种应用于高性能数字信号处理器BWDSP100的指令缓存器。该指令缓存器支持超长指令字,共有三级缓冲,每级缓冲包含16个指令槽。该指令缓存器可高效完成指令执行行的提取、拼接及废弃等操作,可有效提高DSP的指令执行效率。     

LC823425：音频处理器

三洋半导体推出用于数码录音笔等便携设备的音频处理方案LC823425,包含内置硬连线MP3编码器／解码器系统,提供5mW功耗,内置数字信号处理器。     

数字处理器56F802x/3x在开关电源和电机上的应用

数字信号控制器是综合了微控制器和数字信号处理器功能的专用微处理器,其内核处理能力适用于多种类型的解决方案,其CPU通用的基本功能包括:单周期乘累加操作指令(MAC):一个指令周期内允许多次存储器存取操作:专用操作     

新型宽带数字信号处理器BSP-15及其应用

在多媒体信号处理领域，特别是视频处理方面，通常要求数字信号处理器具有针对多媒体应用的最优化的内核结构和丰富的媒体接口。而通用信号处理器在这方面的性能得不到充分发挥，为此，美国Equator公司推出了BSP系列高速宽带数字信号处理器BSP-15。该处理器与MAP-CA反向兼容，是专门以视频应用为主设计的高效DSP，在400MHz的时钟频率下，BSP-15处理能力为40GOPS（每秒400亿次整数运算），其速度相当于Pentium Ⅲ的8．5倍，是同系列MAP—CA芯片的1．33倍。由于BSP-15的核心功能是通过软件来实现高性能、大视频流的宽带应用设计，因此，结合iMMediaTools软件开发环境及其所提供的视音频库，BSP-15可为高性能的宽带应用产品如机顶盒、数字电视、视频会议系统、医疗图像产品、     

浙大数芯媒体处理器

浙大数芯是一种全新的RISC／DSP混合体系结构处理器，在一个单核流水级架构上实现RISC通用指令、DSP数据处理指令和SIMD多媒体增强指令，是多媒体数字处理和计算机体系结构研究的一次集成电路创新实践，其相应的集成开发平台进一步为嵌入式应用系统的开发提供良好的软硬件环境。     

推动初、中级汽车信息娱乐体验的Jacinto6Eco系统

DRA72x提供了加速性能的最佳组合。其中包括能在帧率为60fPS，分辨率为1080p的情况下进行H-264解码的IVA-HD视频协处理器，该视频协处理器支持标准的同步多媒体流和新兴的自带设备（BYOD）连接。此外，基于集成的数字信号处理器装载的噪音消除（ANC）、语音增强和音频后期处理算法将为驾驶员与乘客带来更优越的语音功能用户体验。     

合2为1的媒体处理器

日本松下电器产业公司日前开发出画向DVD播放机的媒体核心处理(Media Core Processor),其主要功能适用于图像处理和通信处理领域的数字信号处理。该公司把面向指令一级并行处理的甚长指令字VLIW(Very Long Instraction Word)结构处理器机芯和按顺序处理的DSP(Digital Signal Processor)机芯集成在单一硅片上,仅以54MHz时钟频率却实现3200MOPS(Million Operations Per Second)的高速运算性能。 日本松下电器产业公司开发的Media Core Processor产品,现已开始大批量投产,用于装备DVD播放机。其制造工艺、技术也是比较先进的,栅长为0.35um的CMOS     

一种新的数字信号处理器--媒体处理器DM642

数字信号处理器(DSP)自1982年问世以来，已经成为嵌入式高速计算平台的主要的实现工具。随着多媒体技术的发展，一类新的DsP器件：媒体处理器，越来越得到产业界的重视。早期有Philips的TriMediaf100和1300，及Equotor的MAPCA等；近期全球最大的DSP制造商德州仪器(TI)也推出了一款高性能媒体处理器TMS320DM642。媒体处理器的市场竞争，必然给多媒体设备的实现带来另一种有效的实现手段。本文较详细的介绍DM642的主要功能。     

高性能通用数字信号处理器指令分配

介绍了一种高性能通用数字信号处理器(DSP)指令分配技术及硬件实现方法,该技术是BWDSP100——中国第一款从指令集、体系结构到设计实现都完全自主的通用信号处理器的内置关键技术,主要解决总线分配与占用的问题。其功能是将接收到的各种不同的指令分配到相应的运算处理单元,或者将指令需要传输的数据分配到数据传输通道。文章对实现方法步骤进行了详细说明,最后给出了仿真实验结果,该技术在DSP器件内部高度集成的实用电路中真实可行。     

宽带信号处理器BSP-15

随着多媒体技术的广泛应用，采用DSP芯片设计多媒体设备，成为人们关注的方向，但是，对于可编程的媒体处理器的需求也很高。因此，一种新型的DSP芯片——媒体处理器(Media Processor)应运而生，并很快得到业界的广泛关注，而本文介绍的BSP-15正是一款典型的媒体处理器。BSP-15是专门以视频应用为中心而设计的高效DSP，以高度集成的单芯片满足了宽带产品的需要。本文介绍了BSP-15的性能、结构及其软件开发，并给出了基于BSP—15的软件并行设计。     

基于FPGA和DSP的音视频采集处理系统设计

为了实时记录飞机飞行及作业过程中的各种信息,提出了一种基于FPGA和DSP的机载音视频采集处理系统。FPGA作为协处理器,完成对高清视频信号和音频信号的采集、解码以及格式的转换。DSP作为主处理器,在Linux系统的开发环境下,以视频H.264编码算法和音频G.711编码算法为核心完成了对音视频信号的压缩和存储。该系统性能稳定,实用性强,能够满足飞机飞行6小时的5路视频和2路音频信号的采集、存储和回放,达到了设计要求,具有一定的参考价值。     

A single-chip MPEG-2 codec based on customizable media embedded processor

A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm/sup 2/ die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time.     

SIMD技术在数字图像处理中的应用研究

SIMD处理机特别适合于要求大量高速向量或矩阵计算的场合,数据缓存系统和对准网络是它的关键部件。而图像卷积是图像处理技术中最基本也是最重要的一项技术,本文根据数字图像的卷积定理对数字图像的卷积运算进行了分析,并提出了一种基于SIMD处理机的可变卷积模板的图像卷积处理器的体系结构。该处理器内部包含有接口部件、控制部件、数据缓存系统、对准电路和执行部件等。它的极高效率的数据缓存系统和对准电路成为该处理器最有特色的部分,它从根本上解决了图像卷积中的数据复用带来的CPU重复访问主存储器的问题。实现了卷积模板为3×3的图像卷积运算,从而实现了对卷积计算的硬件加速目的。最后,对这个图像卷积处理器体系结构的性能及其可扩展性进行了缜密的分析。     

基于C62的DTV实时多节目复用器设计

介绍了一种采用高速ＤＳＰ的ＤＴＶ实时多节目复用器的实现方案。系统以ＴＩ通用定点ＤＳＰＴＭＳ３２０Ｃ６２０１为主处理器,配合少量ＰＬＤ,硬件和软件设计充分利用ＤＳＰ的特点,实现将多路音频、视频和辅助数据实时复用成符合ＭＰＥＧ－２系统层传输规范的码流。系统还具有ＲＳ编码功能和加扰扩展功能。由于系统规范主要由ＤＳＰ软件实现,因而能通过修改软件以适合不同的应用场合。系统具有完备的调试电路,良好的可维护性。     

Application Specific Processor Design for H.264 Decoder with a Configurable Embedded Processor

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction‐level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.     

The impact of Mpact 2

Mpact media processors enable powerful, flexible and cost-effective multimedia in a PC. A single chip replaces today's multiboard, multichip solutions for graphics, video, audio, and communications. The architecture combines a high-bandwidth RAMBUS memory, VLIW/SIMD (single instruction, multiple data) processing, standard buses, and software programmability for the cost of a modern graphics chip. Mpact architecture uses a modified VLIW style with two RISC-like instructions per VLIW. The instructions are either executed sequentially or concurrently based on a tag in the VLIW. Classical VLIW suffers from low code density due to unused instruction fields, but the Mpact modified VLIW has the same code density as RISC instructions. Additionally, the SIMD instructions improve code density by increasing the work done by each instruction. An 8 byte word size was chosen to balance vector and scalar performance and also to balance data and instruction bandwidth. A 9 bit byte was chosen to represent color-component differences in one byte and to represent 18 bit color or 18 bit audio samples in two bytes. Hardware-dithered rounding of quantization noise allows most audio to be processed in two byte precision. The maximal multiplier precision of 24×24 was chosen for audio requirements. The article reviews the first-generation Mpact media processor and then describes the multimedia performance goals and architecture of Chromatic's second-generation media processor architecture. It then presents newer modules of the architecture in more detail     

A Single‐Chip Video/Audio CODEC for Low Bit Rate Application

In this paper, we present a design of video and audio single chip encoder/decoder for portable multimedia application. The single‐chip called as video audio signal processor (VASP) consists of a video signal processing block and an audio signal processing block. This chip has mixed hardware/software architecture to combine performance and flexibility. We designed the chip by partitioning between video and audio block. The video signal processing block was designed to implement hardwired solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bits RISC type internal controller. The audio signal processing block is implemented with software solution using a 16 bits fixed point DSP. This chip contains 142,300 gates, 22 kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size is 9.02 mm ×9.06 mm which is fabricated using 0.5 micron 3‐layer metal CMOS technology.     

A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation

As DSP (Digital Signal Processing) applications become more complex, there is also a growing need for new architectures supporting efficient high-level language compilers. We try to synthesize a new DSP processor architecture by adding several DSP processor specific features to a RISC core that has a compiler friendly structure, such as many general-purpose registers and orthogonal instructions. The synthesized digital signal processor supports single-cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping capabilities in addition to ordinary RISC instructions. The compiler for the new architecture is quickly implemented by developing a code-converter that modifies the assembly codes that are generated by the RISC compiler. The performance effects of adding each of these as well as all the combined features are evaluated using seven DSP-kernel benchmarks, a QCELP vocoder, and an MPEG video decoder. The effects of CPU clock frequency change due to the addition of these features are also considered. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.     

TMS320C6X为核心的实时视频图像处理器的初步设计

探讨了TMS320C6X实时视频数字图像处理器的总体结构、各个部分的构成、功能以及所选用的主要器件,阐述了该设计方案的主要特点。最后指出了视频图像处理器关键器件的一些新进展。