结构化ASIC:替代标准单元ASIC

在历史上,系统设计人员和OEM供货商依靠专用集成电路(ASIC)实现高性能、低功耗、低成本组件,这类组件使终端产品与其竞争产品有明显的区别.     

深亚微米ASIC:系统设计不可或缺的技术

要想充分利用深亚微米ASIC的全部速度和复杂性,就需要知道IC物理性质是如何变化的,并要知道如何去选择能使你达到深亚微米ASIC功能的设计工具。     

Analysis of Cell-averaging Based Detectors for χ2 Fluctuating Targets in Multitarget Environments

The χ^2 family of signal fluctuation distributions represents the main fluctuation models which most radar targets follow it in their reflections. This family can be categorized as fluctuation distribution with two degrees of freedom and those with four degrees of freedom. The first category represents all important class of fluctuation models which when illuminated by a coherent pulse train, return a train of fully correlated pulses （Swerling Ⅰ model） or fully decorrelated pulses （Swerling Ⅱ model）. The detection of this type of fluctuating targets is therefore of great importance. This paper is devoted to the analysis of Cell-Averaging （CA） based detectors for the case where the radar receiver noncoherently integrates M square-law detected pulses and the signal fluctuation obeys 2 statistics with two degrees of freedom. These detectors include the Mean-Of （MO）, the Greatest-Of （GO） and the Smallest-Of（SO） schemes. In these processors, the estimation of the noise power levels from the leading and the trailing reference windows is based on the CA technique. Exact formulas for the detection probabilities are derived, in the absence as well as in the presence of spurious targets. The primary and the secondary interfering targets are assumed to be fluctuating in accordance with the χ^2 fluctuation model with two degrees of freedom （SWI ＆ SWII）. The numerical results show that the MO version has the best homogeneous performance, the SO scheme has the best multiple-target performance, while the GO procedure does not offer any merits, neither in the absence nor in the presence of outlying targets.     

ASIC:中国电子设计业的新选择

要缩短我国电子业与发达国家之间的距离,需要做的事很多,短缺的东西很多。但是我们要有一些突破点。技术密集的领域对一贯被认为头脑好用的中国人来说是可以入手下功夫的。专用集成电路(ASIC)正被国家列为要大力推广发展的技术。今年1月,由北京集成电路设计中心召集成立了“全国ICCAD联谊会”,ASIC电路是该联谊会的重点课题。 ASIC电路在当今世界飞速发展,对电子技术的发展具有变革性的意     

ASIC和ASSP:今日的IC之路

专用集成电路(ASIC)是按用户的具体要求,为用户制作的有特定用途的集成电路。目前,对A-SIC的门类有狭义和广义之分。狭义ASIC包括全定制集成电路、半定制集成电路和可编程序逻辑器件(PLD)。广义ASIC除包括狭义ASIC之外,还包括专用标准产品(ASSP)和专用存储器集成电路(ASMIC)等。各种门阵列属于半定制的ASIC。专用集成电路具有研制周期短和产品更新快等优点。军用集成电路的要     

从ASIC到PLD:半导体技术市场趋势展望

根据Dataquest的统计数据,PLD是半导体行业中增长最快的细分市场,复合年度增长率(CAGR)达19.5%。这一数字是ASIC市场预计9%复合年度增长率的两倍多。过去,可编程芯片在半导体行业中一直是很重要的外围器件,由于其灵活性而被广泛用于ASIC仿真、胶合逻辑,或者作为适应标准变化的一种解决方案。今天,在与ASIC和ASSP的市场份额竞争中,PLD取得了很大进步。目前,该技术正逐渐成为主要设计技术,而且业界也在普遍向可编程芯片转移。作为重要的ASIC替代解决方案,PLD现在已成为大势所趋。促进这种发展的主要因素是FPGA技术的重大进展…     

上海爱普生ASIC设计中心推行“省”的理念

近几年,随着国内电子产业的迅猛发展,特别是通信产业出现的一次次群体突破,使人们对如何能真正掌握具有自主知识产权的产品有了更深一层的认识,随之而来的就是对专用集成电路,即ASIC     

A sigma–delta interface ASIC for force-feedback micromachined capacitive accelerometer

A single-loop fourth-order sigma?Cdelta (????) interface circuit for micromachined accelerometer is presented in this study. Two additional electronic integrators are cascaded with the micromachine sensing element to form a fourth-order loop filter to eliminate quantization noise. A precise model for the overall system is set up based on nonlinear model of 1-bit quantizer. Three main noise sources affecting the overall system resolution of a ???? accelerometer: mechanical noise, electronic noise and quantization noise are analyzed in more detail. A switched-capacitor charge integrator and correlated double sampling are applied to reduce input-referred electronic noise. The ASIC is fabricated in 0.5???m two-metal two-poly n-well CMOS process, and test results show that the noise density floors of the open-loop and closed-loop modes are 12 and 80???g/Hz^1/2, respectively, the sensitivity is 1.25?V/g, the full measurement range can be achieved from ?2 to +2?g, and the power dissipation is 40?mW.     

FPGA到ASIC转换:从原型到生产

许多工程师都采用这样的传统方法:利用FPGA进行设计,然后在产品需要更大批量或更高性能的时候再将设计转换为采用ASIC。这种做法的问题在于FPGA是标准产品,有固定的设计约束和要求,以及定义明确的标准功能和越来越多的免费可选功能。将FPGA设计转换为采用不同设计约束和有不同成本构成因素的ASIC器件可能意味着效率降低,因为FPGA器件中的许多“免费”选择,在ASIC中都需要一定的成本或性能代价。反过来,由于在整个设计周期中精力都集中于FPGA器件,因此可能不得不忽略许多只有ASIC才能提供的特性,从而限制了设计自由度并增加了…     

颓势已现，ASIC能否涅槃重生？——全球电子产业高峰论坛聚焦“ASIC技术未来走向”

硅谷如此多娇，引无数英雄竞折腰。前不久第五届全球电子产业高峰论坛（Electronics Summit2007）在美国加州Monterey举行，吸引到38家半导体公司高层技术及运营管理人员参会，更有全球57家电子行业最具影响力的媒体汇聚于此。在媒体的关注和参与中，半导体行业的精英们就技术发展趋势等热点问题激烈交锋，畅所欲谈。     

“SoC设计山寨化”背后：设计服务推动ASIC复苏

设计服务通过缩短并降低SoC设计的时间、成本和风险门槛,揭开TSoC设计的神秘面纱,推动了ASIC需求的复苏,同时也改变了Fabless在整个半导体产业链中的定位和价值。     

ASIC设计可选方案:运用低成本FPGA进行系统集成

根据摩尔定律，每隔18个月，处理器上的晶体管数量和性能就会翻一番。现在在其他很多相关领域比如存储器、总线接口、通信协议等也无一例外地遵循这一定律。