Low Voltage and Ferroelectric 2D Electron Devices Using Lead‐Free BaxSr1‐xTiO3 and MoS2 Channel

Coupling between non‐toxic lead‐free high‐k materials and 2D semiconductors is achieved to develop low voltage field effect transistors (FETs) and ferroelectric non‐volatile memory transistors as well. In fact, low voltage switching ferroelectric memory devices are extremely rare in 2D electronics. Now, both low voltage operation and ferroelectric memory function have been successfully demonstrated in 2D‐like thin MoS₂ channel FET with lead‐free high‐k dielectric Ba_xSr_1‐xTiO₃ (BST) oxides. When the BST surface is coated with a 5.5‐nm‐ultrathin poly(methyl methacrylate) (PMMA)‐brush for improved roughness, the MoS₂ FET with BST (x = 0.5) dielectric results in an extremely low voltage operation at 0.5 V. Moreover, the BST with an increased Ba composition (x = 0.8) induces quite good ferroelectric memory properties despite the existence of the ultrathin PMMA layer, well switching the MoS₂ FET channel states in a non‐volatile manner with a ±3 V low voltage pulse. Since the employed high‐k dielectric and ferroelectric oxides are lead‐free in particular, the approaches for applying high‐k BST gate oxide for 2D MoS₂ FET are not only novel but also practical towards future low voltage nanoelectronics and green technology.     

Fully Transparent p‐MoTe2 2D Transistors Using Ultrathin MoOx/Pt Contact Media for Indium‐Tin‐Oxide Source/Drain

Since transition metal dichalcogenide (TMD) semiconductors are found as 2D van der Waals materials with a discrete energy bandgap, many 2D‐like thin field effect transistors (FETs) and PN diodes are reported as prototype electrical and optoelectronic devices. As a potential application of display electronics, transparent 2D FET devices are also reported recently. Such transparent 2D FETs are very few in report, yet no p‐type channel 2D‐like FETs are seen. Here, 2D‐like thin transparent p‐channel MoTe₂ FETs with oxygen (O₂) plasma‐induced MoO_x/Pt/indium‐tin‐oxide (ITO) contact are reported for the first time. For source/drain contact, 60 s short O₂ plasma and ultrathin Pt‐deposition processes on MoTe₂ surface are sequentially introduced before ITO thin film deposition and patterning. As a result, almost transparent 2D FETs are obtained with a decent mobility of ≈5 cm² V^?1 s^?1, a high ON/OFF current ratio of ≈10⁵, and 70% transmittance. In particular, for normal MoTe₂ FETs without ITO, O₂ plasma process greatly improves the hole injection efficiency and device mobility (≈60 cm² V^?1 s^?1), introducing ultrathin MoO_x between Pt source/drain and MoTe₂. As a final device application, a photovoltaic current modulator, where the transparent FET stably operates as gated by photovoltaic effects, is integrated.     

Anisotropic Growth of Nonlayered CdS on MoS2 Monolayer for Functional Vertical Heterostructures

2D semiconductors have emerged as a crucial material for use in next‐generation optotelectronics. Similar to microelectronic devices, 2D vertical heterostructures will most likely be the elemental components for future nanoscale electronics and optotelectronics. To date, the components of mostly reported 2D van der Waals heterostructures are restricted to layer crystals. In this work, it is demonstrated that nonlayered semiconductors of CdS can be epitaxially grown on to 2D layered MoS₂ substrate to form a new quasi vertical heterostructure with clean interface by chemical vapor deposition. Photodetectors based on this CdS/MoS₂ heterostructure show broader wavelength response and ≈50‐fold improvement in photoresponsivity, compared to the devices fabricated from MoS₂ monolayer only. This research opens up a way to fabricate a variety of functional quasi heterostructures from nonlayered semiconductors.     

Asymmetric Schottky Contacts in Bilayer MoS2 Field Effect Transistors

The high‐bias electrical characteristics of back‐gated field‐effect transistors with chemical vapor deposition synthesized bilayer MoS₂ channel and Ti Schottky contacts are discussed. It is found that oxidized Ti contacts on MoS₂ form rectifying junctions with ≈0.3 to 0.5 eV Schottky barrier height. To explain the rectifying output characteristics of the transistors, a model is proposed based on two slightly asymmetric back‐to‐back Schottky barriers, where the highest current arises from image force barrier lowering at the electrically forced junction, while the reverse current is due to Schottky‐barrier‐limited injection at the grounded junction. The device achieves a photoresponsivity greater than 2.5 A W^?1 under 5 mW cm^?2 white‐LED light. By comparing two‐ and four‐probe measurements, it is demonstrated that the hysteresis and persistent photoconductivity exhibited by the transistor are peculiarities of the MoS₂ channel rather than effects of the Ti/MoS₂ interface.     

Controlled Vapor–Solid Deposition of Millimeter‐Size Single Crystal 2D Bi2O2Se for High‐Performance Phototransistors

Atomically thin 2D materials have received intense interest both scientifically and technologically. Bismuth oxyselenide (Bi₂O₂Se) is a semiconducting 2D material with high electron mobility and good stability, making it promising for high‐performance electronics and optoelectronics. Here, an ambient‐pressure vapor–solid (VS) deposition approach for the growth of millimeter‐size 2D Bi₂O₂Se single crystal domains with thicknesses down to one monolayer is reported. The VS‐grown 2D Bi₂O₂Se has good crystalline quality, chemical uniformity, and stoichiometry. Field‐effect transistors (FETs) are fabricated using this material and they show a small contact resistivity of 55.2 Ω cm measured by a transfer line method. Upon light irradiation, a phototransistor based on the Bi₂O₂Se FETs exhibits a maximum responsivity of 22 100 AW^?1, which is a record among currently reported 2D semiconductors and approximately two orders of magnitude higher than monolayer MoS₂. The Bi₂O₂Se phototransistor shows a gate tunable photodetectivity up to 3.4 × 10¹⁵ Jones and an on/off ratio up to ≈10⁹, both of which are much higher than phototransistors based on other 2D materials reported so far. The results of this study indicate a method to grow large 2D Bi₂O₂Se single crystals that have great potential for use in optoelectronic applications.     

Improved Electrical Contact Properties of MoS2‐Graphene Lateral Heterostructure

2D materials have been extensively investigated in view of their excellent electrical/optical properties, with particular attention directed at the fabrication of vertical or lateral heterostructures. Although such heterostructures exhibit unexpected or enhanced properties compared to those of singly used 2D materials, their fabrication is challenged by the difficulty of realizing spatial control and large area integration. Herein, MoS₂ is grown on patterned graphene at variable temperatures, combining the concept of lateral heterostructure with chemical vapor deposition to realize large area growth with precise spatial control, and probe the spatial distribution of graphene and MoS₂ by a number of instrumental techniques. The prepared MoS₂‐graphene lateral heterostructure is employed to construct field effect transistors with graphene as the source/drain and MoS₂ as the channel, and the performance of these transistors (on/off ratio ≈10⁹, maximum field effect mobility = 8.5 cm² V^?1 s^?1) is shown to exceed that of their MoS₂‐only counterparts.     

Graphene-Enhanced Metal Transfer Printing for Strong van der Waals Contacts between 3D Metals and 2D Semiconductors

2D semiconductors have shown great potentials for ultra-short channel field-effect transistors (FETs) in next-generation electronics. However, because of intractable surface states and interface barriers, it is challenging to realize high-quality contacts with low contact resistances for both p- and n- 2D FETs. Here, a graphene-enhanced van der Waals (vdWs) integration approach is demonstrated, which is a multi-scale (nanometer to centimeter scale) and reliable (≈100% yield) metal transfer strategy applicable to various metals and 2D semiconductors. Scanning transmission electron microscopy imaging shows that 2D/2D/3D semiconductor/graphene/metal interfaces are atomically flat, ultraclean, and defect-free. First principles calculations indicate that the sandwiched graphene monolayer can eliminate gap states induced by 3D metals in 2D semiconductors. Through this approach, Schottky barrier-free contacts are realized on both p- and n-type 2D FETs, achieving p-type MoTe₂, p-type black phosphorus and n-type MoS₂ FETs with on-state current densities of 404, 1520, and 761 µA µm⁻¹, respectively, which are among the highest values reported in literature.     

Amorphous Boron Nitride: A Universal,Ultrathin Dielectric For 2D Nanoelectronics

Next‐generation nanoelectronics based on 2D materials ideally will require reliable, flexible, transparent, and versatile dielectrics for transistor gate barriers, environmental passivation layers, capacitor spacers, and other device elements. Ultrathin amorphous boron nitride of thicknesses from 2 to 17 nm, described in this work, may offer these attributes, as the material is demonstrated to be universal in structure and stoichiometric chemistry on numerous substrates including flexible polydimethylsiloxane, amorphous silicon dioxide, crystalline Al₂O₃, other 2D materials including graphene, 2D MoS₂, and conducting metals and metal foils. The versatile, large area pulsed laser deposition growth technique is performed at temperatures less than 200 °C and without modifying processing conditions, allowing for seamless integration into 2D device architectures. A device‐scale dielectric constant of 5.9 ± 0.65 at 1 kHz, breakdown voltage of 9.8 ± 1.0 MV cm^?1, and bandgap of 4.5 eV were measured for various thicknesses of the ultrathin a‐BN material, representing values higher than previously reported chemical vapor deposited h‐BN and nearing single crystal h‐BN.     

Nonvolatile Floating‐Gate Memories Based on Stacked Black Phosphorus–Boron Nitride–MoS2 Heterostructures

Research on van der Waals heterostructures based on stacked 2D atomic crystals is intense due to their prominent properties and potential applications for flexible transparent electronics and optoelectronics. Here, nonvolatile memory devices based on floating‐gate field‐effect transistors that are stacked with 2D materials are reported, where few‐layer black phosphorus acts as channel layer, hexagonal boron nitride as tunnel barrier layer, and MoS₂ as charge trapping layer. Because of the ambipolar behavior of black phosphorus, electrons and holes can be stored in the MoS₂ charge trapping layer. The heterostructures exhibit remarkable erase/program ratio and endurance performance, and can be developed for high‐performance type‐switching memories and reconfigurable inverter logic circuits, indicating that it is promising for application in memory devices completely based on 2D atomic crystals.     

Enhanced Quality of Wafer‐Scale MoS2 Films by a Capping Layer Annealing Process

Wafer‐scale, single‐crystalline 2D semiconductors without grain boundaries and defects are needed for developing reliable next‐generation integrated 2D electronics. Unfortunately, few literature reports exist on the growth of 2D semiconductors with single‐crystalline structure at the wafer scale. It is shown that direct sulfurization of as‐deposited epitaxial MoO₂ films (especially, with thicknesses more than ≈5 nm) produces textured MoS₂ films. This texture is inherited from the high density of defects present in the as‐prepared epitaxial MoO₂ film. In order to eliminate the texture of the converted MoS₂ films, a new capping layer annealing process (CLAP) is introduced to improve the crystalline quality of as‐deposited MoO₂ films and minimize its defects. It is demonstrated that sulfurization of the CLAP‐treated MoO₂ films leads to the formation of single‐crystalline MoS₂ films, instead of textured films. It is shown that the single‐crystalline MoS₂ films exhibit field‐effect mobility of 6.3 cm² V^?1 s^?1, which is 15 times higher than that of textured MoS₂. These results can be attributed to the smaller concentration of defects in the single‐crystalline films.     

Phototransistors with Negative or Ambipolar Photoresponse Based on As‐Grown Heterostructures of Single‐Walled Carbon Nanotube and MoS2

A facile synthesis method for the heterostructures of single‐walled carbon nanotubes (SWCNTs) and few‐layer MoS₂ is reported. The heterostructures are realized by in situ chemical vapor deposition of MoS₂ on individual SWCNTs. Field effect transistors based on the heterostructures display different transfer characteristics depending on the formation of MoS₂ conduction channels along SWCNTs. Under light illumination, negative photoresponse originating from charge transfer from MoS₂ to SWCNT is observed while positive photoresponse is observed in MoS₂ conduction channels, leading to ambipolar photoresponse in devices with both SWCNT and MoS₂ channels. The heterostructure phototransistor, for negative photoresponse, exhibits high responsivity (100–1000 AW^?1) at low bias voltages (0.1 V) in the visible spectrum (500–700 nm) by combining high mobility conduction channel (SWCNT) with efficient light absorber (MoS₂).     

Transparent Photo‐Stable Complementary Inverter with an Organic/Inorganic Nanohybrid Dielectric Layer

Transparent electronics has been one of the key terminologies forecasting the ubiquitous technology era. Several researchers have thus extensively developed transparent oxide‐based thin‐film transistors (TFTs) on glass and plastic substrates. However, work in transparent electronics has been limited mostly to high‐voltage devices operating at more than a few tens of volts, and has mainly focused on transparent display drivers. Low‐voltage logic devices, such as transparent complementary inverters, operating in an electrically stable and photo‐stable manner, are now very necessary to practically realize transparent electronics. Electrically stable dielectrics with high strength and high capacitance must also be proposed to support this mission, and simultaneously these dielectrics must be compatible with both n‐ and p‐channel TFTs in device fabrication. Here, a nanohybrid dielectric layer that is composed of multiple units of inorganic oxide and organic self‐assembled monolayer is proposel to support a transparent complementary TFT inverter operating at 3 V.     

High‐Performance Monolayer MoS2 Films at the Wafer Scale by Two‐Step Growth

To realize multifunctional devices at the wafer scale, the growth process of monolayer (ML) 2D semiconductors must meet two key requirements: 1) growth of continuous and homogeneous ML film at the wafer scale and 2) controllable tuning of the properties of the ML film. However, there is still no growth method available that fulfills both of these criteria. Here, the first report is presented on the preparation of continuous and uniform ML MoS₂ films through a two‐step process at the wafer scale. Unlike in previous ML MoS₂ film growth processes, the ML MoS₂ film can be uniformly modulated across the wafer in terms of material structure and composition, exciton state, and electronic transport performance. A significant result is that the high‐quality wafer‐scale ML MoS₂ films realize superior electronic performance compared to reported two‐step‐grown films, and it even matches or exceeds reported ML MoS₂ films prepared by other processes. The transistor performance of the optimized ML film achieves a field effect mobility of 10 to 30 cm² V^?1 s^?1, an on/off current ratio of about 10⁷, and hysteresis as low as 0.4 V.     

Fully Transparent Non‐volatile Memory Thin‐Film Transistors Using an Organic Ferroelectric and Oxide Semiconductor Below 200 °C

A fully transparent non‐volatile memory thin‐film transistor (T‐MTFT) is demonstrated. The gate stack is composed of organic ferroelectric poly(vinylidene fluoride‐trifluoroethylene) [P(VDF‐TrFE)] and oxide semiconducting Al‐Zn‐Sn‐O (AZTO) layers, in which thin Al₂O₃ is introduced between two layers. All the fabrication processes are performed below 200 °C on the glass substrate. The transmittance of the fabricated device was more than 90% at the wavelength of 550 nm. The memory window obtained in the T‐MTFT was 7.5 V with a gate voltage sweep of ?10 to 10 V, and it was still 1.8 V even with a lower voltage sweep of ?6 to 6 V. The field‐effect mobility, subthreshold swing, on/off ratio, and gate leakage currents were obtained to be 32.2 cm² V^?1 s^?1, 0.45 V decade^?1, 10⁸, and 10^?13 A, respectively. All these characteristics correspond to the best performances among all types of non‐volatile memory transistors reported so far, although the programming speed and retention time should be more improved.     

Fully Patterned Low‐Voltage Transparent Metal Oxide Transistors Deposited Solely by Chemical Spray Pyrolysis

All‐inorganic transparent thin‐film transistors deposited solely by the solution processing method of spray pyrolysis are reported. Different precursor materials are employed to create conducting and semiconducting species of ZnO acting as electrodes and active channel material, respectively, as well as zirconium oxide as gate dielectric layer. Additionally, a simple stencil mask system provides sufficient resolution to realize the necessary geometric patterns. As a result, fully functional low‐voltage n‐type transistors with a mobility of 0.18 cm² V^?1 s^?1 can be demonstrated via a technique that bears the potential for upscaling. A detailed microscopic evaluation of the channel region by electron diffraction, high‐resolution and analytical TEM confirms the layer stacking and provides detailed information on the chemical composition and nanocrystalline nature of the individual layers.     

Enhanced Performance of Self‐Assembled Monolayer Field‐Effect Transistors with Top‐Contact Geometry through Molecular Tailoring,Heated Assembly,and Thermal Annealing

Low‐voltage self‐assembled monolayer field‐effect transistors (SAMFETs) that operate under an applied bias of less than ?3 V and a high hole mobility of 10^?2 cm² V^?1 s^?1 are reported. A self‐assembled monolayer (SAM) with a quaterthiophene semiconducting core and a phosphonic acid binding group is used to fabricate SAMFETs on both high‐voltage (AlO_x/300 nm SiO₂) and low‐voltage (HfO₂) dielectric platforms. High performance is achieved through enhanced SAM packing density via a heated assembly process and through improved electrical contact between SAM semiconductor and metal electrodes. Enhanced electrical contact is obtained by utilizing a functional methylthio head group combined with thermal annealing post gold source/drain electrode deposition to facilitate the interaction between SAM and electrode.     

Low‐Temperature‐Processed Printed Metal Oxide Transistors Based on Pure Aqueous Inks

Additive patterning of transparent conducting metal oxides at low temperatures is a critical step in realizing low‐cost transparent electronics for display technology and photovoltaics. In this work, inkjet‐printed metal oxide transistors based on pure aqueous chemistries are presented. These inks readily convert to functional thin films at lower processing temperatures (T ≤ 250 °C) relative to organic solvent‐based oxide inks, facilitating the fabrication of high‐performance transistors with both inkjet‐printed transparent electrodes of aluminum‐doped cadmium oxide (ACO) and semiconductor (InO_x ). The intrinsic fluid properties of these water‐based solutions enable the printing of fine features with coffee‐ring free line profiles and smoother line edges than those formed from organic solvent‐based inks. The influence of low‐temperature annealing on the optical, electrical, and crystallographic properties of the ACO electrodes is investigated, as well as the role of aluminum doping in improving these properties. Finally, the all‐aqueous‐printed thin film transistors (TFTs) with inkjet‐patterned semiconductor (InO_x ) and source/drain (ACO) layers are characterized, which show ideal low contact resistance (R _c < 160 Ω cm) and competitive transistor performance (µ _lin up to 19 cm² V^?1 s^?1, Subthreshold Slope (SS) ≤150 mV dec^?1) with only low‐temperature processing (T ≤ 250 °C).     

Transition Metal Dichalcogenide‐Based Transistor Circuits for Gray Scale Organic Light‐Emitting Displays

Two types of transition metal dichalcogenide (TMD) transistors are applied to demonstrate their possibility as switching/driving elements for the pixel of organic light‐emitting diode (OLED) display. Such TMD materials are 6 nm thin WSe₂ and MoS₂ as a p‐type and n‐type channel, respectively, and the pixel is thus composed of external green OLED and nanoscale thin channel field effect transistors (FETs) for switching and driving. The maximum mobility of WSe₂‐FETs either as switch or as driver is ≈30 cm² V^?1 s^?1, in linear regime of the gate voltage sweep range. Digital (ON/OFF‐switching) and gray‐scale analogue operations of OLED pixel are nicely demonstrated. MoS₂ nanosheet FET‐based pixel is also demonstrated, although limited to alternating gray scale operation of OLED. Device stability issue is still remaining for future study but TMD channel FETs are very promising and novel for their applications to OLED pixel because of their high mobility and I _D ON/OFF ratio.     

A Surface Tailoring Method of Ultrathin Polymer Gate Dielectrics for Organic Transistors: Improved Device Performance and the Thermal Stability Thereof

Tailoring the surface of the dielectric layer is of critical importance to form a good interface with the following channel layer for organic thin film transistors (OTFTs). Here, a simple surface treatment method is applied onto an ultrathin (<15 nm) organosilicon‐based dielectric layer via the initiated chemical vapor deposition (iCVD) to make it compatible with organic semiconductors without degrading its insulating property. A molecular‐thin oxide capping layer is formed on a 15 nm thick poly(1,3,5‐trimetyl‐1,3,5‐trivinyl cyclotrisiloxane) (pV3D3) by a brief oxygen plasma treatment. The capping layer greatly enhances the thermal stability of the dielectrics, without degrading the original mechanical flexibility and insulating performance of the dielectrics. Moreover, the surface silanol functionalities formed by the plasma treatment can also be utilized for the surface modification with silane compounds. The surface‐modified dielectrics are applied to fabricate low‐voltage operating (<5 V) pentacene‐based OTFTs. The highest field‐effect mobility of the device with the surface‐treated 15 nm thick pV3D3 is 0.59 cm² V^?1 s^?1, which is improved up to two times compared to the TFT with the pristine pV3D3. It is believed that the simple surface treatment method can widely extend the applicability of the highly robust, ultrathin, and flexible pV3D3 gate dielectrics to design the surface of the dielectrics to match well various kinds of organic semiconductors.     

Nanoscale Selective Passivation of Electrodes Contacting a 2D Semiconductor

2D semiconducting materials have become the central component of various nanoelectronic devices and sensors. For sensors operating in liquid, it is crucial to efficiently block the electron transfer that occurs between the electrodes contacting the 2D material and the interfering redox species. This reduces current leakages and preserves a good signal‐to‐noise ratio. Here, a simple electrochemical method is presented for passivating the electrodes contacting a monolayer of MoS₂, a representative of transition metal dichalcogenide semiconductors. The method is based on blocking the electrode surface by a thin and compact layer of electronically nonconductive poly(phenylene oxide), PPO, formed by electrochemical polymerization of phenol. Since the phenol polymerization occurs in the potential window where MoS₂ is electrochemically inactive, the PPO deposition is area‐selective, limited to the electrode surface. The deposited PPO film is characterized by electrochemical, X‐ray photoelectron spectroscopy, scanning electron microscopy, and atomic force microscopy techniques. The applicability of this method is demonstrated by coating the electrodes of a MoS₂‐based field‐effect transistor coupled with a nanopore. The highly selective deposition, the simple approach, and the compatibility with MoS₂ makes this method a good strategy for efficient insulation of micro‐ and nanoelectrodes contacting 2D semiconductor‐based devices.