首页 | 本学科首页   官方微博 | 高级检索  
相似文献
 共查询到20条相似文献,搜索用时 15 毫秒
1.
A technique has been developed to fabricate transistors using a continuously scaled 0-2.5-nm SiO/sub 2/ interface layer between a silicon substrate and high-/spl kappa/ dielectric, on a single wafer. The transistor results are promising with good mobility values and drive current. The slant-etching process has no detrimental effect on the electrical characteristics of the Si/SiO/sub 2/ interface. This technique provides a powerful tool in examining the effect of the process variations on device performance.  相似文献   

2.
In this paper, atomic layer deposition (ALD) and ultraviolet ozone oxidation (UVO) of zirconium and hafnium oxides are investigated for high-/spl kappa/ dielectric preparation in Ge MOS devices from the perspectives of thermodynamic stability and electrical characteristics. Prior to performing these deposition processes, various Ge surface preparation schemes have been examined to investigate their effects on the resulting electrical performance of the Ge MOS capacitors. Interfacial layer-free ALD high-/spl kappa/ growth on Ge could be obtained; yet, insertion of a stable interfacial layer greatly enhanced the electrical characteristics but with a compromise for equivalent dielectric thickness scalability. On the other hand, interfacial layer-free UVO high-/spl kappa/ growth on Ge was demonstrated with minimal capacitance-voltage hysteresis and sub-1.0-nm capacitance equivalent thickness. Finally, the leakage conduction and scalability of these nanoscale Ge MOS dielectrics are discussed and are shown to outperform their Si counterparts.  相似文献   

3.
A new parameter extraction technique has been outlined for high-/spl kappa/ gate dielectrics that directly yields values of the dielectric capacitance C/sub di/, the accumulation layer surface potential quotient, /spl beta//sub acc/, the flat-band voltage, the surface potential /spl phi//sub s/, the dielectric voltage, the channel doping density and the interface charge density at flat-band. The parallel capacitance, C/sub p/(=C/sub sc/+C/sub it/), was found to be an exponential function of /spl phi//sub s/ in the strong accumulation regime, for seven different high-/spl kappa/ gate dielectrics. The slope of the experimental lnC/sub p/(/spl phi//sub s/) plot, i.e., |/spl beta//sub acc/|, was found to depend strongly on the physical properties of the high-/spl kappa/ dielectric, i.e., was inversely proportional to [(/spl phi//sub b/m/sup *//m)/sup 1/2/K/C/sub di/], where /spl phi//sub b/ is the band offset, and m/sup */ is the effective tunneling mass. Extraction of /spl beta//sub acc/ represented an experimental carrier confinement index for the accumulation layer and an experimental gate-dielectric direct-tunneling current index. /spl beta//sub acc/ may also be an effective tool for monitoring the effects of post-deposition annealing/processing.  相似文献   

4.
Schottky-barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric, HfN-TaN metal gate and self-aligned NiGe S/D. The drain drivability is improved over the silicon counterpart with PtSi S/D by as much as /spl sim/5 times due to the lower hole Schottky barrier of the NiGe-Ge contact than that of PtSi-Si contact as well as the higher mobility of Ge channel than that of Si.  相似文献   

5.
Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.  相似文献   

6.
We report the impact of high work-function (/spl Phi//sub M/) metal gate and high-/spl kappa/ dielectrics on memory properties of NAND-type charge trap Flash (CTF) memory devices. In this paper, theoretical and experimental studies show that high /spl Phi//sub M/ gate and high permittivity (high-/spl kappa/) dielectrics play a key role in eliminating electron back tunneling though the blocking dielectric during the erase operation. Techniques to improve erase efficiency of CTF memory devices with a fixed metal gate by employing various chemicals and structures are introduced and those mechanisms are discussed. Though process optimization of high /spl Phi//sub M/ gate and high-/spl kappa/ materials, enhanced CTF device characteristics such as high speed, large memory window, and good reliability characteristics of the CTF devices are obtained.  相似文献   

7.
A quantum-mechanical (QM) model is presented for accumulation gate capacitance of MOS structures with high-/spl kappa/ gate dielectrics. The model incorporates effects due to penetration of wave functions of accumulation carriers into the gate dielectric. Excellent agreement is obtained between simulation and experimental C-V data. It is found that the slope of the C-V curves in weak and moderate accumulation as well as gate capacitance in strong accumulation varies from one dielectric material to another. Inclusion of penetration effect is essential to accurately describe this behavior. The physically based calculation shows that the relationship between the accumulation semiconductor capacitance and Si surface potential may be approximated by a linear function in moderate accumulation. Using this relationship, a simple technique to extract dielectric capacitance for high-/spl kappa/ gate dielectrics is proposed. The accuracy of the technique is verified by successfully applying the method to a number of different simulated and experimental C-V characteristics. The proposed technique is also compared with another method available in the literature. The improvements made in the proposed technique by properly incorporating QM and other physical effects are clearly demonstrated.  相似文献   

8.
This paper presents a novel metal-oxide-nitride-oxide-silicon (MONOS)-type nonvolatile memory structure using hafnium oxide (HfO/sub 2/) as tunneling and blocking layer and tantalum pentoxide (Ta/sub 2/O/sub 5/) as the charge trapping layer. The superiorities of such devices to traditional SiO/sub 2/-Si/sub 3/N/sub 4/-SiO/sub 2/ stack devices in obtaining a better tradeoff between faster programming and better retention are illustrated based on a band engineering analysis. The experimental results demonstrate that the fabricated devices can be programmed as fast as 1 /spl mu/s and erased from 10 ns at an 8-V gate bias. The retention decay rate of this device is improved by a factor more than three as compared to the conventional MONOS/SONOS type devices. Excellent endurance and read disturb performance are also demonstrated.  相似文献   

9.
We report the successful growth of MOS capacitor stacks with low temperature strained epitaxial Ge or Si/sub 1-x/Ge/sub x/(x=0.9) layer directly on Si substrates, and with HfO/sub 2/(EOT=9.7 /spl Aring/) as high-/spl kappa/ dielectrics, both using a novel remote plasma-assisted chemical vapor deposition technique. These novel MOS capacitors, which were fabricated entirely at or below 400/spl deg/C, exhibit normal capacitance-voltage and current-voltage characteristics.  相似文献   

10.
Substituted aluminum (SA) metal gate on high-/spl kappa/ gate dielectric is successfully demonstrated. Full substitution of polysilicon with Al is achieved for a Ti-Al-polysilicon-HfAlON gate structure by a low-temperature annealing at 450/spl deg/C. The SA gate on HfAlON dielectric shows a very low work function of 4.25eV, which is well suitable for bulk nMOSFETs. The SA process is fully free from the Fermi-level pinning problem. In addition, the SA process also shows improved uniformity in leakage current distribution compared to fully silicided metal gate.  相似文献   

11.
Dielectric relaxation currents in SiO/sub 2//Al/sub 2/O/sub 3/ and SiO/sub 2//HfO/sub 2/ high-/spl kappa/ dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-/spl kappa/ dielectric stacks. It is found that high-/spl kappa/ dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high-/spl kappa/ dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO/sub 2//high-/spl kappa/ interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO/sub 2//high-/spl kappa/ interface is a key requirement for high-/spl kappa/ dielectric stack application and reliability in MOS devices.  相似文献   

12.
This letter reports the observation of a process integration issue that arises when large doses of nitrogen (>1/spl times/10/sup 15/ cm/sup -2/) are incorporated in oxynitride gate dielectric films targeting equivalent oxide thickness of 11-13 /spl Aring/. It is shown that capacitance-extracted active doping density at the polysilicon/oxynitride (poly/SiON) interface of boron-doped p/sup +/-polysilicon gated pMOSFETs decreases with increasing nitrogen dose of the oxynitride film as measured by X-ray photoelectron spectroscopy. A physical mechanism is proposed to explain experimental observations.  相似文献   

13.
In this letter, we report successful fabrication of germanium n-MOSFETs on lightly doped Ge substrates with a thin HfO/sub 2/ dielectric (equivalent oxide thickness /spl sim/10.8 /spl Aring/) and TaN gate electrode. The highest peak mobility (330 cm/sup 2//V/spl middot/s) and saturated drive current (130 /spl mu/A/sq at V/sub g/--V/sub t/=1.5 V) have been demonstrated for n-channel bulk Ge MOSFETs with an ultrathin dielectric. As compared to Si control devices, 2.5/spl times/ enhancement of peak mobility has been achieved. The poor performance of Ge n-MOSFET devices reported recently and its mechanism have been investigated. Impurity induced structural defects are believed to be responsible for the severe degradation.  相似文献   

14.
We have demonstrated the advantages of silicon interlayer passivation on germanium MOS devices, with CVD HfO/sub 2/ as the high-/spl kappa/ dielectric and PVD TaN as the gate electrode. A silicon interlayer between a germanium substrate and a high-/spl kappa/ dielectric, deposited using SiH/sub 4/ gas at 580/spl deg/C, significantly improved the electrical characteristics of germanium devices in terms of low D/sub it/ (7/spl times/10/sup 10//cm/sup 2/-eV), less C- V hysteresis and frequency dispersion. Low leakage current density of 5/spl times/10/sup -7/ A/cm/sup 2/ at 1 V bias with EOT of 12.4 /spl Aring/ was achieved. Post-metallization annealing caused continuing V/sub fb/ positive shift and J/sub g/ increase with increased annealing temperature, which was possibly attributed to Ge diffusion into the dielectric during annealing.  相似文献   

15.
The effects of high-pressure annealing on interface properties and charge trapping of nMOSFET with high-/spl kappa/ dielectric were investigated. Comparing with conventional forming gas (H/sub 2//Ar=4%/96%) annealed sample, nMOSFET sample annealed in high-pressure (5-20 atm), pure H/sub 2/ ambient at 400/spl deg/C shows 10%-15% improvements in linear drain current (I/sub d/) and maximum transconductance (g/sub m,max/). Interface trap density and charge trapping properties were characterized with charge pumping measurements and "single pulsed" I/sub d/-V/sub g/ measurements where reduced interface state density and improved charge trapping characteristics were observed after high pressure annealing. These results indicate that high pressure pure hydrogen annealing can be a crucial process for future high-/spl kappa/ gate dielectric applications.  相似文献   

16.
The authors have developed a distributed tunneling model to investigate the threshold-voltage instability induced by charge trapping in field-effect transistors (FETs) using high-/spl kappa/ gate dielectric materials. The charge trapping dynamics in the high-/spl kappa/ layer are modeled based on a rate equation, which is self-consistently incorporated into device-level simulations. The model is used to simulate pulsed operation of HfO/sub 2/ based n-type FETs; good agreement is obtained with pulsed measurements including the dependence of the threshold-voltage shift on pulse heights and durations. The trap-energy-level shift due to the polaron effect is found to be critical to model the pulse-height dependence of the threshold-voltage shift.  相似文献   

17.
In this letter, we present the use of atomic layer deposition (ALD) for high-/spl kappa/ gate dielectric formation in Ge MOS devices. Different Ge surface cleaning methods prior to high-/spl kappa/ ALD have been evaluated together with the effects on inserting a Ge oxynitride (GeO/sub x/N/sub y/) interlayer between the high-/spl kappa/ layer and the Ge substrate. By incorporating a thin GeO/sub x/N/sub y/ interlayer, we have demonstrated excellent MOS capacitors with very small capacitance-voltage hysteresis and low gate leakage. Physical characterization has also been done to further investigate the quality of the oxynitride interlayer.  相似文献   

18.
The instability of threshold voltage in high-/spl kappa//metal gate devices is studied with a focus on the separation of reversible charge trapping from other phenomena that may contribute to time dependence of the threshold voltage during a constant voltage stress. Data on the stress cycles of opposite polarity on both pMOS and nMOS transistor suggests that trapping/detrapping at the deep bandgap states contributes to threshold voltage instability in the pMOS devices. It is found that under the same electric field stress conditions, threshold voltage changes in pMOS and nMOS devices are nearly identical.  相似文献   

19.
Thermal instability of effective work function and its material dependence on metal/high-/spl kappa/ gate stacks is investigated. It is found that thermal instability of the effective work function of metal electrode on a gate dielectric is strongly dependent on the gate electrode and dielectric material. Thermal instability of a metal gate is related to the presence of silicon at the interface, and the Fermi-level pinning position is dependent on the location of silicon at the interface. The silicon-metal or metal-silicon bond formation by thermal anneal at the metal/dielectric interface induces the donor-like or acceptor-like interface states, causing a change of effective work function.  相似文献   

20.
Metal-insulator-metal (MIM) capacitors with (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ high-/spl kappa/ dielectric films were investigated for the first time. The results show that both the capacitance density and voltage/temperature coefficients of capacitance (VCC/TCC) values decrease with increasing Al/sub 2/O/sub 3/ mole fraction. It was demonstrated that the (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitor with an Al/sub 2/O/sub 3/ mole fraction of 0.14 is optimized. It provides a high capacitance density (3.5 fF//spl mu/m/sup 2/) and low VCC values (/spl sim/140 ppm/V/sup 2/) at the same time. In addition, small frequency dependence, low loss tangent, and low leakage current are obtained. Also, no electrical degradation was observed for (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitors after N/sub 2/ annealing at 400/spl deg/C. These results show that the (HfO/sub 2/)/sub 0.86/(Al/sub 2/O/sub 3/)/sub 0.14/ MIM capacitor is very suitable for capacitor applications within the thermal budget of the back end of line process.  相似文献   

设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号