基于FPGA的高精度图像采集系统设计

为了获取更高精度的图像，文章设计了一套基于FPGA结合高精度AD的CMOS图像探测器图像采集系统。首先通过串口配置图像探测器和AD的寄存器，使其按照成像要求进行工作，然后将高速串行差分图像输入Xilinx FPGA，综合运用差分转换、高速数据解串、数据时钟域转换等设计方法，使图像满足系统应用和存储与显示要求。实验表明，当AD的输出时钟高达240MHz时，系统能够准确、平稳的输出30MHz的14位高精度图像。     

基于ARM和FPGA的嵌入式CCD采集系统

提出了基于嵌入式技术CCD采集系统的新方法,并以ARM微处理器和FPGA芯片为核心设计了嵌入式CCD采集系统,解决了传统采集方法中系统过于庞大和复杂的问题,具有结构简单、小型化和智能化的特点.试验结果表明,该系统实现了CCD输出图像的高速采集和实时显示,数据采集速率达到5 MHz.     

基于Xilinx PCI LogiCore的高速红外图像采集及实时显示系统

介绍了一种红外图像的高速采集显示系统,实现对高帧频的红外图像的实时采集并显示.重点讨论了其关键模块PCI图像采集板卡的设计.其设计基于Xilinx PCI LogiCORE,可以达到现行PCI标准的最高速度:64 bit×66 MHz,并可以通过主控方式传输.实验结果表明此高速红外图像采集系统可以稳定地、可靠地长时间工作,适用于高帧频、高分辨率红外图像的实时采集显示.     

Laplacian图像边缘检测器的FPGA实现研究

介绍了Laplacian边缘检测算法模型,边缘检测工作流程,分布式运算原理,阐述了用FPGA实现的一个Lapla-cian图像边缘检测器的设计,包括系统总体设计,主要模块的设计思想和系统仿真结果.该检测器采用了流水式数据输入和高速分布式卷积运算等技术,具有良好的实时处理性能.若系统工作时钟为100 MHz,则处理一幅1024×1024的图像的时间仅需0.01 s左右.     

一种用于CMOS图像传感器的锁相环设计

设计了一种用于CMOS图像传感器时钟产生的电荷泵锁相环(CPPLL)电路.基于0.18μm CMOS工艺,系统采用常规鉴频鉴相器、电流型电荷泵、二阶无源阻抗型低通滤波器、差分环形压控振荡器以及真单相时钟结构分频器与CMOS图像传感器片内集成.系统电路结构简洁实用、功耗低,满足CMOS图像传感器对锁相环低功耗、低噪声、输出频率高及稳定的要求.在输入参考频率为5 MHz时,压控振荡器(VOC)输出频率范围为40～217 MHz,系统锁定频率为160MHz,锁定时间为16.6μs,功耗为2.5 mW,环路带宽为567 kHz,相位裕度为57°,相位噪声为一105 dBc/Hz@1 MHz.     

Laplacian图像边缘检测器的FPGA实现研究

介绍了Laplacian边缘检测算法模型,边缘检测工作流程,分布式运算原理,阐述了用FPGA实现的一个Lapla—cian图像边缘检测器的设计,包括系统总体设计,主要模块的设计思想和系统仿真结果。该检测器采用了流水式数据输入和高速分布式卷积运算等技术,具有良好的实时处理性能,若系统工作时钟为100MHz,则处理一幅1024-1024的图像的时间仅需0．01s左右。     

基于FPGA的图像光点中心坐标提取

设计了两轴转台的一部分,主要实现图像的采集、处理和光点中心坐标提取的功能。系统利用FPGA作为核心控制器,通过Verilog硬件描述语言设计出视频采集模块、PLL锁相环时钟管理模块、I2C总线模块、SDRAM存储模块和LCD显示驱动控制模块;光点中心坐标提取时,先对图像进行4邻域平均法滤波,然后求取光点图像块的中心位置作为光点的中心坐标,实现十字光标的跟踪;最后通过实验调试,验证了系统功能。     

基于FPGA的PLL动态配置设计与实现

介绍了Actel FPGA中PLL（Phase Locked Logic）的结构和相关特性,提出了一种基于Actel FPGA（Field Programmable Gate Array）的PLL动态配置的原理方案,并给出了一个具体的实现系统。本系统仅通过外部和ActelAPA600相连的少数控制线,就可以在输入66MHz的时钟条件下,对PLL进行6MHz～155MHz范围内准确、快速地变频（变频值必须是PLL能产生的合法时钟频率值）,在3炉内就可以得到想要的时钟频率。同时为了使输出的高速时钟稳定、可靠,还采用了LVDS（Low Voltage Differential Signaling）技术对时钟信号进行了处理。本设计系统具有接口简单、实时性强、稳定度高等特点,目前已成功应用到某电子学与信息处理系统中。     

叶端定时信号采集系统的设计

在非接触式高速旋转叶片自动实时监测系统中，要求25μm的振动位移测量分辨率为采集电路的设计增加了很大的难度。由于信号处理系统用固定频率脉冲填充法计数，实现定时时间的测量，因此采集系统的设计关键是：频率达100MHz的24bit高速计数器的设计，并利用D触发器使锁存脉冲与100MHz的计数时钟同步，从而解决由于计数脉冲与锁存脉冲不同步所造成的数据锁存失误问题。实验证实了该系统性能良好，达到预定精度要求。     

基于FPGA的Camera Link输出编码设计

为了Camera Link摄像机的小型化和集成化,设计并实现了基于FPGA的Camera Link接口的编码输出功能。输出编码分为3个步骤:首先,完成图像像素数据到Camera Link PORT的映射;其次,根据DS90CR287的数据编码要求对PORT数据和同步时钟信号进行编码;最后,通过FIFO和并串转换功能模块完成图像数据和时钟编码信号的LVDS信号输出。使用ModelSim软件,对像素时钟为40 MHz的BASE模式进行了仿真,同时在实物实验中,完成了像素时钟为40 MHz的FULL模式的实验,通过以上两方面实验验证了设计的Camera Link输出编码方案的正确性和可行性。提出的编码方案稳定可靠,可以应用于不同模式下的Camera Link编码输出,具有很高的灵活性和应用价值。     

Programmable 2D linear filter for video applications

A fully integrated 2-D linear filter including a line buffer for a 7×7 kernel is presented. To run the filter in real time at video clock frequencies, an array of pipelined carry-save adders was used as a very fast arithmetic unit. The filter chip contains 292451 transistors on a silicon area of 135 mm². The maximum clock frequency under worst-case conditions for technology and temperature was simulated to be 20 MHz. The main blocks are designed as independent parameterizable modules. The line buffer and the arithmetic unit are available as macros in a standard cell library for semicustom design. With these macros a semicustom chip for image enhancement in a X-ray system was produced. This chip works with a system frequency of 13 MHz. The line buffer module is used in another full-custom image processing chip-a two-dimensional rank order filter with a kernel size of also 7×7. This chip contains more than 300000 transistors on a silicon area of 103 mm². In this case the module containing the 1-D FIR (finite impulse response) filters is replaced by additional pixel delays and a sorter module. Simulations have shown that the chip could work with clock frequencies up to 20 MHz     

400MHz高速数据采集系统的设计与实现

介绍了一种用ECL逻辑和TTL逻辑器件构成的高速数据采集系统,采样频率为400MHz。系统实现简单,工作稳定。对系统进行的性能测试表明其有效位数为6位以上,满足实际应用的需要,适用于高速数字信号处理领域。     

A novel CMOS implementation of double-edge-triggered flip-flops

A CMOS implementation of a D-type double-edge-triggered flip-flop (DET-FF) is presented. A DET-FF changes its state at both the positive and the negative clock edge transitions. It has advantages with respect to both system speed and power dissipation. The design presented requires little overhead in circuit complexity. This CMOS D-type DET-FF is capable of operating at more than 50 MHz, which gives an equivalent system frequency of 100 MHz     

Integrated circuits for a real-time large-vocabulary continuousspeech recognition system

The architecture and implementation of a word processing subsystem for a real-time speech recognition system using hidden Markov models are described. The bottleneck of this system, which is the acquisition of data, is demonstrated, and an architecture that speeds up this bottleneck using on-chip dual-ported cache memories is presented. The architecture is described in a textual form, and the layout data were completely automatically generated. The chips have been fabricated through MOSIS using a 2-μm CMOS n-well technology. The functionality of the processors was successfully tested using the scan-path test methodology. The clock rate for the scan-path test was 5 MHz to guarantee proper operation of the circuits for this clock rate. All the processors were first time working silicon     

CMOS on-chip clock for digital signal processors

An on-chip clock for frequencies up to 190 MHz is presented. This clock generator can be used for application specific digital signal processors which are clocked faster than the off-chip system clock. It is useful for both processors with a few cycles per sample or for high frequency bit-serial processors which need a large number of cycles.<>     

热释电IRFPA图像采集系统设计

针对热释电红外焦平面阵列(IRFPA)的成像特点,基于虚拟仪器技术,利用Labview软件平台,采用PCI-6115采集卡构造了PC-DAQ热释电IRFPA图像采集系统。利用外部驱动电路产生的驱动信号作为采集系统的控制信号,控制采集的起止以及采集的时钟。采集同步信号作为判别信号,判断热释电IRFPA的亮、暗场以便差分处理。详细叙述了图像采集系统的构成,硬件、软件设计以及程序面板的操作。并对实验室研制的热释电ROIC输出信号及热释电IRFPA图像输出进行采集实验,得到了输出信号的波形显示及图像显示,验证了图像采集的可行性。     

A High Speed VLSI Architecture for Handwriting Recognition

This article presents PAPRICA-3, a VLSI-oriented architecture for real-time processing of images and its implementation on HACRE, a high-speed, cascadable, 32-processors VLSI slice. The architecture is based on an array of programmable processing elements with the instruction set tailored to image processing, mathematical morphology, and neural networks emulation. Dedicated hardware features allow simultaneous image acquisition, processing, neural network emulation, and a straightforward interface with a hosting PC.HACRE has been fabricated and successfully tested at a clock frequency of 50 MHz. A board hosting up to four chips and providing a 33 MHz PCI interface has been manufactured and used to build BEATR IX, a system for the recognition of handwritten check amounts, by integrating image processing and neural network algorithms (on the board) with context analysis techniques (on the hosting PC).     

An all-digital phase-locked loop for high-speed clock generation

An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-/spl mu/m one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 reference clock cycles. The power dissipation of the ADPLL is 100 mW (at 500 MHz) with a 3.3-V power supply. From chip measurement results, the P/sub k/-P/sub k/ jitter of the output clock is <70 ps, and the root-mean-square jitter of the output clock is <22 ps. A systematic way to design the ADPLL with the specified standard cell library is also presented. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for system-on-chip applications.     

High-speed CMOS circuit technique

It is shown that clock frequencies in excess of 200 MHz are feasible in a 3-μm CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz     

基于FPGA的空间太阳望远镜图像相关算法实现

两维图像相关跟踪是空间太阳望远镜1m光学系统达到0.1″分辨率关键之一.介绍了基于FPGA实现SST相关算法的方法,如2×2矢量基蝶形FFT、模块化结构、两级状态机、动态块浮点、并行流水时序等.20MHz下32×32图像相关算法在XCV800芯片上实现仅713 微秒,像元拟合精度优于1/50.