CMOS反相器高功率微波脉宽扰乱效应的建模和分析

本文对受脉宽影响的过剩载流子浓度分布及高功率微波(HPM)扰乱易发性进行解析建模,并利用仿真结果和实验数据对模型进行验证。利用机理分析与模型推导,得到过剩载流子主导闩锁效应中电流放大过程的结论。结果表明,P型衬底中的过剩载流子浓度分布确与HPM脉宽有关,HPM扰乱电压阈值Vp随着脉宽增宽而减小,同时这一变化存在一个拐点,这是由于P型衬底中的过剩载流子累积效应将随着时间推移而受到抑制。文中首次提出HPM脉宽扰乱效应的物理本质是过剩载流子的累积效应。实验验证认为,Vp解析模型能够对CMOS反相器的HPM扰乱易发性进行可靠和准确的预测,并同时考虑工艺、环境温度及版图参数等因素。从模型中可以得到,版图参数LB对脉宽扰乱效应有显著影响：LB较小的CMOS反相器更容易受到HPM的扰乱,这一结论将有助于提出反相器免于HPM扰乱的加固措施。     

SOI CMOS模拟集成电路发展概述

从SOI CMOS模拟集成电路(IC)中存在的关键问题——浮体效应——及其影响出发，介绍了在解决浮体效应以后，已实现的有代表性的模拟集成电路的发展状况。特别指出了SOI CMOS在实现RF电路及SOC芯片中的优点。     

一种CMOS低噪声有源下变频混频器

提出了一种采用电流源开关的低噪声开关跨导有源下变频混频器.使用正弦波本振大信号驱动可以避免因为脉冲本振谐波诱发的噪声叠加效应;利用LC谐振结构来缓解尾节点寄生电容充电和放电对电路高频工作时的限制.提出的混频器采用65 nm CMOS工艺实现,工作在5.2 GHz的RF频段下,最大转换增益为11.6 dB, 输入三阶交调...     

RFSOICMOS技术及其应用

介绍了RF SOI CMOS技术的特点。着重论述了RF SOI CMOS技术的低串扰特性、低损耗特性及其优质无源元件的性能。最后,阐述了RF SOI CMOS技术在RF系统片上集成方面的应用情况。     

电磁波对CMOS反相器扰乱作用的仿真分析

介绍了FDTD-PSPICE法进行场-路计算的基本方法和优势,利用该方法仿真计算了强电磁脉冲辐照对CMOS反相器逻辑电平的扰乱作用,发现强电磁脉冲可致使CMOS反相器的逻辑电平发生畸变或发生翻转,并比较了不同频率、不同强度电磁脉冲对CMOS电路的扰乱效果,结果表明,CMOS电路对特定频率的电磁波具有更高的敏感性。     

BSIM射频模型综述

CMOS集成电路技术的进一步发展和不断出现的新技术要求模型研究人员持续改进和增强VLSI电路设计和模拟的集约模型。美国Berkeley加州大学的BSIM团队对业界标准芯片仿真物理模型BSIM进行了不断的改进与开发。主要介绍BSIM系列模型在RF应用方面的改进。相对于BSIM3v3,BSIM4添加了更多真实器件效应,BSIM5和BSIM6是为了满足射频(RF)和高速CMOS电路模拟要求而发展的新一代物理基础的BSIM模型,具有对称、连续和参数少的特点。BSIM6可用于低压低功耗的RF和模拟设计。     

深亚微米CMOS反相器的单粒子瞬态效应研究

针对小尺寸CMOS反相器的单粒子瞬态效应,分别采用单粒子效应仿真和脉冲激光模拟试验两种方式进行研究。选取一种CMOS双反相器作为研究对象,确定器件的关键尺寸,并进行二维建模,完成器件的单粒子瞬态效应仿真,得到单粒子瞬态效应的阈值范围。同时,开展脉冲激光模拟单粒子瞬态效应试验,定位该器件单粒子瞬态效应的敏感区域,捕捉不同辐照能量下器件产生的单粒子瞬态脉冲,确定单粒子瞬态效应的阈值范围,并与仿真结果进行对比分析。     

RF采用CMOS工艺实现毫米波电路CMOS工艺带动频率和集成度提高

由于模拟和RF领域的论文提交数量急剧增加,RF从这一次开始作为独立的专业举行会议.在RF领域,CMOS电路技术的进展也很引人瞩目,适用于60GHz等毫米波波段的集成电路终于也可以利用CMOS工艺实现.     

深亚微米CMOS将成为RFIC的候选技术

依靠按比例缩小理论,CMOS现在已进入深亚微米至纳米时代,这不仅使CMOS数字集成电路达到Gb规模的集成度,而且由于器件工作频率的提高使CMOS技术有可能进入射频(RF)领域。 RF是radio frequency的缩写,现在RF已经替代微波而成为一个时髦的词。对RF的定义也在随着技术的发展而变化。过去,如果一个电子管制成的放大器的通频带超过600kHz,可以达到广播波段,就定义为射频放大器:而在今天,通频带达到2GHz的运算放大器被称     

RF集成电感的设计与寄生效应分析

分析了体硅 CMOS RF集成电路中电感的寄生效应 ,以及版图参数对电感品质因数 Q的影响 ,并通过Matlab程序模拟了在衬底电阻、金属条厚度、氧化层厚度改变时电感品质因数的变化 ,分析了不同应用频率时版图参数在寄生效应中所起的作用 ,得出了几条实用的设计原则并进行了实验验证 ,实验结果与模拟值符合得很好 ,表明此模拟方法与所得结论均可有效地用于指导射频 (RF)集成电路中集成电感的设计     

Improving the RF performance of 0.18 μm CMOS with deep n-wellimplantation

The radio-frequency (RF) figures of merit of 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology are investigated by evaluating the unity-current-gain cutoff frequency (F _t) and maximum oscillation frequency (F_max). The device fabricated with an added deep n-well structure is shown to greatly enhance both the cutoff frequency and the maximum oscillation frequency, with negligible DC disturbance. Specifically, an 18% increase in F_t and 25% increase in F_max are achieved. Since the deep n-well implant can be easily adopted in a standard CMOS process, the approach appears to be very promising for future CMOS RF applications     

A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends

As CMOS technology scales down, digital supply voltage and digital power consumption goes down. However, the supply voltage and power consumption of the RF front-end and analog sections do not scale in a similar fashion. In fact, in many state-of-the-art communication transceivers, RF and analog sections can consume more energy compared to the digital part. In this paper, first, a system level energy model for all the components in the RF and analog front-end is presented. Next, the RF and analog front-end energy consumption and communication quality of three representative systems are analyzed: a single user point-to-point wireless data communication system, a multi-user code division multiple access (CDMA)-based system and a receive-only video distribution system. For the single user system, the effect of occupied signal bandwidth, peak-to-average ratio (PAR), symbol rate, constellation size, and pulse-shaping filter roll-off factor is analyzed; for the CDMA-based multi-user system, the effect of the number of users in the cell and multiple access interference (MAI) along with the PAR and filter roll-off factor is studied; for the receive-only system, the effect of 1/f noise for direct-conversion receiver and the effect of IF frequency for low-IF architecture on the RF front-end power consumption is analyzed. For a given communication quality specification, it is shown that the energy consumption of a wireless communication front-end can be scaled down by adjusting parameters such as the pulse shaping filter roll-off factor, constellation size, symbol rate, number of users in the cell, and signal center frequency     

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

A fully integrated 5-GHz low-power ESD-protected low-noise amplifier (LNA), designed and fabricated in a 90-nm RF CMOS technology, is presented. This 9.7-mW LNA features a 13.3-dB power gain at 5.5 GHz with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB. An on-chip inductor, added as "plug-and-play," i.e., without altering the original LNA design, is used as ESD protection for the RF pins to achieve sufficient ESD protection. The LNA has an ESD protection level up to 1.4 A transmission line pulse (TLP) current, corresponding to 2-kV Human Body Model (HBM) stress. Experimental results show that only minor RF performance degradation is observed by adding the inductor as a bi-directional ESD protection device to the reference LNA.     

Impact of technology scaling and process variations on RF CMOS devices

Inspired by the huge improvement in the RF properties of CMOS devices, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static effects is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Moreover, the RF frequency performance of CMOS is investigated under the influence of process variations for different CMOS generations. Using the BSIM4 model, it is found that future CMOS technologies have high prospects in the RF industry and will continue challenging other technologies in the RF domain to be the dominant technology for RF transceivers and system-on-chip implementations.     

射频接收机中低抖动双模分频器

对射频接收机中双模分频器的设计和应用进行了研究.提出了一种改进型D-latch以提高双模分频器速度与驱动能力,一种将D-latch与"或"逻辑门集成的结构以降低电路的复杂度.采用TSMC 0.18μm CMOS混合信号工艺实现了用于地面数字电视接收机的除16/17双模分频器.采用0.18μm CMOS标准单元库设计并以与双模分频器同样的工艺实现了可编程吞吐式脉冲分频器.测试结果显示双模分频器的输出抖动小于0.03%,而且能够与可编程吞吐式脉冲分频器良好地配合工作.     

0.15-μm RF CMOS technology compatible with logic CMOS forlow-voltage operation

Radio Frequency (RF) CMOS is expected to replace bipolar and GaAs MESFETs in RF front-end ICs for mobile telecommunications devices in the near future. In order for the RF CMOS to be popularly used in this application, compatibility of its process for high-speed logic CMOS and low supply voltage operation are important for low fabrication cost and low power consumption. In this paper, a 0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation is described. Because the fabrication process is the same as the high-speed logic CMOS, manufacturability of this technology is excellent. Some of the passive elements can be integrated without changing the process and others can be integrated with the addition of a few optional processes. Mixed RF and logic CMOS devices in a one-chip LSI can be realized with relatively low cost. Excellent high-frequency characteristics of small geometry silicon MOSFETs with low-power supply voltage are demonstrated. Cutoff frequency of 42 GHz of n-MOSFETs, which is almost the same level at that of general high-performance silicon bipolar transistors, was obtained. N-MOSFET's maintained enough high cutoff frequency of 32 GHz even at extremely low supply voltage of 0.5 V. Moreover, it was confirmed that degradation of minimum noise figure for deep submicron MOSFETs with 0.5 V operation is sufficiently small compared with 2.0 V operation. These excellent high-frequency characteristics of small geometry silicon MOSFETs under low-voltage operation are suitable for mobile telecommunications applications     

An Agile, Ultra-Wideband Pulse Radio Transceiver With Discrete-Time Wideband-IF

A pulse-based CMOS ultra-wideband transmitter and receiver have been realized using a standard digital 90 nm CMOS process. The transceiver uses digital templates stored in high-speed memories for pulse generation on the transmit side and for correlation on the receive side. This allows fast band switching for multi-band operation and interferer avoidance without the requirement for fast-settling phase-locked loops. The receiver contains a 3.1–9.5 GHz broadband front-end and discrete-time intermediate frequency correlators that achieve a pulse rate of 100 Mpulses/s and has a die area of 1 ${hbox{mm}}^{2}$ while consuming 130 mA from a 1.2 V supply. The transmitter uses interleaved, intermediate frequency digital-to-analog converters followed by partial-order hold reconstruction filters that eliminate sampling images, and a quadrature RF up-converter. 1.25 nJ is spent per transmitted pulse for a pulse-repetition rate of 100 MHz while achieving a broadband image cancellation of 42 dB.      

应用于频率合成器的宽分频比CMOS可编程分频器设计

提出一种应用于射频频率合成器的宽分频比可编程分频器设计。该分频器采用脉冲吞吐结构,可编程计数器和吞脉冲计数器都采用改进的CMOS源极耦合（SCL）逻辑结构的模拟电路实现,相对于采用数字电路实现降低了电路的噪声和减少了版图面积。同时,对可编程分频器中的检测和置数逻辑做了改进,提高分频器的工作频率及稳定性。最后,采用TSMC的0.13μm CMOS工艺,利用Cadence Spectre工具进行仿真,在4.5 GHz频率下,该分频器可实现200515的分频比,整个功耗不超过19 mW,版图面积为106μm×187μm。