Experimental analysis of transmission line parameters in high-speedGaAs digital circuit interconnects

Transmission line properties of typical high-speed interconnects were experimentally investigated by fabricating and characterizing coplanar strips on semi-insulating GaAs substrates. The strips have thicknesses of about 2500 Å or 5000 Å and widths of 4, 6, or 8 μm so as to be representative of on-chip interconnects in high-speed GaAs digital circuits. Measurements are carried out up to 18 GHz, and the pertinent line parameters, such as resistance, capacitance per unit length, and characteristic impedance, are extracted using the measured S-parameters. The measurement results confirm the quasi-TEM properties of such interconnects. In all cases, the measured distributed capacitance and inductance are sensitive to frequency whereas the resistance is found to increase as much as 38% for the widest and thickest conductors     

Enhanced transmission characteristics of on-chip interconnects withorthogonal gridded shield

On-chip interconnects over an orthogonal grid of grounded shielding lines on the silicon substrate are characterized by full-wave electromagnetic simulation. The analysis is based on a unit cell of the periodic shielded interconnect structure. It is demonstrated that the shielding structure may help to significantly enhance the transmission characteristics of on-chip interconnects particularly in analog and mixed-signal integrated circuits with bulk substrate resistivity on the order of 10 Ω-cm. Simulation results for the extracted R, L, G, C transmission line parameters show a significant decrease in the frequency-dependence of the distributed shunt capacitance as well as decrease in shunt conductance with the shielding structure present, while the series inductance and series resistance parameters are nearly unaffected. An extension of the equivalent circuit model for the shunt admittance of unshielded on-chip interconnects to include the effects of shielding is also presented     

Analysis and optimization of shielded RLC global interconnects for gigascale integration

Compact physical models are presented for on-chip double-sided shielded transmission lines, which are mainly used for long global interconnects where inductance effects should not be ignored. The models are then used to optimize the width and spacing of long global interconnects with repeater insertion. The impacts of increasing line width and spacing on various performance parameters such as delay, data-flux density, power dissipation and total repeater area are analysed. The product of data-flux density and reciprocal delay per unit length are defined as a figure of merit (FOM). By maximizing the FOM, the optimal width and spacing of shielded RLC global interconnects are obtained for various international technology roadmap for semiconductors (ITRS) technology nodes.     

Some measurement results for frequency-dependent inductance of ICinterconnects on a lossy silicon substrate

Frequency dependent measurements of scattering (S) parameters using a vector network analyzer (VNA) have been performed on IC interconnects on a lossy silicon substrate. The multiline calibration method has been used to perform the de-embedding of the line parameters, from which the line inductance is extracted. A highly accurate closed-form approximation for frequency-dependent impedance per unit length of a lossy silicon substrate for IC interconnects has been used to compare with the measurements performed     

DSM interconnects: importance of inductance effects and corresponding range of length

To analyze at which rise/fall times the inductance effect appears in DSM interconnects, the author develops a methodology versus the input line transition time to be technology-independent. These lines are modeled as RC and RLC distributed lines, and the two models are compared to define the effects caused by neglecting inductance. The goal of this study is, based upon the discrepancy between RC and RLC models, to define when inductance must be included in the modeling of interconnects. A simple rule permits the choice of the simplest model (RC or RLC) for a given accuracy. The length range concerned by the inductive effect is calculated from the complex propagation factor value. The theoretical limits are illustrated on several interconnection configurations, on a 0.18-/spl mu/m technology.     

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.     

激光微熔覆法制备空芯薄膜电感的研究

采用激光微熔覆方法制备了空芯薄膜电感,着重研究了激光功率密度对电感线宽影响,以及薄膜电感的结构参数变化对电感电性能影响。结果表明,线宽随激光功率密度增大而增大;电感量随着圈数增多、中心线间距增大、线宽变大而增大。通过优化激光工艺和结构参数,制备了面积5 mm×5 mm和9 mm×9 mm,线宽100 μm和120 μm,线中心间距250 μm和500 μm,圈数8和16,厚度1 μm的空芯回字型电感,在测试频率100 kHz～1 MHz条件下,电感量为240 nH±3 nH～1.2 μH±3 nH,单位面积电感量可达14.81 nH/mm2。通过实验证明,采用激光微熔覆法制备的微电感,在同样形状和面积下,可提高电感量。     

Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method

A new inductance extraction method is defined to accelerate modeling of massively coupled resistance–inductance–capacitance (RLC) interconnects. The new relative inductance generates a sparse inductance matrix. Therefore, it enables modeling of large circuits with reasonable speed and accuracy. It maintains accuracy for a wide frequency range, even for the cases that there are far inductance couplings. It is demonstrated that the relative inductance matrix is equivalent to the conventional partial inductance matrix. Simulations done for a 16-bit bus with each bus line divided into 32 segments show that the simulations using the relative inductance method is 20 times faster and requires 9.5 times less memory compared to the established partial inductance method.      

互连线串扰耦合噪声的ABCD矩阵模型

高频互连线间的相互耦合和相互感应是产生串扰的一个重要因素。已有文献利用二端口网络ABCD矩阵从理论上求出了耦合互连线阶跃响应,但该方法对互感描述不准确,导致计算复杂,且对串扰耦合噪声的估计不够准确。该文根据互感的基本定义,修改了原模型中互感的表示方法,提出了一个新的ABCD矩阵级联模型,对LTCC工艺互连线的串扰耦合噪声进行分析,并将得到的ABCD模型分析结果与ADS软件的仿真结果对比,验证了改进的ABCD模型的准确性。     

Highly Accurate Quasi-Static Modeling of Coupled Interconnects in CMOS Technology

A new analytic model is presented (the model is based on the induced current density distribution inside silicon substrate) to calculate frequency dependent mutual inductance and resistance per unit length of coupled on-chip interconnects in CMOS technology. The validity of the proposed model has been checked by a comparison with a quasi-TEM spectral domain numerical simulation and equivalent-circuit modeling procedure. It is found that the silicon semiconducting substrate skin effect must be considered for the accurate prediction of the high-frequency characteristics of VLSI interconnects.     

Permalloy loaded transmission lines for high-speed interconnect applications

The mutual inductance and self-inductance of global interconnects are important but difficult to extract and model in deep submicrometer very large scale integration (VLSI) designs. The absence of effective mutual magnetic field shielding limits the maximum unbuffered interconnect line length. In this paper, we propose and demonstrate that permalloy-loaded transmission lines can be used for high-speed interconnect applications to overcome these limitations. Permalloy films were incorporated into planar transmission lines using a CMOS-compatible process. The line characteristics show that eddy-current effects are the limiting factors for the high-frequency permalloy applications when ferromagnetic resonance are restrained through geometry design. Patterning permalloy films effectively extends their application to above 20 GHz. The line characteristic impedances are about /spl sim/90 /spl Omega/. Under 50 mA dc current biases, the line parameters did not change much. Moreover, the patterned permalloy reduces the magnetic field coupling between two adjacent transmission lines by about 10 dB in our design. The demonstrated operation frequency range, current carrying capability and magnetic field shielding properties indicate that the permalloy loaded lines are suitable for high-speed interconnect applications in CMOS technologies.     

An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects

This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS [1], interconnects become extremely resistive and, while inductance effects diminish with scaling but the performance, specifically, delay per unit length, degrades with scaling. The effect of the proposed global interconnect scaling scheme on optimized driver size, interconnect length, delay per unit length and total buffer area is quantified and compared with the unscaled and the ITRS cases. It is shown that the proposed scaling scheme improves the delay per unit length without degrading inductive effects or increasing buffer area with scaling.     

An experimental procedure for characterizing interconnects to theDC power bus on a multilayer printed circuit board

The effectiveness of DC power bus decoupling is impacted by the inductance associated with interconnect vias in printed circuit boards (PCBs). Adequate characterization of these interconnects is necessary to facilitate modeling and simulation, and to assess the effectiveness of added decoupling. A measurement procedure is presented for determining the series inductance and resistance of an interconnect with a network analyzer. The validity and limitations of the procedure are discussed. Experimental results of interconnect parameters on an 8×10 in ten-layer test-board corroborate those measured with a precision impedance analyzer. The measured interconnect values are used to simulate several cases of power-bus decoupling which show good agreement with two-port swept frequency measurements     

Influence of the ground line position on the signal integrity of product-related interconnects in the frequency and time domain

The impact of the ground line position on the line parameters of signal interconnects built in a 110-nm CMOS technology is investigated in the presence of a conductive substrate. Characteristic line parameters obtained from simulations are validated with two-port network analyzer measurements of specially designed test structures in a frequency range up to 50 GHz. In addition, the influence of the ground line position on time-domain signals in product-related bus systems is explored. It is shown that the impact of substrate effects on the line parameters, and consequently on the signal shape in the time domain, strongly depends on the relative position of the ground line with respect to the signal lines and, as expected, on the length of the line system. The authors show that for short on-chip bus systems (shorter than 2 mm), the influence of the ground line positioning on time-domain signals is negligible. However, for long bus systems (e.g., 5 mm), this influence becomes significant and can no longer be neglected.     

An efficient crosstalk parameter extraction method for high-speedinterconnection lines

A proposal is presented for an effective extraction method for crosstalk model parameters of high-speed interconnection lines. In the extraction procedure, mutual capacitance and mutual inductance of the coupled interconnection lines are extracted based on S-parameter measurement, time-domain-reflectometry (TDR) measurement and subsequent microwave network analysis. The extraction method is useful for characterizing homogeneous guiding structures, where the propagation of coupled transverse electromagnetic (TEM) modes is supported. In contrast to previous extraction methods, the suggested procedure requires fewer on-wafer probing steps and does not need matched terminations in the test device for high-frequency probing. The extracted models can be readily used with simulation program with integrated circuit emphasis (SPICE) circuit simulation. The procedure can also be used for modeling the crosstalk in packaging structures and multichip modules (MCMs). The proposed procedure has been successfully applied to the crosstalk model extraction of on-chip interconnection lines. Crosstalk model parameters were obtained for different line structures, spaces, and widths. Finally, the validity and reliability of the extracted models were examined by comparing a SPICE circuit simulation using the extracted crosstalk model parameters with high-speed time-domain crosstalk measurement. A close agreement was observed in the amplitude and pulse shape between the simulation and the measurement, showing the accuracy and usefulness of the proposed extraction method     

芯片内互连线电阻和电感频变分布参数提取

本文使用导体截面矩量法提取芯片内互连线电阻和电感频变分布参数。根据芯片内多接地导体的情况重新推导了公式 ,实现了对算法的改进。研究了硅衬底导电率变化对金属绝缘半导体传输线的分布电阻和分布电感参数的影响。通过两个例子的计算 ,证明算法可应用于芯片内互连线参数提取。     

Microwave frequency interconnection line model of a wafer level package

In this paper, we introduce the microwave transmission characteristics of interconnection lines on a wafer level package (WLP) and also propose a precise microwave-frequency model of the WLP interconnections. The slow wave factor (SWF) and attenuation constant are measured and discussed. High-frequency measurement is described, based on two-port S-parameter measurements, using an on-wafer microwave probe with a frequency range of up to 5 GHz. The extracted model is represented in the form of distributed lumped circuit model elements and can be easily merged into SPICE simulations. From the extracted model, it was found that line capacitance and inductance per unit length are 0.110 pF/mm and 0.286 nH/mm, respectively. We have successfully applied the extracted model to the design and analysis of a Rambus memory module for time domain simulation and signal integrity simulation. From the simulation, it was found that the WLP has better high-frequency performance, because of its low package inductance, compared with the /spl mu/BGA package, but longer propagation delay, because of the relatively high package capacitance.     

多导体传输线的邻近效应和分布参数研究

随着多导体传输线内各导体之间间距的减小, 导体之间的近邻效应对传输线的分布参数和传输特性的影响越来越大.为此, 我们针对三种典型的传输线结构, 分别建立了基于矢势有限元方法分析的多导体传输线的模型, 并分析了近邻效应对磁通密度和分布电感的影响.利用提出的方法计算了同轴传输线的单位长度分布电感, 并将它与采用解析方法得到的结果进行比较来证明该方法的正确性.计算双线传输线在不同间距时的单位长度电感, 与理论分析得到的结果相比较验证了导线间距越小, 近邻效应对单位长度电感的影响越大.最后, 计算考虑了近邻效应的耦合微带线的电感矩阵, 并将它与其他不考虑近邻效应的方法得到的结果相比较, 说明近邻效应对传输线电感矩阵的影响.     

An improved two-frequency method of capacitance measurement forSrTiO3 as high-k gate dielectric

An improved two-frequency method of capacitance measurement for the high-k gate dielectrics is proposed. The equivalent circuit model of the MOS capacitor including the four parameters of intrinsic capacitance, loss tangent, parasitic series inductance, and series resistance is developed. These parameters can be extracted by independently measuring the capacitor at two different frequencies. This technique is demonstrated for high-k SrTiO₃ gate dielectrics and the results show that the calibrated capacitances are invariant over a wide range of frequency. In addition, the extracted loss tangent, inductance and resistance are independent on gate voltage and frequency. The effect of series resistance on the frequency dispersion of the capacitance can be also explained by this model. These results indicate that this modified technique can be incorporated in the routine capacitance-voltage (C-V) measurement procedure providing the physically meaningful data for the high-k gate dielectrics     

Interconnect characterization of X architecture diagonal lines for VLSI design

This paper addresses the manufacturability, yield, and reliability aspects of X Architecture interconnects (diagonal lines) in a very large scale integrated (VLSI) design that enables integrated circuit (IC) chips to become faster and smaller (area) compared to the same design in Manhattan routing. Test chips that consist of comb/serpentine, maze, via chain, as well as resistance and capacitance structures are designed and fabricated using both 130- and 90-nm copper processes. A new technique to characterize interconnect physical parameters (top and bottom line widths, metal line, and dielectric thickness) is developed that requires capacitance measurement on sets of special test structures. An excellent agreement is found between the extracted process parameters, for both diagonal and Manhattan lines, using this technique and those of SEM/FIB data. Measurements of the line resistance, capacitance, and SEM/FIB data on different types of test structures show that 1:1 design rule ratio (Manhattan versus X Architecture) is manufacturable, and the uniformity and fidelity of the diagonal lines are as good as Manhattan lines. The current generation of mask, lithography, wafer processing techniques are applicable to X Architecture designs.