Controlled Doping of Wafer‐Scale PtSe2 Films for Device Application

Semiconductive transition metal dichalcogenides (TMDs) have been considered as next generation semiconductors, but to date most device investigations are still based on microscale exfoliation with a low yield. Wafer scale growth of TMDs has been reported but effective doping approaches remain challenging due to their atomically thick nature. This work reports the synthesis of wafer‐scale continuous few‐layer PtSe₂ films with effective doping in a controllable manner. Chemical component analyses confirm that both n‐doping and p‐doping can be effectively modulated through a controlled selenization process. The electrical properties of PtSe₂ films have been systematically studied by fabricating top‐gated field effect transistors (FETs). The device current on/off ratio is optimized in two‐layer PtSe₂ FETs, and four‐terminal configuration displays a reasonably high effective field effect mobility (14 and 15 cm² V^?1 s^?1 for p‐type and n‐type FETs, respectively) with a nearly symmetric p‐type and n‐type performance. Temperature dependent measurement reveals that the variable range hopping is dominant at low temperatures. To further establish feasible application based on controllable doping of PtSe₂, a logic inverter and vertically stacked p–n junction arrays are demonstrated. These results validate that PtSe₂ is a promising candidate among the family of TMDs for future functional electronic applications.     

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.     

Field‐Induced n‐Doping of Black Phosphorus for CMOS Compatible 2D Logic Electronics with High Electron Mobility

Black phosphorus (BP) has been considered as a promising two‐dimensional (2D) semiconductor beyond graphene owning to its tunable direct bandgap and high carrier mobility. However, the hole‐transport‐dominated characteristic limits the application of BP in versatile electronics. Here, we report a stable and complementary metal oxide semiconductor (COMS) compatible electron doping method for BP, which is realized with the strong field‐induced effect from the K⁺ center of the silicon nitride (Si_xN_y). An obvious change from pristine p‐type BP to n type is observed after the deposit of the Si_xN_y on the BP surface. This electron doping can be kept stable for over 1 month and capable of improving the electron mobility of BP towards as high as ~176 cm² V^–1 s^–1. Moreover, high‐performance in‐plane BP p‐n diode and further logic inverter were realized by utilizing the n‐doping approach. The BP p‐n diode exhibits a high rectifying ratio of ~10⁴. And, a successful transfer of the output voltage from “High” to “Low” with very few voltage loss at various working frequencies were also demonstrated with the constructed BP inverter. Our findings paves the way for the success of COMS compatible technique for BP‐based nanoelectronics.     

Organic N‐Type Molecule: Managing the Electronic States of Bulk Perovskite for High‐Performance Photovoltaics

The power conversion efficiency (PCE) of planar p–i–n perovskite solar cells (pero‐SCs) is commonly lower than that of the n–i–p pero‐SCs, due to the severe nonradiative recombination stemming from the more p‐type perovskite with prevailing electron traps. Here, two n‐type organic molecules, DMBI‐2‐Th and DMBI‐2‐Th‐I, with hydrogen‐transfer properties for the doping of bulk perovskite aimed at regulating its electronic states are synthesized. The generated radicals in these n‐type dopants with high‐lying singly occupied molecular orbitals enable easy transfer of the thermally activated electrons to the MAPbI₃ perovskite for the realization of n‐doped perovskites. The n‐doping degree could be further enhanced by using the iodine ionized dopant DMBI‐2‐Th‐I. The doping effect could reduce the electron trap density, increase the electron concentration of the bulk perovskite, and simultaneously improve the surface electronic contact. When the DMBI‐2‐Th‐I‐doped perovskite is used in planar p–i–n pero‐SCs, the nonradiative recombination is significantly suppressed. As a result, the photovoltaic performance improved significantly, as evidenced by an excellent PCE of 20.90% and a robust ambient stability even under high relative humidity. To the best of the knowledge, this work represents the first example where organic n‐type dopants are used to tune the electronic states of a bulk perovskite film for efficient planar p–i–n pero‐SCs.     

Transistor-transistor logic with high packing density and optimum performance at high inverse gain

The advantages of using thin epitaxial layers for bipolar integrated circuits are discussed in this paper. Using epitaxial layer thicknesses of ~ 1 /spl mu/ and a low-voltage form of transistor-transistor logic, packing densities of 10/SUP 5/ logic gates/in/SUP 2/ have been achieved. The power x delay product of the circuits was 5 pJ. The transistors were formed in 1 /spl mu/ thick epitaxial layers and have inverse common-emitter current gains of 2 to 3. These high inverse gains make practical some new circuit configurations, including a dual-emitter inverter with reduced storage time. The thin epitaxial layer may be p type, rather than the usual n type, and this makes possible a new isolation scheme that allows the fabrication of bipolar integrated circuits using only five photolithographic steps.     

The effect of logic cell configuration, gatelength, and fan-out on the propagation delays of GaAs MESFET logic gates

In this work, three different logic cell configurations, two with and one without a source-follower are employed: These logic cells are arranged in 5- and 11-stage ring oscillator (RO) circuits. The circuits are then fabricated with nominal gatelengths of 0.5, 1.0, 1.5, and 2.0 µm and fan-out loadings of 1, 2, 4, and 8 (consisting of source-gate capacitances). All these test circuits are incorporated into a 6-mm by 6-mm master field. Sufficiently large slices to result in a 4 × 4 array of the master field are used. Si⁺implantation intolangle100rangleCr-doped Bridgman and not intentionally doped liquid encapsulated Czochralski (LEC) substrates have been used with success in terms of reproducibility, long range uniformity, and mobility. Since circuit yields are high, each slice provides a sufficiently large data base for a meaningful statistical analysis to be carried out for each circuit type. These data (propagation delay versus circuit type) together with power dissipation results are presented. Preliminary modeling results of the experimental data are also presented.     

An optimal NOR logic element using nonlinear resistance

The design procedures for a NOR logic element using a nonlinear collector resistor are described. The nonlinear collector resistor is used as a means for reducing dissipation over a linear resistor with the same fan-out capability. The nonlinear resistor is combined with a standard transistor-resistor logic gate to reduce the effects of two of the undesirable characteristics of this type of logic, namely, high dissipation and slow transient response. In the analysis an expression for fan-out is developed to determine base network resistances. Typical design examples are described with calculations made for MOS-type current limiters. Circuits were constructed and tested to verify these calculations.     

MoS2 Van der Waals p–n Junctions Enabling Highly Selective Room‐Temperature NO2 Sensor

Van der Waals p–n junctions of 2D materials present great potential for electronic devices due to the fascinating properties at the junction interface. In this work, an efficient gas sensor based on planar 2D van der Waals junctions is reported by stacking n‐type and p‐type atomically thin MoS₂ films, which are synthesized by chemical vapor deposition (CVD) and soft‐chemistry route, respectively. The electrical conductivity of the van der Waals p–n junctions is found to be strongly affected by the exposure to NO₂ at room temperature (RT). The MoS₂ p–n junction sensor exhibits an outstanding sensitivity and selectivity to NO₂ at RT, which are unavailable in sensors based on individual n‐type or p‐type MoS₂. The sensitivity of 20 ppm NO₂ is improved by 60 times compared to a p‐type MoS₂ sensor, and an extremely low limit of detection of 8 ppb is obtained under ultraviolet irradiation. Complete and very fast sensor recovery is achieved within 30 s. These results are superior to most of the previous reports related to NO₂ detection. This work establishes an entirely new sensing platform and proves the feasibility of using such materials for the high‐performance detection of gaseous molecules at RT.     

p–n‐Junction‐Based Flexible Dye‐Sensitized Solar Cells

In this paper, a new type of flexible working electrode, TiO₂/CuI/Cu, is reported, in which the p–n junction of TiO₂–CuI is introduced into dye‐sensitized solar cells (DSSCs) for the first time. The devices give a high conversion efficiency of up to 4.73% under 1 sun illumination. The excellent performance is ascribed to the existence of the p–n junction, which forms a single directional pathway for electron transport which benefits the charge separation, and improves the efficiency of the flexible solar cells as a result.     

Pipelined GaAs carry lookahead adder

Based on the recently introduced GaAs pseudo-dynamic latched logic, the authors present a new type of carry lookahead adder (CLA) which combines the benefits of 0.6 μm E/D MESFET technology with the above mentioned class of logic. Consideration is given to power dissipation, taking into account that for high levels of integration, techniques to reduce the power budget are essential. As a result. The design of a four bit pipelined GaAs CLA operating at 800 MHz and exhibiting less than 1.8 mW of power dissipation is presented     

Reducing the power consumption of two-dimensional logic transistors

The growing demand for high-performance logic transistors has driven the exponential rise in chip integration,while the transistors have been rapidly scaling down to sub-10 nm.The increasing leakage current and subthreshold slope(SS) induced by short channel effect(SCE) result in extra heat dissipation during device operation.The performance of electronic devices based on two-dimensional(2D) semiconductors such as the transition metal dichalcogenides(TMDC) can significantly reduce power consumption,benefiting from atomically thin thickness.Here,we discuss the progress of dielectric integration of 2D metal–oxide–semiconductor field effect transistors(MOSFETs) and 2D negative capacitance field effect transistors(NCFETs),outlining their potential in low-power applications as a technological option beyond scaled logic switches.Above all,we show our perspective at 2D low-power logic transistors,including the ultra-thin equivalent oxide thickness(EOT),reducing density of interface trap,reliability,operation speed etc.of 2D MOSFETs and NCFETs.     

低功耗双边沿触发器的逻辑设计

本文从消除时钟信号冗余跳变而致的无效功耗的要求出发,提出双边沿触发器的设计思想与基于与非门的逻辑设计．用ＰＳＰＩＣＥ程序模拟证实了该种触发器具有正确的逻辑功能,能够正常地应用于时序电路的设计,并且由于时钟工作频率减半而导致系统功耗的明显降低．     

Polymer Light‐Emitting Electrochemical Cells: Doping Concentration,Emission‐Zone Position,and Turn‐On Time

Direct optical probing of the doping progression and simultaneous recording of the current–time behavior allows the establishment of the position of the light‐emitting p–n junction, the doping concentrations in the p‐ and n‐type regions, and the turn‐on time for a number of planar light‐emitting electrochemical cells (LECs) with a 1 mm interelectrode gap. The position of the p–n junction in such LECs with Au electrodes contacting an active material mixture of poly(2‐methoxy‐5‐(2′‐ethylhexyloxy)‐p‐phenylene vinylene) (MEH‐PPV), poly(ethylene oxide), and a XCF₃SO₃ salt (X = Li, K, Rb) is dependent on the salt selection: for X = Li the p–n junction is positioned very close to the negative electrode, while for X = K, Rb it is significantly more centered in the interelectrode gap. Its is demonstrated that this results from that the p‐type doping concentration is independent of salt selection at ca. 2 × 10²⁰ cm^–3 (ca. 0.1 dopants/MEH‐PPV repeat unit), while the n‐type doping concentration exhibits a strong dependence: for X = K it is ca. 5 × 10²⁰ cm^–3 (ca. 0.2 dopants/repeat unit), for X = Rb it is ca. 9 × 10²⁰ cm^–3 (ca. 0.4 dopants/repeat unit), and for X = Li it is ca. 3 × 10²¹ cm^–3 (ca. 1 dopants/repeat unit). Finally, it is shown that X = K, Rb devices exhibit significantly faster turn‐on times than X = Li devices, which is a consequence of a higher ionic conductivity in the former devices.     

An ECL-compatible GaAs MESFET 1-kbit static RAM

A fully ECL-compatible GaAs enhancement/depletion (E/D)-MESFET 1-kb static RAM was designed, fabricated, and tested. Direct-coupled FET logic is used for the memory array while buffered FET logic is utilized in the peripheral circuitry to provide an ECL 100 K interface. The memory cell area is 774 /spl mu/m/SUP 2/, and the chip size is 2.0/spl times/1.75 mm/SUP 2/. Fabrication of the 1-kb RAM involves a fully implanted two-threshold process with true double-level metal interconnection. A minimum access time of 1.3 ns has been obtained with a total power dissipation of 1.4 W (memory array power dissipation is only ~40 mW). The output voltage swing across a 50-/spl Omega/ load is 750 mV.     

Demonstration of sub-5 ps CML ring oscillator gate delay withreduced parasitic AlInAs/InGaAs HBT

We have demonstrated a gate delay of 4.9 ps and a power dissipation of 8 mW per CML inverter in an AlInAs-InGaAs HBT technology with 150 mV logic swing. The demonstration circuit was a 15-stage ring oscillator based on CML inverters with a fan-out of 1 and a nominal 3.1 V supply. The same circuit was measured to have a gate delay of 4.7 ps and a power dissipation of 13 mW per inverter using a 3.6 V supply, and a gate delay of 6.2 ps and a power dissipation of 2.4 mW per inverter with a 2.2 V supply. These are the fastest results for a bipolar transistor based logic family in any semiconductor and comparable to the fastest results for any logic family in any semiconductor. Because two gate delays are required for the simplest useful sequential logic circuits such as clocked flip-flops, this is a significant milestone in that it is the first, though somewhat idealized, demonstration that logic at 100 GHz is realizable in InP-based HBT     

Highly Efficient p‐i‐n and Tandem Organic Light‐Emitting Devices Using an Air‐Stable and Low‐Temperature‐Evaporable Metal Azide as an n‐Dopant

Cesium azide (CsN₃) is employed as a novel n‐dopant because of its air stability and low deposition temperature. CsN₃ is easily co‐deposited with the electron transporting materials in an organic molecular beam deposition chamber so that it works well as an n‐dopant in the electron transport layer because its evaporation temperature is similar to that of common organic materials. The driving voltage of the p‐i‐n device with the CsN₃‐doped n‐type layer and a MoO₃‐doped p‐type layer is greatly reduced, and this device exhibits a very high power efficiency (57 lm W^?1). Additionally, an n‐doping mechanism study reveals that CsN₃ was decomposed into Cs and N₂ during the evaporation. The charge injection mechanism was investigated using transient electroluminescence and capacitance–voltage measurements. A very highly efficient tandem organic light‐emitting diodes (OLED; 84 cd A^?1) is also created using an n–p junction that is composed of the CsN₃‐doped n‐type organic layer/MoO₃ p‐type inorganic layer as the interconnecting unit. This work demonstrates that an air‐stable and low‐temperature‐evaporable inorganic n‐dopant can very effectively enhance the device performance in p‐i‐n and tandem OLEDs, as well as simplify the material handling for the vacuum deposition process.     

Patterned Growth of P‐Type MoS2 Atomic Layers Using Sol–Gel as Precursor

2D layered MoS₂ has drawn intense attention for its applications in flexible electronic, optoelectronic, and spintronic devices. Most of the MoS₂ atomic layers grown by conventional chemical vapor deposition techniques are n‐type due to the abundant sulfur vacancies. Facile production of MoS₂ atomic layers with p‐type behavior, however, remains challenging. Here, a novel one‐step growth has been developed to attain p‐type MoS₂ layers in large scale by using Mo‐containing sol–gel, including 1% tungsten (W). Atomic‐resolution electron microscopy characterization reveals that small tungsten oxide clusters are commonly present on the as‐grown MoS₂ film due to the incomplete reduction of W precursor at the reaction temperature. These omnipresent small tungsten oxide clusters contribute to the p‐type behavior, as verified by density functional theory calculations, while preserving the crystallinity of the MoS₂ atomic layers. The Mo containing sol–gel precursor is compatible with the soft‐lithography techniques, which enables patterned growth of p‐type MoS₂ atomic layers into regular arrays with different shapes, holding great promise for highly integrated device applications. Furthermore, an atomically thin p–n junction is fabricated by the as‐prepared MoS₂, which shows strong rectifying behavior.     

Cover Picture: Bilayer Organic–Inorganic Gate Dielectrics for High‐Performance,Low‐Voltage,Single‐Walled Carbon Nanotube Thin‐Film Transistors,Complementary Logic Gates,and p–n Diodes on Plastic Substrates (Adv. Funct. Mater. 18/2006)

Low‐voltage, hysteresis‐free, flexible thin‐film‐type electronic systems based on networks of single‐walled carbon nanotubes and bilayer organic–inorganic nanodielectrics are detailed in work by Rogers and co‐workers reported on p. 2355. The cover image shows a schematic array of such thin‐film transistors (TFTs) on a plastic substrate. The structure of the bilayer nanodielectric, which consists of a film of HfO₂ formed by atomic layer deposition and an ultrathin layer of epoxy formed by spin‐casting, is also illustrated schematically. High‐capacitance bilayer dielectrics based on atomic‐layer‐deposited HfO₂ and spin‐cast epoxy are used with networks of single‐walled carbon nanotubes (SWNTs) to enable low‐voltage, hysteresis‐free, and high‐performance thin‐film transistors (TFTs) on silicon and flexible plastic substrates. These HfO₂–epoxy dielectrics exhibit excellent properties including mechanical flexibility, large capacitance (up to ca. 330 nF cm^–2), and low leakage current (ca. 10^–8 A cm^–2); their low‐temperature (ca. 150 °C) deposition makes them compatible with a range of plastic substrates. Analysis and measurements of these dielectrics as gate insulators in SWNT TFTs illustrate several attractive characteristics for this application. Their compatibility with polymers used for charge‐transfer doping of SWNTs is also demonstrated through the fabrication of n‐channel SWNT TFTs, low‐voltage p–n diodes, and complementary logic gates.     

A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic

Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation.     

Feasibility of substrate fed threshold logic

Proposes a modified integrated injection logic (I/SUP 2/L) structure called substrate fed threshold logic (SFTL) for the implementation of multivalued logic. In this structure, threshold current is supplied from the p/SUP +/ substrate to the top p region through the windows in the n/SUP +/ buried layer, and the magnitude of the threshold current is determined by the number of injection windows. The feasibility of the structure is discussed theoretically and experimentally. The results show that four-valued threshold logic is possible with the proposed structure.