Power Consumption of Quasi-adiabatic Logic Gates

A computer simulation is carried out to investigate the power consumption of major quasi-adiabatic logic gates. Anomalously high dissipation is found at low clock rates. An explanation for the anomaly and a method of eliminating this are proposed. For the dissipated energy W and the clock rate f, it is found that W f C ^{1 +} as f tends to infinity, where is essentially less than unity. The mechanism of the phenomenon is identified. Rules are established that govern the power consumption of the logic gates. It is concluded that they should help one to strike a balance between power consumption and speed, to optimize power characteristics, and to predict the performance of future models made by better process technologies.     

Symmetric Adiabatic Logic Circuits against Differential Power Analysis

We investigate the possibility of using adiabatic logic as a countermeasure against differential power analysis (DPA) style attacks to make use of its energy efficiency. Like other dual‐rail logics, adiabatic logic exhibits a current dependence on input data, which makes the system vulnerable to DPA. To resolve this issue, we propose a symmetric adiabatic logic in which the discharge paths are symmetric for data‐independent parasitic capacitance, and the charges are shared between the output nodes and between the internal nodes, respectively, to prevent the circuit from depending on the previous input data.     

采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路--complementary pass-transistor adiabatic logic(CPAL).电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MOSIS的0.25μm CMOS工艺,在50～200MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2N-2N2P电路的50%和35%.     

采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路——complementary pass- transistor adiabatic logic (CPAL ) .电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MO-SIS的0 .2 5μm CMOS工艺,在5 0～2 0 0 MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2 N - 2 N2 P电路的5 0 %和35 % .     

一种交叉耦合低功耗传输门绝热逻辑电路

提出了一种新的能量恢复型电路—— Transmission Gate Adiabatic Logic(TGAL)。该电路由交叉耦合的 CMOS传输门完成逻辑运算与能量恢复 ,对负载的驱动为全绝热过程。TGAL电路输出端始终处于箝位状态 ,在整个输出期不存在悬空现象并具有良好的信号传输效果。分析了 TGAL反相器的能耗 ,并与静态 CMOS电路及部分文献中绝热电路进行了比较。使用 TGAL构成门电路与时序系统的实例被演示。应用 MOSIS的0 .2 5 μm CMOS工艺参数的模拟结果表明 ,与传统 CMOS和 2 N-2 N2 P绝热电路相比 ,TGAL电路在 1 0 0 MHz工作频率时分别节省 80 %与 60 %以上的功耗。     

一种BTL低静态功耗CMOS音频功率放大器的设计

对AB类CMOS音频功率放大系统中的核心运放单元电路结构,即基于共漏与共源并联组合的功率级放大电路进行了改进与优化设计a基于CSMC0.6 μm CMOS工艺的仿真结果表明,在5 V电源电压下,静态电流仅为1.59 mA.BTL模式驱动4 Ω的负载,当1 kHz频率点的总谐波失真小于0.1%时,获得的最大输出功率可以达到2 W,电源转换效率为60.7%.     

基于静态逻辑蕴涵的电路功耗优化

介绍一种针对经过工艺映射的组合逻辑电路进行功耗优化的方法.首先根据电路节点的翻转频率对节点进行分类,每次考虑一个节点,找出它在电路中的直接和间接蕴涵;然后利用这些蕴涵在电路添加一些逻辑门和连接,来增加电路的冗余;最后去除这些冗余来化简电路,去除那些高功耗的节点,从而减少整个电路的翻转活动,降低功耗.这个过程是重复的,每次重复从一个新的节点开始,最后得到一个跳变减少的电路.     

门控逻辑信号的非易失性数字电位计

本设计实例描述了一个非易失性门控功能的简单替代方案,通常实现门控功能要使用PAL(可编程逻辑阵列)、GAL(门阵列逻辑)或CPLD(复杂可编程逻辑器件).     

基于常规逻辑门和原理图方式的可逆逻辑描述

针对可逆逻辑综合在设计较大规模可逆逻辑电路(ALU)时遇到的瓶颈问题。文中借用现行EDA技术的逻辑描述和验证能力,可逆逻辑门的功能表达式为依据,设计具有等功能的常规逻辑组合电路,通过等功能代换的方法,设计实现以常规原理图方式描述的可逆ALU。仿真图中显示的16种运算结果表明,该方法具有一定的可行性和有效性。     

Adiabatic Logic Circuits: A Review

The current status of research and development in the field of adiabatic electronic devices for the production of information is reviewed. The adiabatic property means that the power supply regains most of the energy expended on computing. A design philosophy of universal adiabatic logic gates is framed. The gates are categorized according to adiabatic rank, the principle of operation, the method used to satisfy the thermal-equilibrium conditions, the information-storage technique, and the mode of operation. For adiabatic-gate drivers, existing design concepts are categorized and described. Promising avenues of development are outlined.     

二种EPAL绝热开关电路

研究和设计了两种低功耗的EPAL(efficientPAL)绝热开关电路.这两种电路均采用逐级相位落后90°的四相正弦功率时钟.讨论了EPAL电路的设计方法,并在不同时钟频率和不同的负载条件下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟.模拟结果表明这两类电路均能完成正确的逻辑功能.两种EPAL的五级反相器/缓冲器电路在功率时钟频率为10MHz时都比相应的PAL-2N电路节省80%以上的功耗,在400MHz时功耗节省也分别可达23%和50%.EPAL电路可以工作于更高的时钟频率,有更强的驱动负载能力和更低的输出波形畸变     

二种EPAL绝热开关电路

研究和设计了两种低功耗的EPAL(efficient PAL)绝热开关电路.这两种电路均采用逐级相位落后90°的四相正弦功率时钟.讨论了EPAL电路的设计方法,并在不同时钟频率和不同的负载条件下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟.模拟结果表明这两类电路均能完成正确的逻辑功能.两种EPAL的五级反相器/缓冲器电路在功率时钟频率为10MHz时都比相应的PAL-2N电路节省80%以上的功耗,在400MHz时功耗节省也分别可达23%和50%.EPAL电路可以工作于更高的时钟频率,有更强的驱动负载能力和更低的输出波形畸变.     

门电路构成的多谐振荡器的仿真方法

给出了用于仿真的门电路多谐振荡器的实际电路结构，在发现直接应用OrCAD Capture提供的门电路模型，对门电路多谐振荡器进行仿真失败的前提下，提出了创建由子电路模型构成新元件，然后对电路进行仿真的方法。实际的仿真结果表明该方法正确，应用效果良好，这一方法可以解决含门电路多谐振荡器电路的仿真问题，并对其他复杂电路的仿真具有重要参考价值。     

Pulse Noise Immunity in Saturated Logic Gates

This paper develops techniques for assessing the inherent pulse noise immunity of saturated logic gates, with a view towards determining their ability to operate reliably in a pulse noise environment. A test method has been outlined for specifying and measuring this noise immunity. Although this method is applicable to all forms of saturated logic, the low level T /sup 2/ L gate has been singled out for experiment because of its high speed capability. Using both discrete component and microcircuit gates of this type, close correlation was obtained between experimental results and calculations based on internal parameters of the individual devices.     

忆阻器实现逻辑门的方法研究

在分析忆阻器特性及相关文献的基础上提出了一种只使用忆阻器元件实现基本逻辑门的电路方案,理论分析及Spice仿真实验结果证实了方案的可行性．所设计的逻辑门电路简单,实现的逻辑门无需时序操作就能工作,其在电路尺寸、集成密度、电路功耗等方面拥有很大的优势．     

量子逻辑门核磁共振实验的仿真实现

利用核磁共振(NMR)实验技术来实现量子计算，是当前各种验证量子算法最为有效的方法之一。对如何设计核磁共振(NMR)脉冲序列来实现各种量子逻辑门，如量子控非门、toffoli门等进行了研究。并在量子仿真器(QCE)上进行实验验证。     

A New Static Differential CMOS Logic with Superior Low Power Performance

A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, making it simple to design. The circuit topology of the DSCL and its operation is explained. Delay optimization of the new circuits was performed. It showed the fully static behavior of these circuits. Their performance in terms of delay, power, and area is compared to that of conventional static differential logic and dynamic differential logic. Spice simulations using a 0.18 m technology with a power supply of 1.8 V was utilized to evaluate the performance of the three circuits. Two different sets of simulations were carried out; one with equal input capacitances of all circuits and another with equal circuit delays. For each design, all circuits were optimized for minimum delay. It is shown that at equal input capacitance, the DSCL achieved 40% less delay than the DCVSL at one third the power. Also, at equal delay, the DSCL achieved 20% of the power dissipation of the DCVSL and 78% of the DDCVSL making it the most energy-efficient among the three circuits.Muhammad E.S. Elrabaa received his B.Sc. degree in computer Engineering from Kuwait University, Kuwait in 1989, and his M.A.Sc. and PhD degrees in Electrical Engineering from the University of Waterloo, Waterloo, Canada, in 1991 and 1995, respectively. His graduate research dealt with Digital BiCMOS ICs and Low-Power circuit techniques. From 1995 till 1998, he worked as a senior circuit designer with Intel Corp., in Portland, Oregon, USA. He designed and developed low power digital circuits for Microprocessors. From 1998 till 2001 he was with the EE department, UAE University as an assistant professor. In 2001, he joined the computer Engineering department, KFUPM University. His current research interests include reconfigurable computing, low-power circuits, and communication circuits. He authored and co-authored several papers, a book and holds two US patents.     

电路抗老化设计中基于门优先的关键门定位方法

随着CMOS工艺尺寸不断缩小,尤其在65 nm及以下的CMOS工艺中,负偏置温度不稳定性(NBTI)已经成为影响CMOS器件可靠性的关键因素。提出了一种基于门优先的关键门定位方法,它基于NBTI的静态时序分析框架,以电路中老化严重的路径集合内的逻辑门为优先,同时考虑了门与路径间的相关性,以共同定位关键门。在45 nm CMOS工艺下对ISCAS基准电路进行实验,结果表明:与同类方法比较,在相同实验环境的条件下,该方法不仅定位关键门的数量更少,而且对关键路径的时延改善率更高,有效地减少了设计开销。     

SoC设计中的低功耗逻辑综合策略

介绍了一种SoC(片上系统)电路的高效逻辑综合方法,用工具对功耗关键模块插入时钟门控单元来降低功耗,并用工具提取不带时钟门控模块的约束条件来优化相应带门控的模块,使SoC在最高主频率、面积和功耗等方面达到最优,且时序收敛较快.采用该方法对Unity805plus SoC芯片进行综合,取得比自顶向下、自底向上等传统综合方法更好的效果,在最差情况下最高频率为200 MHz,面积为8 773 410μm2,功耗为724.920 4 mW.在ULTRA60上运行时间为14h.[关键词:逻辑综合,SoC,时序收敛     

基于绝热逻辑的低功耗乘法器电路设计

基于绝热开关理论的能量回收逻辑与传统的静态CMOS逻辑相比,能够大大减少电路的功率消耗。这里介绍了一种使用单相正弦电源时钟的能量回收逻辑,分别用静态CMOS逻辑和这种能量回收逻辑设计,并仿真了一个两位乘法器电路,比较了这两种电路的性能。研究表明,采用能量回收逻辑设计的乘法器显著降低了电路的功率消耗。