Grain boundary diffusion and growth of titanium silicide layers on silicon

A kinetics study of titanium silicide formation is described. The results show that a fine grained precursor layer exist in between the well developed C-54 silicide layer and the unreacted titanium film. This layer is a mixture of C49-TiSiV₂ and unreacted titanium. The fact that no C54-TiSi₂ formed directly from the Ti-Si reaction suggests that the nucleation of C49-TiSi₂ is easier than that of C54-TiSi₂ under our annealing conditions. The silicide layer growth has a non-t^1/2 dependence and is much better described by a grain boundary diffusion limited model giving different kinetics. This indicates that grain boundary diffusion is the major atomic transportation mechanism. The growth rate depends on both the grain boundary diffusion coefficient and the silicide grain growth rate.     

In-situ study of stress evolution during solid state reaction of Pd with Si(001) using synchrotron radiation

Using X-ray diffraction experiments and curvature measurements, in-situ real-time measurements of stress are performed during solid state reaction of a palladium thin film with Si(001). From X-ray diffraction measurements and using the sin²ψ method, we found out that the stress in the metal and in the silicide is compressive. This stress decreases all along the solid-state reaction for the silicide. We then compared our results with the qualitative model proposed by Zhang and d’Heurle. This model suggests the development of a high compressive stress (−2.4 GPa) in the silicide.     

Evaluation of Transmission Line Model Structures for Silicide-to-Silicon Specific Contact Resistance Extraction

In order to measure silicide-to-silicon specific contact resistance rho_c, transmission line model (TLM) structures were proposed as attractive candidates for embedding in CMOS processes. We optimized TLM structures for nickel silicide and platinum silicide and evaluated them for various doping levels of n- and p-type Si. The measurement limitations and accuracy of the specific contact resistance extraction from the optimized TLM structures are discussed in this paper.     

在薄二氧化硅层上纯多晶硅化镍膜的研究

本文研究了在薄二氧化硅层上快速热退火（RTA）形成的多晶硅化镍膜的电特性，对于在薄二氧化硅上的纯硅化镍膜，测试了其到衬底的泄漏电流，发现二氧化硅性质仍类似于多晶硅膜或纯铝膜下二氧化硅性质，采用准静态C－V方法研究了多晶硅栅和纯硅化镍栅的多晶栅耗尽效应（PDE），并探讨了硅化镍栅掺杂浓度和栅氧化层厚度对PDE的影响，结果表明，即使在未被掺杂的纯硅化镍栅膜，也未曾观察到PDE。     

Source/drain contact resistance of silicided thin-film SOI MOSFET's

We developed a source/drain contact (S/D) resistance model for silicided thin-film SOI MOSFET's, and analyzed its dependence on device parameters considering the variation in the thickness of the silicide and residual SOI layers due to silicidation. The S/D resistance is insensitive to the silicide thickness over a wide range of thicknesses; however, it increases significantly when the silicide thickness is less than one hundredth of initial SOI thickness, and when almost all the SOI layer is silicided. To obtain a low S/D resistance, the specific contact resistance must be reduced, that is, the doping concentration at the silicide-SOI interface must be more than 10²⁰ cm^-3     

Silicide application on gated single-crystal, polycrystalline andamorphous silicon FEAs. II. Co silicide

For pt. I see ibid., vol.48, no.1, p.149-54 (Jan. 2001). For enhancement and stabilization of electron emission, Co silicides were formed from Co, Co/Ti and Ti/Co layers on silicon FEAs. Since Ti prevents oxygen adsorption on the Co film during silicidation, uniform and smooth Co silicide layers can be obtained by depositing Co first and then Ti on silicon tips, followed by rapid annealing. Among Co silicide FEAs, Co silicide formed from Ti/Co bi-layers shows the lowest leakage current, the highest failure voltage over 152 V and the largest anode current over 1 mA at the gate voltage of 150 V. Compared with silicon field emitters, the silicide FEAs formed from Ti/Co layers exhibited a significant improvement in maximum emission current, emission current fluctuation and stability, and failure voltage     

Titanium silicide-silicon interface degradation during heat treatment

Thin titanium silicide films were grown on different silicon substrates by rapid thermal annealing in a nitrogen ambient. The silicide films were then annealed in a furnace at high temperature in a nitrogen ambient for various times. The effect of such heat treat-ment on the morphology of titanium silicide surface and the titanium silicide-silicon interface was studied. It is proposed that the morphological change is primarily due to the diffusion of silicon and/or dopant impurities via grain boundaries of the silicide. There is a strong correlation between the surface of the titanium silicide film and that of the titanium silicide-silicon interface.     

A self-aligned CoSi2interconnection and contact technology for VLSI applications

Cobalt silicide is investigated in view of possible application in a self-aligned technology. Extremely smooth, highly conductive CoSi2films are obtained using rapid thermal processing for silicide formation starting from deposited cobalt layers (on Si). The phase formation is studied by XRD and RBS. No lateral silicide formation is observed at contact edges. The influence of Si consumption and dopant behavior on diode performance is studied. Shallow arsenic (0.15 µm deep) and boron (0.3 µm deep) junctions are successfully silicided. Very low contact resistances are obtained between the silicide and n+ and p+ regions. MOS transistors were fabricated with CoSi2on the source, drain, and gate. An increase in current driving capability is noticed while no degradation of other electrical parameters due to the silicide processing steps is observed. At some critical points, comparison is made with the TiSi2process.     

Development of the self-aligned titanium silicide process for VLSI applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Ω/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-µm gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, linewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.     

太赫兹Si/SiGe量子级联激光器波导模拟

波导层结构设计是制备太赫兹(THz)量子级联激光器的关键问题之一.本文基于德鲁得(Drude)模型,利用时域有限差分(FDTD)法,对Si/SiGe量子级联激光器的波导层进行优化设计,从理论上对传统的递变折射率波导、单面金属波导、双面金属波导以及金属/金属硅化物波导横磁模(TM模)的模式损耗和光场限制因子进行了对比分析.结果表明,金属/金属硅化物波导不但可以减小波导损耗,而且有很高的光学限制因子,同时其工艺也比双面金属波导容易实现,为Si/SiGe太赫兹量子级联激光器波导层的设计提供了一定的理论指导.     

Development of the Self-Aligned Titanium Silicide Process for VLSI Applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Omega/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-/spl mu/m gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, Iinewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.     

太赫兹Si/SiGe量子级联激光器波导模拟

波导层结构设计是制备太赫兹(THz)量子级联激光器的关键问题之一.本文基于德鲁得(Drude)模型,利用时域有限差分(FDTD)法,对Si/SiGe量子级联激光器的波导层进行优化设计,从理论上对传统的递变折射率波导、单面金属波导、双面金属波导以及金属/金属硅化物波导横磁模(TM模)的模式损耗和光场限制因子进行了对比分析.结果表明,金属/金属硅化物波导不但可以减小波导损耗,而且有很高的光学限制因子,同时其工艺也比双面金属波导容易实现,为Si/SiGe太赫兹量子级联激光器波导层的设计提供了一定的理论指导.     

Arsenic redistribution induced by low-temperature Ni silicidation at 450°C on shallow junctions

Redistribution of arsenic (As) during silicidation of a 13-nm Ni film on an n⁺/p junction at 450°C is investigated. NiSi formation is observed by x-ray diffraction, micro-Raman scattering spectroscopy, and Rutherford backscattering spectroscopy (RBS). Both secondary ion mass spectroscopy and RBS data indicate the redistribution and accumulation of As into two layers after the low-temperature annealing. The deeper accumulation peak, located just near the silicide/silicon interface, is attributed to As segregation from silicide into Si substrate. The shallower accumulation peak is located in a vacancy-cluster layer several nanometers below the silicide film surface. The vacancy-cluster layer, characterized by cross-sectional transmission electron microscopy, separates the silicide film into two layers, and is attributed to the well-known Kirkendall effect.     

A formation of cobalt silicide on silicon field emitter arrays byelectrical stress

A novel process utilizing electrical stress is proposed for the formation of Co silicide on single crystal silicon (c-Si) FEAs to improve the field emission characteristics. Co silicide FEAs formed by electrical stress (ES) exhibited a significant improvement in turn-on voltage and emission current compared with c-Si FEAs. The improvement mainly comes from the lower effective work function of Co silicide and less blunting of tips during silicidation by electrical stress in an ultra high vacuum (UHV) environment less than 10^-8 torr     

Formation of TiSi2 and shallow junction byAs+ ion-beam mixing and infrared rapid heat treatment

A technique for forming shallow junctions with low-resistance silicide contacts developed for the use in VLSI with scaled MOSFETs is discussed. The salicide (self-aligned silicide) MOSFET gate and source-drain features self-aligned refractory metal silicide and are isolated from one another even without any insulating spacer on the gate sides. A critical step in such a MOSFET fabrication process is the ion implantation through metal silicidation technique, which includes As⁺ ion-beam-induced titanium-silicon interface mixing and infrared rapid heat treatment to form simultaneously the n⁺-p junction and a high-quality TiN covered TiSi₂ contact layer     

Schottky–ohmic transition in nickel silicide/SiC-4H system: is it really a solved problem?

The transition from Schottky to ohmic contact in the nickel silicide/SiC system during annealing from 600 to 950 °C was investigated by measuring the electrical properties of the contact and by analyzing the microstructure of the silicide/SiC interface. The graphite clusters formed by carbon atoms during silicidation are uniformly distributed into the silicide layer after annealing at 600 °C and they agglomerate into a thin layer far from the silicide/SiC interface after annealing at 950 °C. At this temperature an increase of the Schottky barrier height was measured, while deep level transient spectroscopy evidences the absence of the 0.5 eV peak related to the carbon vacancies.     

PECVD法制备硅化钛膜的工艺研究

硅化钛薄膜由于电阻率低和其它一些良好特性,在VLSI的栅电极和互连线中显示出它潜在的优势。本文研究了用PECVD法制备硅化钛膜的卫艺。结果表明:所形成硅化钛膜的性质强烈地依赖于淀积工艺条件。还确定了典型工艺条件,并用俄歇电子能谱分析了硅化钛膜的组分。     

Effects of alloying elements on cobalt silicide formation

Alloying elements can substantially affect the formation of cobalt silicide. A comprehensive study of phase formation was performed on 23 Co alloys with alloying element concentrations ranging from 1 at.% up to 20 at.%. Using in-situ characterization techniques in which x-ray diffraction (XRD) and elastic-light scattering are monitored simultaneously, we follow the formation of the silicide phases and the associated variation in surface roughness in real time during rapid thermal annealing. For pure Co silicide, we detect the formation of all stable silicide phases (Co₂Si, CoSi, and CoSi₂) as well as abnormal grain growth in the Co film and thermal degradation of the silicide layer at high temperatures. The effect of the various additives on phase formation was determined. The roughness of the interface was also measured using grazing incidence x-ray reflectivity (GIXR). We show that by selecting an alloy with a specific composition, we can change the phase-formation temperatures and modify the final CoSi₂ film texture and roughness.     

Stable tantalum silicide Schottky barrier on n-type gallium arsenide evaluated at elevated temperatures

The high-temperature stability of sputtered tantalum silicide contacts on gallium arsenide has been evaluated. Diodes consisting of Ta silicide on epitaxial n (1.9 × 1017 cm?3; 0.23 ?m/n+ GaAs substrate were annealed at temperatures from 375°C to 800°C. Result show that the ideality factor, barrier height and reverse breakdown voltage remain stable at value of 1.1, 0.79 V and 9 V, respectively. MESFETs with Ta silicide gates exhibited similar drain current/voltage characteristics as conventional Cr/Au gate devices.     

Verification structures for transmission line pulse measurements

Test structures intended for performance verification of transmission line pulse (TLP) systems have been designed and tested. They consist of simple resistors in either copper or silicide clad polysilicon. The copper structures proved unsuitable due to excess heating and melting of any reasonable geometry. The silicide clad polysilicon proved more successful. A simple model of resistive heating accounts for observed nonlinearity in the structures under high current stress. The availability of a verification structure on wafer ensures the proper performance of the full measurement system, including contact to the wafer and the pad structure, ensuring valid TLP measurements.