超薄氧化层的电击穿特性

本文在测试分析N 理层—隧道氧化层一多晶硅电容（N OP电容）、P衬底一隧道氧化层一多晶硅电容（POP电容）和EEPROM单元隧道氧化层电容（TOP电容）的I－V特性、I－t特性、V－t特性的基础上,对隧道氧化层的击穿特性进行了理论分析,并提出了提高隧道氧化层可靠性的具体措施。     

集成电路中栅介质膜的C－V测试误差分析及其修正模型

通过具有各种串联电路的ＭＯＳ电容的分析测试表明：串联电阻引起ＭＯＳＣ－Ｖ特性畸变、失真，并与介质膜电容大小有关；串联电容使ＭＯＳＣ－Ｖ特性严重不稳定；而当存在电容和电阻并联的串联电路时，即使串联电路中的电阻高达１ｋΩ以上，只要其并联的电容远大于介质膜电容，这个串联电路的影响就可以忽略不计。也测试分析了硅衬底参数和测试环境对ＭＯＳＣ－Ｖ特性的影响。指出了改善测试分析准确性的各种有效途径。提出了ＭＯＳＣ－Ｖ特性的串联电阻修正模型。即：存在串联电阻效应的判据；ＭＯＳＣ－Ｖ特性失真的判据；串联电阻计算公式、电容修正公式及ＭＯＳＣ－Ｖ修正过程。举例说明修正模型编程的实际应用：超薄栅氧化层ＭＯＳＣ－Ｖ特性的修正；ＣＭＯＳ电路中，Ｐ阱中ＭＯ５电容Ｃ－Ｖ特性的修正。     

用镶嵌工艺制作金属/高k晶体管

东芝公司的研究人员认为,２ｍｍ以下的薄栅介质是开发高性能晶体管的最佳材料。这意味着栅材料从现在采用的重掺杂多晶硅栅和ＳｉＯ２栅氧化层向金属栅和高ｋ栅介质材料发展。 金属栅与多晶硅栅相比,其优点是不受栅耗尽效应的影响。高ｋ介质的优点是介质材料具有较高的介质常数（ｋ值）以及较低的隧道电流密度。同时,由于它们具有较大的电容,所以在相似的电特性下,能淀积的膜层厚度比二氧化硅膜厚。高ｋ材料包括Ｔａ氧化层、Ｔｉ氧化层、Ｚｒ氧化层以及Ｈｆ氧化层。 促使开发镶嵌栅工艺的一个因素是用反应离子刻蚀薄栅氧化层图形太难,…     

一种高速高压NPN管的研制

把Ｎｉｎｇ－Ｔａｎｇ测试发射极电阻的方法进行扩展，用来测试多晶发射极界面氧化层电阻，作发射极界面氧化层电阻与多晶硅发射极晶体管退火的优化实验，获得退火的优化工艺条件，并由此成功地研制出ＢＶＣＥＯ≥３０，ＢＶＣＢＯ＝７５Ｖ，ｆｒ＝２ＧＨｚ，β＝１８０的多晶硅发射极晶体管。用扩展电阻ＳＳＭ１５０型测多晶硅发射极晶体管的纵向杂质分布，得出多晶硅发射极晶体管的发射区结深为５０ｎｍ，基区结深为２０ｎｍ。     

不连续类氧化层界面多晶硅发射极晶体管理论模型

本文提出了一个不连续类氧化层界面多晶硅发射极晶体管理论模型,根据多晶/单晶硅界面的性质空穴分别以隧道方式或热发射方式通过界面的不同部位.计算机模拟的结果得到了类氧化层界面的连续性、多晶硅膜厚、类氧化层两边的界面态密度、类氧化层厚度和多晶/单晶硅界面杂质浓度峰值等参数与多晶硅发射极晶体管(PET)电学特性的关系.     

EEPROM失效机理初探

在分析了双层多晶硅FLOTOXEEPROM各种失效模式后，从理论上提出了提高EEPROM可靠性的各种措施。提高隧道氧化层和多晶硅之间氧化层的质量，减小擦／写电压和擦／写时间，减小隧道氧化层的面积，都是提高EEPROM可靠性的有效措施。     

LPCVD多晶硅形貌对氧化层击穿特性的影响

多晶硅表面对于电荷耦合器件(CCD)的制作非常重要。采用扫描电子显微镜(SEM)和电学分析技术研究了低压化学气相(LPCVD)法淀积的多晶硅形貌对击穿特性的影响。研究结果表明,减小多晶硅表面颗粒尺寸有助于改善多晶硅氧化层击穿特性。多晶硅氧化层击穿特性与多晶硅和绝缘层交界面的平滑度有关。多晶硅薄膜表面平整度变差,则多晶硅与氧化层之间的界面平滑性变差,多晶硅介质层击穿强度降低。     

多晶硅部分剥离技术对抗辐照VDMOS动态特性的影响

在考虑VDMOS器件的抗辐照特性时,为了总剂量辐照加固的需求,需要减薄氧化层的厚度,然而,从VDMOS器件的开关特性考虑,希望栅氧化层厚度略大些。本文论证了在保证抗辐照特性的需求的薄氧化层条件下,采用漂移区多晶硅部分剥离技术以器件动态特性的可行性,研究了该结构对器件开启电压、击穿电压、导通电阻、寄生电容、栅电荷等参数的影响,重点研究了漂移区多晶硅窗口尺寸对于VDMOS动态特性的影响。模拟结果显示,选取合理的多晶硅尺寸,可以降低栅电荷Qg,减小了栅-漏电容Cgd,减小器件的开关损耗、提高器件的动态性能。     

高场应力下FLOTOXMOS管的性能退化研究

利用氧化层动态电流弛豫谱分析方法,测试分析了在周期性电场应力下ＦＬＯＴＯＸＭＯＳ管隧道氧化层中陷阱电荷的特性,为研究陷阱电荷对ＦＬＯＴＯＸ ＥＥＰＲＯＭ 阈值电压的影响提供了实验依据。在＋ １１ Ｖ、－ １１ Ｖ 周期性老化电压下所产生的氧化层陷阱电荷饱和密度分别为－ １．８×１０１１ ｃｍ － ２和－ １．４×１０１１ ｃｍ － ２,平均俘获截面分别为５．８×１０－ ２０ ｃｍ ２ 和７．２×１０－ ２０ ｃｍ ２,有效电荷中心距分别为３．８ ｎｍ 和４．３ ｎｍ ,界面陷阱电荷饱和密度分别为６．５４×１０９ ｃｍ － ２ｅＶ－ １和－ ３．８×１０９ ｃｍ － ２ｅＶ－ １,平均俘获截面分别为１．１２×１０－ １９ ｃｍ ２ 和４．９×１０－ １９ ｃｍ ２。     

一种低压智能功率集成技术

本文介绍了一种以传统多晶硅栅ＶＤＭＯＳ工艺为主的新型自隔离智能功率集成工艺技术。该技术可以将ＶＤＭＯＳ、ＨＶ－ＣＭＯＳ、ＬＶ－ＣＭＯＳ、ｎｐｎ双极晶体管、齐纳二极管、电容等器件集成在同一单片电路中。整个工艺仅１０块掩模版。结合我们研制的高边智能功率开关电路，对器件结构、特性和工艺设计考虑进行了详细的分析。     

Boron channel-stop design for poly-buffered LOCOS using selectiveboron segregation

A boron channel-stop compensation technique using a selective polysilicon etch prior to field oxidation is proposed for CMOS isolation technologies which use polysilicon buffered LOCOS. The stress relief polysilicon layer is selectively removed over the n-well field regions which results in additional boron segregation into the growing field oxide while the polysilicon layer is being oxidized over the p-well field regions. The resulting field threshold voltages are increased by as much as 11.6 and 6.4 V for the p-well and n-well MOS capacitors, respectively     

High performance scaled flash-type EEPROMs fabricated by in situ multiple rapid thermal processing

Flash-type EEPROMs were fabricated for the first time by in situ multiple rapid thermal processing (RTP) modules. In the paper, rapid thermal oxynitridation tunnel oxide (RTONO) formation followed by in situ arsenic (As)-doped floating gate polysilicon growth by rapid thermal chemical vapour deposition (RTCVD) were introduced. The flash cell indicates only 20% narrowing of the V/sub t/ window after 5*10/sup 4/ program/erase cycle stress. Moreover, there is a higher breakdown field of the ONO film on the floating-gate polysilicon film owing to extremely flat poly-Si surface. Thus, the in situ multiple RTP technology is the key for future flash memory fabrication processes.<>     

3.4nm超薄SiO2栅介质的特性

用LOCOS工艺制备出栅介质厚度为3.4nm的MOS电容样品,通过对样品进行I-V特性和恒流应力下V-t特性的测试,分析用氮气稀释氧化法制备的栅介质的性能,同时考察了硼扩散对栅介质性能的影响.实验结果表明,制备出的3.4nm SiO₂栅介质的平均击穿场强为16.7MV/cm,在恒流应力下发生软击穿,平均击穿电荷为2.7C/cm².栅介质厚度相同的情况下,P⁺栅样品的击穿场强和软击穿电荷都低于N⁺栅样品.     

Stability of polysilicon thin film transistors under switch operating

Ageing of low temperature polysilicon Thin Film Transistors (TFTs) under AC gate bias stress is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine to fabricate n-type transistors. The active layer and the drain arid source regions are Solid Phase Crystallized. The field effect mobility is higher than 100 cm²/V.s, the subthreshold slope around 0.6 V/dec, the threshold voltage around 0.2V and the switching time around 370 nsec.As these TFTs are commonly used as switching devices in the most of applications in large area electronics field, the study of their stability under AC electrical stress is important. The present work shows that the effect of the positive or negative DC stress is higher than that of the AC stress and then the degradation of polysilicon TFTs is over-estimated when it is checked from the effects of DC gate bias stress.Degradation under bias stress is shown to originate from the creation of gap states at the channel-interface oxide and in the channel material. The lower influence of the AC stress is explained from an annealing effect of the created states by the application of an opposite sign bias stress.     

Observation of high interface state densities at the silicon/oxide interface for low doped polysilicon/oxide/silicon capacitor structures

In this work, we present new observations noted in the capacitance–voltage behaviour of polysilicon/oxide/silicon capacitor structures. As the active doping concentration reduces in the polysilicon layer, an anomalous capacitance–voltage behaviour is measured which is not related directly to depletion into the polysilicon gate. From examination of the frequency dependence of the capacitance–voltage characteristic, in conjunction with analysis and simulation, the anomalous capacitance–voltage behaviour is explained by the presence of a high density of near-monoenergetic interface states located at the silicon/oxide surface. The density and energy level of the interface states are determined. Furthermore, the work presents a mechanism by which the polysilicon doping level can impact on the properties of the silicon/oxide interface.     

Characterization of thin textured tunnel oxide prepared by thermaloxidation of thin polysilicon film on silicon

In this paper, the characteristics of thin textured tunnel oxide prepared by thermal oxidation of thin polysilicon film on Si substrate (TOPS) are studied. Because of the rapid diffusion of oxygen through the grain boundaries of the thin polysilicon film into the Si substrate and the enhanced oxidation rate at the grain boundaries, the oxidation rate of the TOPS sample is close to that of a normal oxide grown on a (111) Si substrate. Also, a textured Si/SiO₂ interface is obtained. The textured Si/SiO₂ interface results in localized high fields and causes a much higher electron injection rate. The optimum TOPS sample can be obtained by properly oxidizing the stacked α-Si film, independent of the substrate doping level. Also, the optimum TOPS sample exhibits a smaller electron trapping rate and a lower interface state generation rate when compared to the sample from a standard tunnel oxide process. These differences are attributed to a lower bulk electric field and a smaller injection area in the TOPS samples     

A simple method for extracting average doping concentration in thepolysilicon and silicon surface layer near the oxide in polysilicon-gateMOS structures

The author demonstrates a simple technique that extracts average doping concentration in the polysilicon and silicon near the oxide in a metal/polysilicon/oxide/silicon system. The technique is based on the maximum-minimum capacitance method on two large area structures-one MOSFET and one MOSC (MOS capacitor). The technique is simple and reliable since only three data points in the C-V data are required-two points in MOSC C-V and one point in MOSFET C-V. The technique avoids inaccuracy caused by interface traps at the polysilicon/oxide and the oxide/silicon interface. The technique can be implemented into fab routine electric-test procedures for simultaneously monitoring change of doping concentration in polysilicon and silicon during process development     

Tunnel oxide prepared by thermal oxidation of thin polysilicon filmon silicon (TOPS)

A textured tunnel oxide, TOPS, prepared by thermally oxidizing a thin polysilicon film on a Si substrate is reported. Due to the rapid diffusion of oxygen through the grain boundaries of the thin polysilicon into Si substrate and the enhanced oxidation rate at the grain boundaries, a textured Si-SiO₂ interface is obtained. The textured interface results in localized high fields and enhances electron injection into TOPS. TOPS exhibits a higher electron injection efficiency, a better immunity to the electron trapping and interface state generation under high-field operation, and a higher asymmetric injection polarity than the normal oxide     

MOSFET parameter degradation after Fowler–Nordheim injection stress

We have investigated the degradation of tunnel oxides due to Fowler–Nordheim electron injection from polysilicon gate. Tested devices are n-MOSFET normally used for Flash EPROM applications with four different technologies for the tunnel oxide layer. Stresses have been performed at different source and drain bias conditions for a total injected charge up to 1 C/cm². The oxide characteristics and degradation have been determined comparing the MOSFET threshold voltage and transconductance peak for as received devices and after each stress step.