Thin gate and analog capacitor dielectrics for submicron device fabrication

The miniaturization of devices in ULSI circuits are accompanied by shrinking vertical, as well as horizontal, device parameters such as junction depth, lateral impurity diffusion and film thicknesses. This is achieved by decoupling process steps,i.e. processing at a reduced thermal budget. However, as device dimensions decrease, greater demand in transistor noise immunity and reliability may not be achievable with low-temperature (<900° C) oxidation processes. Low temperature CVD ONO (oxide-nitride-oxide) dielectrics have been evaluated for applications in ULSI gate as well as capacitor structures. Time dependent dielectric breakdown data have shown that ONO has longer lifetime than thermal oxide of equivalent thickness. Such stacked dielectrics nevertheless result in complex processing steps. With the advances in rapid thermal processing equipment today, rapid thermal oxide (RTO) has been shown to offer potential benefits of high temperature without significant addition to the overall thermal budget. We have shown that transistors with RTO gate oxides exhibit longer lifetime and lower noise compared to those with furnace grown gate oxides. We have also shown that interpoly RTO oxides have remarkable dielectric strength of >8 MV/cm. For enhanced radiation hardness and impurity masking capability as well as higher permittivity, rapid thermal nitrided oxides may be a potential choice deserving further evaluation. These nitrided oxides must be reoxidized to reduce densities of interface states and electron traps created during the nitridation process.     

Effects of hydrogen transport and reactions on microelectronics radiation response and reliability

The transport and reactions of hydrogen-related species play critical roles in determining the ionizing radiation response and long-term reliability of Si-based metal-oxide-semiconductor (MOS) and bipolar microelectronics technologies. The role of hydrogen is reviewed in radiation-induced interface-trap formation in metal and polycrystalline-Si-gate devices, with an emphasis on understanding the transport and reaction mechanisms responsible for defect formation. Effects of hydrogen on radiation-induced oxide and border-trap charge densities are discussed. Enhanced low-dose-rate effects in bipolar devices and integrated circuits are sensitive to hydrogen transport and reactions in the oxides that overlie the emitter–base junctions. These enhanced low-dose-rate effects present great challenges for defining practical, cost-effective acceptance tests of bipolar devices for space radiation environments. In addition, a brief discussion is provided of the effects of hydrogen-related species on MOS long-term reliability, including high-field stress, dielectric leakage (e.g., stress-induced leakage current), oxide breakdown, hot-carrier effects, dopant passivation, and low-frequency (1/f) noise. The potential impacts on latent interface-trap formation are discussed for retarded hydrogen transport, trapping, and/or dopant passivation. Further, differences in proton transport and reactions are noted for (a) conventional Si/SiO₂/Si structures and (b) those with high oxygen vacancy densities that are exposed to high-temperature hydrogen annealing ambients. In the former, hydrogen is consumed irreversibly by processes such as interface-trap formation; in the latter, hydrogen often can be cycled from the gate to the Si interface reversibly without losses for up to 10⁶ cycles or more. Moreover, the inferred transport rates are much higher for post-forming-gas anneal transport than for radiation-induced interface-trap buildup. Finally, the motion of hydrogen during post-process, but pre-irradiation, thermal treatments (e.g., burn-in, or temperature cycles during the packaging process) has been associated with significant changes in the radiation response of both MOS and bipolar transistors. Typical mitigation techniques are discussed to reduce the effects of hydrogen on MOS radiation response and long-term reliability. Several unresolved issues and opportunities for future work are identified. The present knowledge of hydrogen effects on the long-term reliability and radiation response of Si based microelectronics will be broadened significantly as alternative dielectrics to SiO₂ are increasingly introduced into the manufacturing process. A brief example of the significant effects of hydrogen on dielectric layers other than SiO₂ is provided for deposited diamond thin films.     

Effect of rapid thermal reoxidation on the electrical properties ofrapid thermally nitrided thin-gate oxides

The authors report a systematic study of the impact of post-nitridation rapid thermal anneals in oxygen and nitrogen on the electrical properties of MOS devices with thin gate oxides. A comparative study of the two annealing ambients has led to the formulation of qualitative models to describe the charge trapping properties of the respective gate dielectrics. Roles of the post-nitridation anneals in altering the radiation and hot-electron sensitivity of the MOS devices are investigated and explained on the basis of structural changes in the gate oxides during nitridation and subsequent annealing. The performance and reliability of MOSFETs with reoxidized nitrided gate oxides are investigated. Overall, the results indicate that reoxidized nitrided oxides show improved charge trapping properties, better resistance to radiation and hot-carrier stress, and improved high-field electron mobility in MOSFETs     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

Defects and their passivation in high K gate oxides

High dielectric constant oxides such as HfO₂ are very important as gate dielectrics in future CMOS devices. However, compared to SiO₂ they suffer from much higher defect concentrations which cause charge trapping, threshold voltage instability, and mobility degradation. The main defect is the oxygen vacancy. It has been found that fluorine is able to passivate these defects to an extent. The mechanism of defect passivation is calculated using ab-initio methods, and the general principles of defect passivation in ionic oxides are discussed.     

Simple estimation of the effect of hot-carrier degradation on scaled nMOSFETs

The influence of parasitic charge at the Si–SiO₂ interface on the characteristics of n-channel metal oxide semiconductor field effect transistors (nMOSFETs) scaled down to a feature size of 25?nm is studied. The results are that the impact of parasitic charge on threshold voltage and drain current degradation significantly decreases. Additionally, as the hot-electron injection current densities are lowered for scaled-down nMOS transistors, less charge build-up occurs. This opens the perspective to make use of alternative gate dielectrics even if they have a higher interface trap density. These materials offer the advantage of greater dielectric constants than silicon oxide, so that a physically thicker dielectric will limit the gate tunnelling current.     

Time-dependent dielectric wearout technique with temperature effect for reliability test of ultrathin (<2.0 nm) single layer and dual layer gate oxides

Ultrathin gate oxide is essential for low supply voltage and high drive current for ULSI devices. The continuous scaling of oxide thickness has been a challenge on reliability characterization with conventional time-dependent dielectric breakdown (TDDB) technique. A new technique, the time-dependent dielectric wearout (TDDW), is proposed as a more practical and effective way to measure oxide reliability and breakdown compared to conventional TDDB methodology. The wearout of oxide is defined as the gate current reaches a critical current density with the circuit operating voltage level. It is shown that although a noisy soft breakdown always exists for ultrathin oxide, with constant-voltage stressing, a big runaway can also be observed for oxides down to 1.8 nm by monitoring the I–V characteristics at a reduced voltage. Devices are found still working after soft breakdowns, but no longer functional after the big runaway. However, by applying E-model to project dielectric lifetime, it shows that the dielectric lifetime is almost infinity for the thermal oxide at 1.8 nm range. It is also demonstrated that the dual voltage TDDW technique is also able to monitor the breakdown mechanism for nitride/oxide (N/O) dual layer dielectrics.     

1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O)composites prepared by RPECVD/oxidation process

Ultrathin nitride/oxide (~1.5/0.7 nm) dual layer gate dielectrics have been formed using remote plasma enhanced CVD of nitride onto plasma-grown oxide interface layers. High accumulation capacitance (1.72 μF/cm²) is measured and the equivalent oxide thickness is 1.6 nm after quantum effect corrections. Compared to 1.6 nm oxides, a tunneling current reduction of more than 100 fold is found for devices with 1.6 nm N/O dielectrics due to increased film thickness and interface nitridation. Hole channel mobility decreases by about 5%, yielding very good P-MOSFET current drive. Excellent dielectric reliability and interface robustness are also demonstrated for P-MOSFET's with N/O dielectrics     

The performance and reliability of PMOSFET's with ultrathin siliconnitride/oxide stacked gate dielectrics with nitrided Si-SiO2interfaces prepared by remote plasma enhanced CVD and post-depositionrapid thermal annealing

Ultrathin (~1.9 nm) nitride/oxide (N/O) dual layer gate dielectrics have been prepared by the remote plasma enhanced chemical vapor deposition (RPECVD) of Si₃N₄ onto oxides. Compared to PMOSFET's with heavily doped p⁺-poly-Si gates and oxide dielectrics, devices incorporating the RPECVD stacked nitrides display reduced tunneling current, effectively no boron penetration and improved interface characteristics. By preventing boron penetration into the bulk oxide and channel region, gate dielectric reliability and short channel effects are significantly improved. The hole mobility in devices with N/O dielectrics with equivalent oxide thickness between 1.8 nm and 3.0 nm is not significantly degraded. Because nitrogen is transported to the substrate/dielectric interface during post-deposition annealing, degradation of mobility during hot carrier stressing is significantly reduced for N/O devices. Compared with oxide, the tunneling current for N/O films with ~1.9 nm equivalent oxide thickness is lower by about an order of magnitude due to the larger physical thickness. Suppression of boron transport in nitride layers is explained by a percolation model in which boron transport is blocked in sufficiently thick nitrides, and is proportional to the oxide fraction in oxynitride alloys     

Reliability and performance limitations in SiC power devices

Despite silicon carbide’s (SiC’s) high breakdown electric field, high thermal conductivity and wide bandgap, it faces certain reliability challenges when used to make conventional power device structures like power MOS-based devices, bipolar-mode diodes and thyristors, and Schottky contact-based devices operating at high temperatures. The performance and reliability issues unique to SiC discussed here include: (a) MOS channel conductance/gate dielectric reliability trade-off due to lower channel mobility as well as SiC–SiO₂ barrier lowering due to interface traps; (b) reduction in breakdown field and increased leakage current due to material defects; and (c) increased leakage current in SiC Schottky devices at high temperatures.Although a natural oxide is considered a significant advantage for realizing power MOSFETs and IGBTs in SiC, devices to date have suffered from poor inversion channel mobility. Furthermore, the high interface state density presently found in the SiC–SiO₂ system causes the barrier height between SiC and SiO₂ to be reduced, resulting in increased carrier injection in the oxide. A survey of alternative dielectrics shows that most suffer from an even smaller conduction band offset at the SiC–dielectric interface than the corresponding Silicon–dielectric interface and have a lower breakdown field strength than SiO₂. Thus, an attractive solution to reduce tunneling such as stacked dielectrics is required.In Schottky-based power devices, the reverse leakage currents are dominated by the Schottky barrier height, which is in the 0.7–1.2 eV range. Because the Schottky leakage current increases with temperature, the SiC Schottky devices have a reduction in performance at high temperature similar to that of Silcon PN junction-based devices, and they do not have the high temperature performance benefit associated with the wider bandgap of SiC.Defects in contemporary SiC wafers and epitaxial layers have also been shown to reduce critical breakdown electric field, result in higher leakage currents, and degrade the on-state performance of devices. These defects include micropipes, dislocations, grain boundaries and epitaxial defects. Optical observation of PN diodes undergoing on-state degradation shows a simultaneous formation of mobile and propagating crystal stacking faults. These faults nucleate at grain boundaries and permeate throughout the active area of the device, thus degrading device performance after extended operation.     

A methodology for the implementation of MOSFETs with a high-k dielectric gate material on the design of 90 nm technology circuits

Up to date, MOSFETs have been made through well established techniques that use SiO₂ as the gate dielectric and the related design issues are well established. The need to scale down device dimensions allowed researchers to seek for alternative materials, in order to replace SiO₂ as the gate dielectric. The implementation of such MOS devices in memory or logic circuits needs to take into account the effects that the use of the new gate dielectrics has on parameters such as the threshold voltage and the drain current. Hence, parameters such as the high dielectric constant values, extra oxide charges and process related defects at the physical level must be taken into account during the device design. As far as circuit applications are concerned, these changes may substantially affect the required performance. This paper presents and provides proposals about the issue of replacing commonly used parameters of the MOSFET modelling with new parameters, in which the presence of a gate dielectric with different properties from those of SiO₂ is taken into account. A stepwise procedure is described for the new device design. Moreover, a case study is presented which examines a memory circuit built up by such new technology devices. In particular, this paper presents and analyses the design of a DRAM cell made up of MOSFETs with an alternative gate dielectric. The 90 nm technology and the BSIM4 model equations are used to derive the single MOSFET behaviour and subsequently the DRAM circuit performance. The results are analysed and compared to those obtained from conventional SiO₂ devices. A cell layout is provided and the DRAM circuit characteristics are also presented.     

Electrical properties of MOSFET's with N2O-nitridedLPCVD SiO2 gate dielectrics

Electrical properties of MOSFETs with gate dielectrics of low-pressure chemical-vapor-deposited (LPCVD) SiO₂ nitrided in N₂O ambient are compared to those with control thermal gate oxide. N₂O nitridation of CVD oxide, combines the advantages of interfacial oxynitride growth and the defectless nature of CVD oxide. As a result, devices with N₂O-nitrided CVD oxide show considerably enhanced performance (higher effective electron mobility), improved reliability (reduced charge trapping, interface state generation, and transconductance degradation), and better time-dependent dielectric breakdown (TDDB) properties (t_BD ) compared to devices with control thermal oxide     

MOS栅氧的界面特性和辐照特性研究

通过交流电导法,对经过不同时间N₂O快速热处理(RTP)的MOS电容进行界面特性和辐照特性研究。通过电导电压曲线,分析N₂O RTP对Si-SiO₂界面陷阱电荷和氧化物陷阱电荷造成的影响。结论表明,MOS电容的Si-SiO₂界面陷阱密度随N₂O快速热处理时间先增加再降低;零偏压总剂量辐照使氧化层陷阱电荷显著增加,而Si-SiO₂界面陷阱电荷轻微减少。     

Tunneling component suppression in charge pumping measurement and reliability study for high-k gated MOSFETs

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high-k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high-k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO₂-dominated high-k gate dielectrics is like mobile defect; while that with SiO₂-dominated ones is similar to the near-interface/border trap.     

A Novel Approach in Separating the Roles of Electrons and Holes in Causing Degradation in Hf-Based MOSFET Devices by Using Stress-Anneal Technique

A novel stress-anneal approach has been investigated to separate the role of electrons and hole charge trappings in Hf-based gate oxides. It is observed that heat treatment following a stress experiments on Hf-based MOSFET can effectively eliminate electron trapping in the oxide. We also report that hole accumulation in the bulk of the Hf-based dielectrics is primarily responsible for dielectric breakdown, though both holes and electrons are trapped in the dielectrics. The Si interface quality does not seem to degrade significantly     

Power-law voltage acceleration: A key element for ultra-thin gate oxide reliability

The properties of the so-called time dependent dielectric breakdown (TDDB) of silicon dioxide-based gate dielectric for microelectronics technology have been investigated and reviewed. Experimental data covering a wide range of oxide thickness, stress voltage, temperature, and for the two bias polarities were gathered using structures with a wide range of gate oxide areas, and over very long stress times. Thickness dependence of oxide breakdown was shown to be in excellent agreement with statistical models founded in the percolation theory which explain the drastic reduction of the time-to-breakdown with decreasing oxide thickness. The voltage dependence of time-to-breakdown was found to follow a power-law behavior rather than an exponential law as commonly assumed. Our investigation on the inter-relationship between voltage and temperature dependencies of oxide breakdown reveals that a strong temperature activation with non-Arrhenius behavior is consistent with the power-law voltage dependence. The power-law voltage dependence in combination with strong temperature activation provides the most important reliability relief in compensation for the strong decrease of time-to-breakdown resulting from the reduction of the oxide thickness.Using the maximum energy of injected electrons at the anode interface as breakdown variable, we have resolved the polarity gap of time- and charge-to-breakdown (T_BD and Q_BD), confirming that the fluency and the electron energy at anode interface are the fundamental quantities controlling oxide breakdown. Combining this large database with a recently proposed cell-based analytical version of the percolation model, we extract the defect generation efficiency responsible for breakdown. Following a review of different breakdown mechanisms and models, we discuss how the release of hydrogen through the coupling between vibrational and electronic degrees of freedom can explain the power-law dependence of defect generation efficiency. On the basis of these results, a unified and global picture of oxide breakdown is constructed and the resulting model is applied to project reliability limits. In this regard, it is concluded that SiO₂-based dielectrics can provide reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable for the 50 nm technology node.     

Short-channel MOSFETs with oxynitride gate dielectrics fabricated using multiple rapid thermal processing

Short-channel MOSFETs with superior thin gate dielectrics have been successfully fabricated using multiple reactive rapid thermal processing of thermal oxides. The gate dielectrics are produced by rapid thermal nitridation (RTN) of thin thermal oxides in pure NH/sub 3/ ambient followed by rapid thermal reoxidation (RTO) in O/sub 2/ ambient. Devices fabricated with RTO/RTN gate dielectrics exhibit improved hot electron induced degradation compared to those fabricated with pure oxides. In addition, the subthreshold leakage current level of RTO/RTN devices is as good as for standard oxide devices.<>     

Fully strained Si0.75Ge0.25 epitaxial films with HfSiO gate dielectrics for high mobility channel metal-oxide semiconductor devices

The authors report on fully strained Si_0.75Ge_0.25 metal-oxide-semiconductor capacitors with HfSiO₂ high-k gate dielectric and TaN metal gate fabricated on Si substrates. Fully strained Si_0.75Ge_0.25 films are directly grown on Si substrates below the critical thickness. HfSiO₂ high-k gate dielectrics exhibit an equivalent oxide thickness of 13-18 Å with a permittivity of 17.7 and gate leakage current density lower than SiO₂ gate oxides by >100×. Interfacial oxide of the HfSiO₂/Si_0.75Ge_0.25 stack consists primarily of SiO₂ with a small amount of Ge and Hf. High performance SiGe field effect transistors are highly manufacturable with excellent electrical characteristics afforded by the fully strained HfSiO₂/SiGe gate stack.     

Characterization of ultra-thin SiO2 by capacitance-voltage and charge pumping measurements

In this paper, we present results on electrical measurements of ultra thin SiO₂ layers (from 3.5 nm down to 1.7 nm), used as gate dielectric in metal-oxide-semiconductors (MOS) devices. Capacitance-voltage (C-V) measurements and simulations on MOS capacitors have been used for extracting the electrical oxide thickness. The SiO₂/Si interface and oxide quality have been analyzed by charge pumping (CP) measurements. The mean interface traps density is measured by 2-level CP, and the energy distribution within the semiconductor bandgap of these traps are investigated by 3-level charge pumping measurements. A comparison of the energy distribution of the SiO₂/Si interface traps is made using classical and quantum simulations to extract the surface potential as a function of the gate signal. When the gate oxide thickness <3.5 nm, we prove that it is mandatory to take into account the quantum effects to obtain a more accurate energy distribution of the SiO₂/Si interface traps. We also explain the increase of the apparent interface traps density measured by 2-levels CP with the increase of the oxide thickness, for transistors made from the same technological process.     

Process damage-free damascene metal gate technology for gentle integration of epitaxially grown high-k

This paper presents the first successful attempt to integrate crystalline high-k gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness (EOT) down to 1.9 nm are discussed and compared with devices with rare-earth gate dielectrics fabricated previously in a conventional CMOS process.